DD219613A1 - ASYMMETRICAL REFRIGERATOR FOR SEMICONDUCTOR MEMORY - Google Patents

Abstract

The invention relates to an asymmetric Leseverstaerker for semiconductor memory with memory cells with arbitrary read signals. The object of the invention is to convert the read signal of such memory cells, which are preferably charge layer cells with serial auxiliary gate in drain circuit, by suitable measures to reinforce another voltage range, so that a little circuit complexity for the read circuit is created and a small clock effort is required. Fig. 1

Description

Asymmetric sense amplifier for semiconductor memory

/ Field of application of the invention

The invention relates to an asymmetrical sense amplifier for semiconductor memory, wherein the memory cells, depending on the stored information zv / ei provide any read signals. Such memory cells are for example charge-layer cells with serial auxiliary gate in drain circuit. In the presence of such cells, the hitherto customary symmetrical sensor flip-flop can not be used, since the required reference voltage of (U-dttt + ⁾ is not realizable within the matrix

In general, symmetric flip-flops are described as sense amplifiers for use in semiconductor memories from various publications. They are specifically designed to amplify small signals of dynamic memory cells. However, these flip-flops always require a reference voltage whose value should lie as accurately as possible in the middle between the signal level of a stored "0" and a stored "1" of the cells. The generation of such a reference voltage but with Schwellspannungs.aellen in the grid of the

Matrix, which is not necessary because of the symmetrical loading of the Plipflops, not possible. For this reason, asymmetric sense amplifiers find. Uses "These may be realized using enhancement transients only or using a zerotransistor. , Unfavorable it turns out that either the signal-voltage difference must be large or a complicated Jertigungst.echnologie is required, causing a high susceptibility to interference. In addition, a high number of clocks is required.

Object of the invention

The object of the invention is to convert the read signal amplifying by suitable measures in a different voltage range, so that the switching angstechnisehe effort and the number of clocks decrease.

Explanation of the essence of the invention

The invention has for its object to provide an asymmetric sense amplifier for semiconductor memories, the memory cell reading one of the stored information, a signal voltage level, the low level, and reading the other stored information, a second signal voltage level, the high level, 'Siert on the read bit-line realized'. At the same time the circuit should be applicable for any value of both signal voltage level with little clock effort. The 'sense amplifier should be designed so that only a dummy cell is required for several sense amplifiers, which provides a constant DC voltage having the value of the low level of the signal voltage, or a clock voltage corresponding to the course on the bit read line.

According to the invention, the object is achieved by an asymmetric sense amplifier for semiconductor memory. The semiconductor memory in this case contains memory cells which, depending on the stored information, two different signal voltage levels,..; Low-level or high-level, implement on the bit-read line, preferably charge-sharing lines with serial auxiliary gate. Each cell is assigned a bit read and a write bit line. The 3it read and the write bit line is associated with a discharge circuit. According to the invention, the bit read line is connected to the gate of a transistor whose drain and source regions are connected to a common node B which is connected via a capacitor to the gate of a switching transistor.

According to the invention, the drain region of a discharge transistor is connected between the capacitor and the gate of the switching transistor, connected to the gate of which a clock cycle and its source region are grounded.

According to the invention are at the node B to the capacitor, at its second terminal a clock 0 ~ is applied, and the source region of a precharge transistor, at the gate of a voltage ög ,, and at the drain region of the clock voltage 0 _R abut connected. In an embodiment of the invention, the transistor ₍ connected to the bit read line) is an enhancement transistor for realizing a non-linear, ie voltage-dependent, capacitance. [Kapazitäten In] In the embodiment of the invention, the capacitances C ₁ and Q _{2 are} voltage-independent is the source region of the switching transistor via a second used. transistor to the bit write line and this is connected via a third transistor to a data line.

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The invention is explained in more detail with reference to a Ausführüngsbeiapiels and two drawings. Show

Pig * i the asymmetric sense amplifier according to the invention according to the embodiment Pig · 2 the timing diagram. Pig. 3 the equivalent circuit diagram with capacitance characteristic

The one in Pig. 1 asymmetric sense amplifier contains matrixf'drmig arranged memory cells 1, which implement two arbitrary signal voltage level, low or high level, on the bit read line 3, depending on the information stored in the cell 1 information. The concrete pail are charge-layer cells with serial Hi-gate in drain circuit. A word line 2 is connected to the auxiliary gate, a bit read line 3 to the source, and a bit write line 4 to the memory gate. Drain of the memory cell 1, is connected to the supply voltage ü ^ w. ; ',' A 'Sntladetransistor 5, at the gate of a Vorladetakt jZL. is applied, the bit-reading line 3 connects to ground. ;

Sin Sntladetransistor 6, - at whose gate a Vorladetakt 0 ^ is applied, connects the bit-write line, 4 to ground. The bit read line 3 is connected to the gate of a transistor 7. Drain and source of this transistor 7 are connected together. At the drain and source of the transistor 7, a capacitor 13, at the zWeitem terminal a conversion clock 0 · ^ is applied, a second capacitor 14, to whose "second terminal the gate of a switching transistor 8 and V drain of a discharge transistor 15 are connected, and source of Precharge transistor 16 connected.

At the gate of the discharge transistor 15 is the clock 0y and source is connected to ground. At the gate of the precharge transistor 16 is the voltage. "CLtτ'an and drain are connected to the clock voltage 0" · The drain region of the switching transistor 8 is connected to the supply voltage U-Qj The source region of the switching transistor 8 13t via a second transistor 9, at the gate of a read clock 0 ,. is applied to the bit-write line 4 connected

The bit-write line 4 is connected via a further transistor 10, at the gate of which a data transfer clock 0 ^ m is present, to a data line 12 for inputting or outputting the information. Sin transistor 11, at the gate of which a precharge clock 0j is applied, connects the ground to the data line 12.

The operation of the sense amplifier is in connection with the in Pig. In the memory state, the word lines 2 are precharged to this potential by the clock 0 _WL = "" E "" (M * average potential = ü _DD / 2). At the same time, the precharge clock 0 ^. = ¹¹ H ", the bit-read line 3, the bit-write line 4, the data line 12 and the node A are discharged to Hull V. The node B is pre-charged with 0 _R β ¹¹ H" to Ü _BLL -U ₁ , At the beginning of the read cycle, the precharge clock becomes j ~ == ^tt L ⁿ , so that the transistors 5, 6, 11 and 15 turn off. The bit-read line 3, the bit-write line 4, the data line 12, the node A and the node B keep the potentials set there. Now, if the word line clock 0 ,,,, ^a "H", so turns on the bit-read line 3, depending on the stored information in the memory cell 1, the low or high level of the signal voltage.

With the conversion clock 0 ~ = "H", the potential at nodes A and B becomes equal to that from the

Capacities G ^ and C ₂ and the bit-read line capacitance, the gate-drain and source capacitance of the Tran'sistprs 7 and the gate-Eulk capacitance of the switching transistor 8,. According to Fig. 3a, formed capacitive voltage divider ratio, increase. The precharge transistor 16 becomes self-blocking since its gate-source voltage becomes smaller than the threshold voltage. · · .. ''. · '

In the case of reading the low level on the bit read line 3, the gate-source and drain voltage of the transistor 7 is Um. Thus, the gate-drain and source capacitance of this transistor is minimal, as shown in FIG. 3b. In the case of reading the high level, the gate-source and drain capacitance of the transistor 7, depending on the channel 'length 10 to 40 times greater, since the gate-source and drain voltage is greater than the threshold voltage U ~ . The capacitances C ^ and C are dimensioned such that in the case of reading the low level the voltage at node A is greater and in the case of reading of the high level: smaller than the threshold voltage TL, of the switching transistor 8, when the clock 0j becomes "H" At the same time, for clocking and refreshing, the clocks 0 _L = "H? and _m = 0 "H".

In the case of reading the low level, the switching transistor 8 is conductive and the Blt write line 4 and the data line 12 are charged; in the case of reading the high level, the switching transistor 8 is turned off and the bit write line 4 and the data line 12 maintain the previously set potential of zero volts.

after the word line clock 0 _,? , _T = "L", the corresponding information is written. This corresponds to a refresh of the information in all cells 1 activated by the line 2.

In the row selected by the data transfer clock 0 ™ = "H ⁿ , in addition to the refresh, the read information is output to the data line 12 (read).

When writing information, the memory cell 1 is selected by the word line 2 and the bit-write line 4. In this case, the data line Ί2 is set to the corresponding potential and via the "data transfer clock 0 ^ = Ο'Η ^Μ , this potential is applied to the Transmit bit-write line 4, for which selected line jZL = "I · ¹¹ must be.

Claims (3)

jsrfindungsanspruch 1. An asymmetric sense amplifier for semiconductor memory, in which the memory cells, depending on the stored information, provide any two read signals, preferably charge-layer cells with a serial auxiliary gate in a drain circuit, wherein the bit line is divided into a bit read and write bit line and each, is associated with a discharge circuit and wherein a, .Datenleitung is associated with a Sntladetransistor, is connected to the output of the sense amplifier and the bit write line or the write bit line only to the data line, characterized in that the bit read lead (3) is connected to the gate of a / transistor (7), whose drain and source are connected via a capacitor (14) to the gate of a switching transistor (8) are connected, wherein at drain and source ^ of the ¹ transistor (7) has a capacitor (13), at whose two-. , , tem terminal a conversion clock ($ ττ) is applied .., and source of a precharge transistor (16), at the 'gate, the reference voltage üg "and the drain a clock, flännung (fi-o) are applied, and connected to the gate of the Switching transistor (8) still another Ent-, charging transistor (15), at the gate of a clock voltage / (0-rr) and whose source is grounded. 2. Asymmetric sense amplifier according to item 1, characterized in that the reference signal required at a transistor, (16) generates outside the matrix, has the value of the low level of the signal voltage and can be used for a plurality of sense amplifiers. 3. Asymmetric sense amplifier according to item 1, characterized in that it can be used for any level of signal voltage, low and high levels. , , '. - Hierau 3 pages drawings -