DE10085617A5 - Frequenzvervielfachende Delay Locked Loop (DLL) - Google Patents

Frequenzvervielfachende Delay Locked Loop (DLL) Download PDF

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Publication number
DE10085617A5
DE10085617A5 DE2000185617 DE10085617T DE10085617A5 DE 10085617 A5 DE10085617 A5 DE 10085617A5 DE 2000185617 DE2000185617 DE 2000185617 DE 10085617 T DE10085617 T DE 10085617T DE 10085617 A5 DE10085617 A5 DE 10085617A5
Authority
DE
Germany
Prior art keywords
dll
locked loop
delay locked
frequency multiplying
multiplying delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE2000185617
Other languages
English (en)
Inventor
Paul W. DeMone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of DE10085617A5 publication Critical patent/DE10085617A5/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
    • H03K5/15046—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a tapped delay line
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
  • Manipulation Of Pulses (AREA)
DE2000185617 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop (DLL) Pending DE10085617A5 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA2,270,516 1999-04-30
CA002270516A CA2270516C (en) 1999-04-30 1999-04-30 Frequency-doubling delay locked loop

Publications (1)

Publication Number Publication Date
DE10085617A5 true DE10085617A5 (de) 2014-04-03

Family

ID=4163496

Family Applications (2)

Application Number Title Priority Date Filing Date
DE10084500.2T Expired - Fee Related DE10084500B3 (de) 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop
DE2000185617 Pending DE10085617A5 (de) 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop (DLL)

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE10084500.2T Expired - Fee Related DE10084500B3 (de) 1999-04-30 2000-05-01 Frequenzvervielfachende Delay Locked Loop

Country Status (9)

Country Link
US (7) US6441659B1 (de)
JP (3) JP2002543732A (de)
KR (1) KR100811766B1 (de)
CN (1) CN1190012C (de)
AU (1) AU4280300A (de)
CA (1) CA2270516C (de)
DE (2) DE10084500B3 (de)
GB (1) GB2363684B (de)
WO (1) WO2000067381A1 (de)

Families Citing this family (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6650661B1 (en) * 1998-06-15 2003-11-18 International Business Machines Corporation System that compensates for variances due to process and temperature changes
US7515896B1 (en) 1998-10-21 2009-04-07 Parkervision, Inc. Method and system for down-converting an electromagnetic signal, and transforms for same, and aperture relationships
US6061551A (en) 1998-10-21 2000-05-09 Parkervision, Inc. Method and system for down-converting electromagnetic signals
US6542722B1 (en) * 1998-10-21 2003-04-01 Parkervision, Inc. Method and system for frequency up-conversion with variety of transmitter configurations
US7039372B1 (en) 1998-10-21 2006-05-02 Parkervision, Inc. Method and system for frequency up-conversion with modulation embodiments
US7027786B1 (en) 1998-10-21 2006-04-11 Parkervision, Inc. Carrier and clock recovery using universal frequency translation
US6370371B1 (en) 1998-10-21 2002-04-09 Parkervision, Inc. Applications of universal frequency translation
US6813485B2 (en) * 1998-10-21 2004-11-02 Parkervision, Inc. Method and system for down-converting and up-converting an electromagnetic signal, and transforms for same
US6873836B1 (en) 1999-03-03 2005-03-29 Parkervision, Inc. Universal platform module and methods and apparatuses relating thereto enabled by universal frequency translation technology
US6879817B1 (en) 1999-04-16 2005-04-12 Parkervision, Inc. DC offset, re-radiation, and I/Q solutions using universal frequency translation technology
US6853690B1 (en) 1999-04-16 2005-02-08 Parkervision, Inc. Method, system and apparatus for balanced frequency up-conversion of a baseband signal and 4-phase receiver and transceiver embodiments
US7110435B1 (en) * 1999-03-15 2006-09-19 Parkervision, Inc. Spread spectrum applications of universal frequency translation
US7693230B2 (en) 1999-04-16 2010-04-06 Parkervision, Inc. Apparatus and method of differential IQ frequency up-conversion
US7065162B1 (en) * 1999-04-16 2006-06-20 Parkervision, Inc. Method and system for down-converting an electromagnetic signal, and transforms for same
US7110444B1 (en) 1999-08-04 2006-09-19 Parkervision, Inc. Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementations
CA2270516C (en) * 1999-04-30 2009-11-17 Mosaid Technologies Incorporated Frequency-doubling delay locked loop
DE19934501C1 (de) * 1999-07-22 2000-11-09 Siemens Ag Synchroner integrierter Speicher
US8295406B1 (en) 1999-08-04 2012-10-23 Parkervision, Inc. Universal platform module for a plurality of communication protocols
US7082171B1 (en) 1999-11-24 2006-07-25 Parkervision, Inc. Phase shifting applications of universal frequency translation
US7010286B2 (en) 2000-04-14 2006-03-07 Parkervision, Inc. Apparatus, system, and method for down-converting and up-converting electromagnetic signals
US6654900B1 (en) * 2000-04-19 2003-11-25 Sigmatel, Inc. Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements
US7010559B2 (en) 2000-11-14 2006-03-07 Parkervision, Inc. Method and apparatus for a parallel correlator and applications thereof
US7454453B2 (en) 2000-11-14 2008-11-18 Parkervision, Inc. Methods, systems, and computer program products for parallel correlation and applications thereof
WO2002043245A2 (en) * 2000-11-23 2002-05-30 Koninklijke Philips Electronics N.V. Clock generation circuit and integrated circuit for reproducing an audio signal comprising such a clock generation circuit
KR100384781B1 (ko) * 2000-12-29 2003-05-22 주식회사 하이닉스반도체 듀티 사이클 보정 회로
WO2002095943A2 (en) * 2001-05-21 2002-11-28 Vasily Grigorievich Atyunin Programmable self-calibrating vernier and method
US6788113B2 (en) * 2001-06-19 2004-09-07 Fujitsu Limited Differential signal output apparatus, semiconductor integrated circuit apparatus having the differential signal output apparatus, and differential signal transmission system
US7072427B2 (en) 2001-11-09 2006-07-04 Parkervision, Inc. Method and apparatus for reducing DC offsets in a communication system
US6653876B2 (en) * 2002-04-23 2003-11-25 Broadcom Corporation Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
US6788045B2 (en) * 2002-05-17 2004-09-07 Sun Microsystems, Inc. Method and apparatus for calibrating a delay locked loop charge pump current
US7321640B2 (en) * 2002-06-07 2008-01-22 Parkervision, Inc. Active polyphase inverter filter for quadrature signal generation
US6753709B2 (en) * 2002-06-28 2004-06-22 Agere Systems Inc. Digital clock rate multiplier method and apparatus
US7379883B2 (en) 2002-07-18 2008-05-27 Parkervision, Inc. Networking methods and systems
US7460584B2 (en) 2002-07-18 2008-12-02 Parkervision, Inc. Networking methods and systems
US20040047441A1 (en) * 2002-09-11 2004-03-11 Gauthier Claude R. Source synchronous interface using a dual loop delay locked loop and variable analog data delay lines
US20040090248A1 (en) * 2002-09-20 2004-05-13 Eastman Kodak Company Programmable timing generator with offset and width control using delay lock loop
US20040057547A1 (en) * 2002-09-23 2004-03-25 Agere Systems Inc. Fractional frequency clock signal synthesizer and method of operation thereof
DE10249886B4 (de) * 2002-10-25 2005-02-10 Sp3D Chip Design Gmbh Verfahren und Vorrichtung zum Erzeugen eines Taktsignals mit vorbestimmten Taktsingaleigenschaften
US6774691B2 (en) * 2003-01-07 2004-08-10 Infineon Technologies Ag High resolution interleaved delay chain
US7120817B2 (en) * 2003-05-29 2006-10-10 Intel Corporation Method of signal distribution based on a standing wave within a closed loop path
WO2005050776A2 (en) * 2003-11-13 2005-06-02 California Institute Of Technology Monolithic silicon-based phased arrays for communications and radars
US7009441B2 (en) * 2004-02-10 2006-03-07 Alan Fiedler Phase multiplier circuit
CN1295870C (zh) * 2004-02-13 2007-01-17 中兴通讯股份有限公司 一种时钟倍频电路
US7123063B2 (en) * 2004-04-28 2006-10-17 Broadcom Corporation Supply tracking clock multiplier
KR100618825B1 (ko) * 2004-05-12 2006-09-08 삼성전자주식회사 지연 동기 루프를 이용하여 내부 신호를 측정하는집적회로 장치 및 그 방법
JPWO2006030905A1 (ja) * 2004-09-17 2008-05-15 日本電気株式会社 クロック生成回路、及びクロック生成方法
KR100709438B1 (ko) * 2004-09-20 2007-04-18 주식회사 하이닉스반도체 내부 클럭 발생 장치
US7202719B2 (en) * 2004-09-30 2007-04-10 Motorola, Inc. Method and apparatus for frequency synthesis
US7274236B2 (en) * 2005-04-15 2007-09-25 Micron Technology, Inc. Variable delay line with multiple hierarchy
US7453301B1 (en) 2005-08-05 2008-11-18 Xilinx, Inc. Method of and circuit for phase shifting a clock signal
US7453297B1 (en) * 2005-08-05 2008-11-18 Xilinx, Inc. Method of and circuit for deskewing clock signals in an integrated circuit
US7295048B2 (en) * 2005-09-22 2007-11-13 International Business Machines Corporation Method and apparatus for generating spread spectrum clock signals having harmonic emission suppressions
US7227809B2 (en) * 2005-10-14 2007-06-05 Micron Technology, Inc. Clock generator having a delay locked loop and duty cycle correction circuit in a parallel configuration
US20070164797A1 (en) * 2005-12-20 2007-07-19 Law Hon-Mo R Method and apparatus to eliminate clock phase error in a multi-phase clock circuit
US7423465B2 (en) * 2006-01-27 2008-09-09 Micron Technology, Inc. Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit
US8073890B2 (en) 2006-02-22 2011-12-06 Micron Technology, Inc. Continuous high-frequency event filter
US7951008B2 (en) * 2006-03-03 2011-05-31 Igt Non-volatile memory management technique implemented in a gaming machine
KR100839499B1 (ko) * 2006-12-22 2008-06-19 삼성전자주식회사 딜레이 제어 장치 및 방법
TWI329873B (en) * 2007-02-15 2010-09-01 Realtek Semiconductor Corp Sampling circuit and method
US7724049B2 (en) * 2007-02-28 2010-05-25 Micron Technology, Inc. Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal
JP4825710B2 (ja) * 2007-03-16 2011-11-30 株式会社リコー 多相クロック生成回路およびシリアルデータ受信回路
US7759997B2 (en) * 2008-06-27 2010-07-20 Microsoft Corporation Multi-phase correction circuit
US7821316B2 (en) 2008-08-29 2010-10-26 Microsoft Corporation Multiphase clock generator with enhanced phase control
KR101046244B1 (ko) * 2009-07-31 2011-07-04 주식회사 하이닉스반도체 반도체 집적 회로의 클럭 생성 장치
US8949069B2 (en) * 2009-12-16 2015-02-03 Intel Corporation Position determination based on propagation delay differences of multiple signals received at multiple sensors
US8258837B2 (en) * 2009-12-17 2012-09-04 Intel Corporation Controlled clock phase generation
KR101685630B1 (ko) * 2010-03-02 2016-12-13 삼성전자주식회사 2상 딜레이 라인과 듀티 교정회로를 갖는 지연 동기 루프 및 그의 듀티 교정방법
KR101212724B1 (ko) * 2010-05-31 2012-12-14 에스케이하이닉스 주식회사 클럭발생회로 및 그를 이용한 지연고정루프
US8411258B2 (en) 2010-12-22 2013-04-02 Intel Corporation Systems and methods for determining position using light sources
CN102594307B (zh) * 2011-01-17 2015-09-30 智原科技股份有限公司 信号延迟装置与方法及使用此信号延迟装置的存储器装置
CN102158205B (zh) * 2011-03-14 2014-03-12 龙芯中科技术有限公司 一种时钟倍频器和装置及时钟倍频方法
US8917131B2 (en) 2011-12-09 2014-12-23 Micron Technology, Inc. Slew rate modulation
JP5966438B2 (ja) 2012-02-29 2016-08-10 富士通株式会社 伝送装置及び伝送方法
CN102684684B (zh) * 2012-04-27 2015-01-21 清华大学深圳研究生院 多通道前向时钟高速串行接口的正交时钟产生电路
US9077348B1 (en) * 2012-09-14 2015-07-07 Maxim Integrated Products, Inc. Fractional clock generator
US8917123B2 (en) * 2013-03-29 2014-12-23 Stmicroelectronics International N.V. Integrated circuit with reduced power consumption in a test mode, and related methods
WO2014193334A1 (en) 2013-05-26 2014-12-04 Intel Corporation Apparatus, system and method of communicating positioning information
US9891279B2 (en) 2013-06-17 2018-02-13 Stmicroelectronics International N.V. Managing IR drop
WO2015005912A1 (en) 2013-07-10 2015-01-15 Intel Corporation Apparatus, system and method of communicating positioning transmissions
US9065449B2 (en) * 2013-10-28 2015-06-23 Avago Technologies General Ip (Singapore) Pte. Ltd. High-speed divide-by-1.5 circuit with 50 percent duty cycle
TWI528724B (zh) * 2014-01-08 2016-04-01 晨星半導體股份有限公司 信號發送方法與相關之信號發送器
US9191193B1 (en) 2014-07-18 2015-11-17 Qualcomm Incorporated Clock synchronization
US9729157B2 (en) * 2015-02-13 2017-08-08 Macom Technology Solutions Holdings, Inc. Variable clock phase generation method and system
US10594810B2 (en) * 2015-04-06 2020-03-17 International Business Machines Corporation Enhancing natural language processing query/answer systems using social network analysis
GB2542200B (en) 2015-09-14 2018-12-26 Jaguar Land Rover Ltd Sensor and method
CN105406838B (zh) * 2015-12-02 2018-06-12 重庆西南集成电路设计有限责任公司 数字倍频电路及修正时钟占空比的方法
KR20180060328A (ko) * 2016-11-28 2018-06-07 삼성전자주식회사 멀티 모달 입력을 처리하는 전자 장치, 멀티 모달 입력을 처리하는 방법 및 멀티 모달 입력을 처리하는 서버
KR102439583B1 (ko) * 2018-04-30 2022-09-05 에스케이하이닉스 주식회사 메모리 장치 및 그의 신호 전송 회로
JP7393079B2 (ja) * 2019-03-26 2023-12-06 ラピスセミコンダクタ株式会社 半導体装置
US10911165B1 (en) * 2019-12-23 2021-02-02 Infineon Technologies Ag System and method for calibrating a frequency doubler
WO2022110235A1 (zh) * 2020-11-30 2022-06-02 华为技术有限公司 芯片及时钟检测方法
US12191862B2 (en) 2021-12-24 2025-01-07 Macom Technology Solutions Holdings, Inc. Hybrid phase-interpolator
CN114024506B (zh) * 2022-01-06 2022-04-19 浙江赛思电子科技有限公司 开环型晶体振荡器电路

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54125558U (de) * 1978-02-22 1979-09-01
JPS60204121A (ja) * 1984-03-29 1985-10-15 Fujitsu Ltd 位相同期回路
US4694197A (en) * 1986-01-06 1987-09-15 Rca Corporation Control signal generator
JPS6359212A (ja) * 1986-08-29 1988-03-15 Toshiba Corp ラツチ回路
US4922141A (en) * 1986-10-07 1990-05-01 Western Digital Corporation Phase-locked loop delay line
JPS63211919A (ja) * 1987-02-27 1988-09-05 Nec Corp クロツク発生回路
US5059924A (en) * 1988-11-07 1991-10-22 Level One Communications, Inc. Clock adapter using a phase locked loop configured as a frequency multiplier with a non-integer feedback divider
US5077529A (en) * 1989-07-19 1991-12-31 Level One Communications, Inc. Wide bandwidth digital phase locked loop with reduced low frequency intrinsic jitter
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
GB2260631B (en) 1991-10-17 1995-06-28 Intel Corp Microprocessor 2X core design
US5412349A (en) 1992-03-31 1995-05-02 Intel Corporation PLL clock generator integrated with microprocessor
US5336939A (en) * 1992-05-08 1994-08-09 Cyrix Corporation Stable internal clock generation for an integrated circuit
DE69327612T2 (de) * 1992-05-08 2000-08-31 National Semiconductor Corp., Richardson Schaltung und Verfahren zur Generierung eines stabilen Taktsignals mit Frequenzvervielfachung
JPH06202759A (ja) 1993-01-05 1994-07-22 Funai Electric Co Ltd ポータブルコンピュータ
US5345186A (en) * 1993-01-19 1994-09-06 Credence Systems Corporation Retriggered oscillator for jitter-free phase locked loop frequency synthesis
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
FR2714550B1 (fr) * 1993-12-24 1996-02-02 Bull Sa Arbre de portes logiques OU-Exclusif et multiplieur de fréquence l'incorporant.
JPH07202649A (ja) * 1993-12-27 1995-08-04 Toshiba Corp 逓倍回路
AU1841895A (en) 1994-02-15 1995-08-29 Rambus Inc. Delay-locked loop
JP3378667B2 (ja) * 1994-08-10 2003-02-17 株式会社アドバンテスト 周期クロックの可変遅延回路
US5815016A (en) * 1994-09-02 1998-09-29 Xilinx, Inc. Phase-locked delay loop for clock correction
JP2734380B2 (ja) * 1994-09-06 1998-03-30 日本電気株式会社 電圧制御発振器およびフェーズロックドループ回路
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
JPH08223003A (ja) * 1995-02-16 1996-08-30 Kawasaki Steel Corp クロック逓倍回路
US5638016A (en) * 1995-04-18 1997-06-10 Cyrix Corporation Adjustable duty cycle clock generator
US5786732A (en) * 1995-10-24 1998-07-28 Vlsi Technology, Inc. Phase locked loop circuitry including a multiple frequency output voltage controlled oscillator circuit
JP3442924B2 (ja) 1996-04-01 2003-09-02 株式会社東芝 周波数逓倍回路
JP3323054B2 (ja) * 1996-04-01 2002-09-09 株式会社東芝 周波数逓倍回路
US5777501A (en) * 1996-04-29 1998-07-07 Mosaid Technologies Incorporated Digital delay line for a reduced jitter digital delay lock loop
JP3700989B2 (ja) * 1996-12-27 2005-09-28 本田技研工業株式会社 信号処理装置
JPH10215153A (ja) * 1997-01-30 1998-08-11 Toshiba Corp クロック逓倍回路及び半導体集積回路
KR100214559B1 (ko) * 1997-02-20 1999-08-02 구본준 주파수 배가기
US6369624B1 (en) * 1998-11-03 2002-04-09 Altera Corporation Programmable phase shift circuitry
CA2270516C (en) 1999-04-30 2009-11-17 Mosaid Technologies Incorporated Frequency-doubling delay locked loop
US8085074B1 (en) * 2010-10-11 2011-12-27 Texas Instruments Incorporated Fast-locking delay locked loop

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DE10084500B3 (de) 2014-02-13
US8283959B2 (en) 2012-10-09
US8558593B2 (en) 2013-10-15
WO2000067381A1 (en) 2000-11-09
CA2270516C (en) 2009-11-17
US6441659B1 (en) 2002-08-27
KR100811766B1 (ko) 2008-03-10
US7746136B2 (en) 2010-06-29
US20140009196A1 (en) 2014-01-09
US7456666B2 (en) 2008-11-25
US20060261866A1 (en) 2006-11-23
AU4280300A (en) 2000-11-17
CA2270516A1 (en) 2000-10-30
GB2363684A (en) 2002-01-02
JP2010074859A (ja) 2010-04-02
US20130015898A1 (en) 2013-01-17
JP2002543732A (ja) 2002-12-17
DE10084500T1 (de) 2002-06-27
CN1349683A (zh) 2002-05-15
US20030042947A1 (en) 2003-03-06
KR20020018660A (ko) 2002-03-08
US7116141B2 (en) 2006-10-03
GB2363684B (en) 2003-07-16
GB0125097D0 (en) 2001-12-12
US20090039931A1 (en) 2009-02-12
US20100225370A1 (en) 2010-09-09
CN1190012C (zh) 2005-02-16
JP4619446B2 (ja) 2011-01-26
JP2011019281A (ja) 2011-01-27
JP4677511B2 (ja) 2011-04-27
US8754687B2 (en) 2014-06-17

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