DE3679698D1 - Mos-kondensator und verfahren zu seiner herstellung. - Google Patents

Mos-kondensator und verfahren zu seiner herstellung.

Info

Publication number
DE3679698D1
DE3679698D1 DE8686302450T DE3679698T DE3679698D1 DE 3679698 D1 DE3679698 D1 DE 3679698D1 DE 8686302450 T DE8686302450 T DE 8686302450T DE 3679698 T DE3679698 T DE 3679698T DE 3679698 D1 DE3679698 D1 DE 3679698D1
Authority
DE
Germany
Prior art keywords
production
mos capacitor
mos
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686302450T
Other languages
English (en)
Inventor
Seiji Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE3679698D1 publication Critical patent/DE3679698D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H10D1/665—Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE8686302450T 1985-04-03 1986-04-02 Mos-kondensator und verfahren zu seiner herstellung. Expired - Lifetime DE3679698D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60070278A JP2604705B2 (ja) 1985-04-03 1985-04-03 Ｍｏｓキヤパシタの製造方法

Publications (1)

Publication Number Publication Date
DE3679698D1 true DE3679698D1 (de) 1991-07-18

Family

ID=13426872

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686302450T Expired - Lifetime DE3679698D1 (de) 1985-04-03 1986-04-02 Mos-kondensator und verfahren zu seiner herstellung.

Country Status (4)

Country Link
US (1) US4797719A (de)
EP (1) EP0197762B1 (de)
JP (1) JP2604705B2 (de)
DE (1) DE3679698D1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2590867B2 (ja) * 1987-03-27 1997-03-12 ソニー株式会社 メモリ装置の製造方法
JPH01287956A (ja) * 1987-07-10 1989-11-20 Toshiba Corp 半導体記憶装置およびその製造方法
JPH01128559A (ja) * 1987-11-13 1989-05-22 Fujitsu Ltd 半導体装置及びその製造方法
US4896293A (en) * 1988-06-09 1990-01-23 Texas Instruments Incorporated Dynamic ram cell with isolated trench capacitors
US4958318A (en) * 1988-07-08 1990-09-18 Eliyahou Harari Sidewall capacitor DRAM cell
US5143861A (en) * 1989-03-06 1992-09-01 Sgs-Thomson Microelectronics, Inc. Method making a dynamic random access memory cell with a tungsten plug
KR920004028B1 (ko) * 1989-11-20 1992-05-22 삼성전자 주식회사 반도체 장치 및 그 제조방법
US5256588A (en) * 1992-03-23 1993-10-26 Motorola, Inc. Method for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cell
US5429978A (en) * 1994-06-22 1995-07-04 Industrial Technology Research Institute Method of forming a high density self-aligned stack in trench
US6222218B1 (en) 1998-09-14 2001-04-24 International Business Machines Corporation DRAM trench
EP0996149A1 (de) * 1998-10-23 2000-04-26 STMicroelectronics S.r.l. Herstellungsverfahren für eine Oxidschicht mit grosser Dicke
JP3580719B2 (ja) * 1999-03-03 2004-10-27 株式会社東芝 半導体記憶装置及びその製造方法
KR20070105710A (ko) * 2006-04-27 2007-10-31 윤욱현 모스 커패시터 및 그 제조 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58137245A (ja) * 1982-02-10 1983-08-15 Hitachi Ltd 大規模半導体メモリ
JPS5982761A (ja) * 1982-11-04 1984-05-12 Hitachi Ltd 半導体メモリ
JPS59106146A (ja) * 1982-12-10 1984-06-19 Hitachi Ltd 半導体メモリ
JPS59161860A (ja) * 1983-03-07 1984-09-12 Hitachi Ltd 半導体メモリ装置
JPH0666436B2 (ja) * 1983-04-15 1994-08-24 株式会社日立製作所 半導体集積回路装置
JPS59191374A (ja) * 1983-04-15 1984-10-30 Hitachi Ltd 半導体集積回路装置
JPS6038855A (ja) * 1983-08-12 1985-02-28 Hitachi Ltd 半導体装置およびその製造方法
JPS6023506B2 (ja) * 1983-11-21 1985-06-07 株式会社日立製作所 半導体記憶装置
JPH0665225B2 (ja) * 1984-01-13 1994-08-22 株式会社東芝 半導体記憶装置の製造方法

Also Published As

Publication number Publication date
EP0197762A2 (de) 1986-10-15
JP2604705B2 (ja) 1997-04-30
EP0197762A3 (en) 1987-08-19
US4797719A (en) 1989-01-10
EP0197762B1 (de) 1991-06-12
JPS61229349A (ja) 1986-10-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee