DE69123473D1 - Schaltungsanordnung zum Ableiten eines Bitsynchronisierungssignals mittels Rahmensynchronisation - Google Patents

Schaltungsanordnung zum Ableiten eines Bitsynchronisierungssignals mittels Rahmensynchronisation

Info

Publication number
DE69123473D1
DE69123473D1 DE69123473T DE69123473T DE69123473D1 DE 69123473 D1 DE69123473 D1 DE 69123473D1 DE 69123473 T DE69123473 T DE 69123473T DE 69123473 T DE69123473 T DE 69123473T DE 69123473 D1 DE69123473 D1 DE 69123473D1
Authority
DE
Germany
Prior art keywords
deriving
circuit arrangement
synchronization signal
frame synchronization
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69123473T
Other languages
English (en)
Other versions
DE69123473T2 (de
Inventor
Mikio Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE69123473D1 publication Critical patent/DE69123473D1/de
Publication of DE69123473T2 publication Critical patent/DE69123473T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE69123473T 1990-03-08 1991-03-07 Schaltungsanordnung zum Ableiten eines Bitsynchronisierungssignals mittels Rahmensynchronisation Expired - Fee Related DE69123473T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5489190A JP2512586B2 (ja) 1990-03-08 1990-03-08 フレ―ム同期依存型ビット同期抽出回路

Publications (2)

Publication Number Publication Date
DE69123473D1 true DE69123473D1 (de) 1997-01-23
DE69123473T2 DE69123473T2 (de) 1997-04-30

Family

ID=12983218

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69123473T Expired - Fee Related DE69123473T2 (de) 1990-03-08 1991-03-07 Schaltungsanordnung zum Ableiten eines Bitsynchronisierungssignals mittels Rahmensynchronisation

Country Status (5)

Country Link
US (1) US5259004A (de)
EP (1) EP0445806B1 (de)
JP (1) JP2512586B2 (de)
CA (1) CA2037739C (de)
DE (1) DE69123473T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5694428A (en) * 1992-03-12 1997-12-02 Ntp Incorporated Transmitting circuitry for serial transmission of encoded information
US5436937A (en) * 1993-02-01 1995-07-25 Motorola, Inc. Multi-mode digital phase lock loop
JPH0779209A (ja) * 1993-09-08 1995-03-20 Fujitsu Ltd フレーム／マルチフレーム位相補正方式
US5463351A (en) * 1994-09-29 1995-10-31 Motorola, Inc. Nested digital phase lock loop
JP3311517B2 (ja) * 1994-10-20 2002-08-05 富士通株式会社 位相比較型ビット同期確立回路
JPH08195740A (ja) * 1995-01-18 1996-07-30 Nec Corp ビット同期回路
JP3467888B2 (ja) * 1995-02-08 2003-11-17 三菱電機株式会社 受信装置及び送受信装置
US5598448A (en) * 1995-03-06 1997-01-28 Motorola Inc. Method and apparatus for controlling a digital phase lock loop and within a cordless telephone
US6169772B1 (en) * 1995-04-07 2001-01-02 Via-Cyrix, Inc. Stretching setup and hold times in synchronous designs
US6885715B1 (en) * 1998-07-29 2005-04-26 Intel Corporation Method and apparatus for synchronizing a network link
US6643788B1 (en) * 1998-11-30 2003-11-04 Raytheon Company Method for detecting a number of consecutive valid data frames and advancing into a lock mode to monitor synchronization patterns within a synchronization window
JP3727206B2 (ja) * 1999-11-11 2005-12-14 Ｎｅｃエレクトロニクス株式会社 クロック乗換回路及びその方法
JP4425945B2 (ja) * 2007-03-20 2010-03-03 富士通株式会社 トランスポンダユニット、トランスポンダユニット制御装置、トランスポンダユニット制御方法およびトランスポンダユニット制御プログラム
KR100894486B1 (ko) * 2007-11-02 2009-04-22 주식회사 하이닉스반도체 디지털 필터, 클록 데이터 복구 회로 및 그 동작방법, 반도체 메모리 장치 및 그의 동작방법
JP5238980B2 (ja) * 2009-10-28 2013-07-17 有限会社アール・シー・エス 瞬時に同期を確立しかつ保持できる同期発振器
US8730251B2 (en) * 2010-06-07 2014-05-20 Apple Inc. Switching video streams for a display without a visible interruption
JP2012182594A (ja) * 2011-02-28 2012-09-20 Nec Corp 光送受信システム及び光受信装置
US8907707B2 (en) * 2013-03-01 2014-12-09 Laurence H. Cooke Aligning multiple chip input signals using digital phase lock loops
US8593191B1 (en) * 2013-03-01 2013-11-26 Laurence H. Cooke Aligning multiple chip input signals using digital phase lock loops
JP6377298B2 (ja) * 2016-04-19 2018-08-22 三菱電機株式会社 スペクトラム拡散信号受信装置および拡散符号の初期化方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3671776A (en) * 1970-05-01 1972-06-20 Xerox Corp Digital signal synchronizing system
JPS626548A (ja) * 1985-07-03 1987-01-13 Hitachi Ltd タイミング信号抽出回路
US4795985A (en) * 1986-04-01 1989-01-03 Hewlett-Packard Company Digital phase lock loop
US4694259A (en) * 1986-09-29 1987-09-15 Laser Magnetic Storage International Company Data tracking clock recovery system having media speed variation compensation
EP0262609A3 (de) * 1986-09-30 1990-04-04 Siemens Aktiengesellschaft Digitaler Phasenregelkreis
US4933959A (en) * 1989-05-08 1990-06-12 Datatape Incorporated Tracking bit synchronizer

Also Published As

Publication number Publication date
EP0445806A3 (en) 1992-12-09
CA2037739C (en) 1995-11-21
US5259004A (en) 1993-11-02
EP0445806B1 (de) 1996-12-11
DE69123473T2 (de) 1997-04-30
JP2512586B2 (ja) 1996-07-03
EP0445806A2 (de) 1991-09-11
CA2037739A1 (en) 1991-09-09
JPH03258048A (ja) 1991-11-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee