ECSP920837A - Computador personal con control de reseteo del procesador - Google Patents

Computador personal con control de reseteo del procesador

Info

Publication number
ECSP920837A
ECSP920837A EC1992000837A ECSP920837A ECSP920837A EC SP920837 A ECSP920837 A EC SP920837A EC 1992000837 A EC1992000837 A EC 1992000837A EC SP920837 A ECSP920837 A EC SP920837A EC SP920837 A ECSP920837 A EC SP920837A
Authority
EC
Ecuador
Prior art keywords
bus
local processor
microprocessor
interface controller
local
Prior art date
Application number
EC1992000837A
Other languages
English (en)
Inventor
Daniel Paul Fuoco
Luis Antonio Hernandez
Eric Mathisen
Dennis Lee Moeller
Jonathan Henry Raymond
Esmaeil Tashakori
Original Assignee
Internat Bussiness Machines Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Internat Bussiness Machines Co filed Critical Internat Bussiness Machines Co
Publication of ECSP920837A publication Critical patent/ECSP920837A/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)
  • Retry When Errors Occur (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

Un sistema de computador personal que comprende: un bus de alta velocidad con un procesador local de información. un bus de entrada/salida de información; un microprocesador reseteable acoplado directamente a dicho bus de procesador local; y un controlador de interfase del bus acoplado directamente a dicho bus de procesador local; y un controlador de interfase del bus acoplado directamente a dicho bus de procesador local y directamente a dicho bus de entrada/salida de información para proveer de comunicación entre dicho bus de procesador local y dicho bus de entrada/salida de información, dicho controlador de interface del bus arbitrando entre dicho microprocesador reseteable y cualquier otro aditamento matriz acoplado directamente a dicho bus de procesador local para accesar a dicho bus de procesador local y, arbitrar entre dicho bus de procesador local y cualquier mecanismo acoplado directamente a dicho bus de entrada/salida de información para accesar a dicho bus de entrada/salida de información, dicho controlador de interface del bus reconoce luego la recepción de una señal de reseteo para iniciar un reseteo de dicho microprocesador y difiere la entrega de una señal de reseteo a dicho microprocesador hasta que el controlador de interface de dicho bus haya bloqueado el acceso a dicho bus de procesador local y dicho bus de entrada/salida por cualquier otro de los mecanismos de dicho microprocesador.
EC1992000837A 1991-05-28 1992-05-27 Computador personal con control de reseteo del procesador ECSP920837A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70649091A 1991-05-28 1991-05-28

Publications (1)

Publication Number Publication Date
ECSP920837A true ECSP920837A (es) 1993-07-29

Family

ID=24837825

Family Applications (1)

Application Number Title Priority Date Filing Date
EC1992000837A ECSP920837A (es) 1991-05-28 1992-05-27 Computador personal con control de reseteo del procesador

Country Status (18)

Country Link
US (1) US5630078A (es)
EP (1) EP0518502B1 (es)
JP (1) JPH0752379B2 (es)
KR (1) KR950005214B1 (es)
CN (1) CN1030944C (es)
AT (1) ATE182697T1 (es)
AU (1) AU661842B2 (es)
BR (1) BR9201917A (es)
CA (1) CA2064163C (es)
DE (1) DE69229656T2 (es)
EC (1) ECSP920837A (es)
FI (1) FI922349A7 (es)
MX (1) MX9202495A (es)
MY (1) MY110949A (es)
NO (1) NO922090L (es)
SG (1) SG43727A1 (es)
TW (1) TW234178B (es)
UY (1) UY23414A1 (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6219754B1 (en) 1995-06-07 2001-04-17 Advanced Micro Devices Inc. Processor with decompressed video bus
US7562265B2 (en) * 2004-03-23 2009-07-14 International Business Machines Corporation Method, apparatus and program storage device for providing self-quiesced logic to handle an error recovery instruction
KR100731208B1 (ko) 2004-12-24 2007-06-20 한국항공우주연구원 로컬 버스를 이용한 통신 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168527A (ja) * 1983-03-16 1984-09-22 Sharp Corp 電源制御方式
US5007014A (en) * 1984-01-11 1991-04-09 Sharp Kabushiki Kaisha Reset circuit for electronic apparatus
JPS62106524A (ja) * 1985-11-01 1987-05-18 Clarion Co Ltd 車載用の機器のマイクロコンピユ−タリセツト回路
US5125088A (en) * 1986-09-08 1992-06-23 Compaq Computer Corporation Computer system speed control at continuous processor speed
US4787032A (en) * 1986-09-08 1988-11-22 Compaq Computer Corporation Priority arbitration circuit for processor access
US4811200A (en) * 1987-05-12 1989-03-07 Motorola, Inc. Multiple microprocessor watchdog system
JPH0289154A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 情報処理システム
US5170481A (en) * 1989-06-19 1992-12-08 International Business Machines Corporation Microprocessor hold and lock circuitry
CA2027799A1 (en) * 1989-11-03 1991-05-04 David A. Miller Method and apparatus for independently resetting processors and cache controllers in multiple processor systems
US5148380A (en) * 1990-08-27 1992-09-15 Acer Incorporated Method and apparatus for conserving power in a data processing system

Also Published As

Publication number Publication date
DE69229656T2 (de) 2000-03-02
NO922090L (no) 1992-11-30
CN1067125A (zh) 1992-12-16
US5630078A (en) 1997-05-13
KR950005214B1 (ko) 1995-05-22
KR920022077A (ko) 1992-12-19
ATE182697T1 (de) 1999-08-15
CA2064163A1 (en) 1992-11-29
FI922349A0 (fi) 1992-05-22
CN1030944C (zh) 1996-02-07
EP0518502B1 (en) 1999-07-28
JPH05134784A (ja) 1993-06-01
AU661842B2 (en) 1995-08-10
BR9201917A (pt) 1993-01-12
UY23414A1 (es) 1992-05-27
FI922349A7 (fi) 1992-11-29
MY110949A (en) 1999-07-31
CA2064163C (en) 1998-04-14
DE69229656D1 (de) 1999-09-02
NO922090D0 (no) 1992-05-26
MX9202495A (es) 1992-11-01
TW234178B (es) 1994-11-11
SG43727A1 (en) 1997-11-14
EP0518502A1 (en) 1992-12-16
AU1519692A (en) 1992-12-03
JPH0752379B2 (ja) 1995-06-05

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