EP0036494A2 - Circuit semiconducteur intégré du type MOS - Google Patents

Circuit semiconducteur intégré du type MOS Download PDF

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Publication number
EP0036494A2
EP0036494A2 EP81101324A EP81101324A EP0036494A2 EP 0036494 A2 EP0036494 A2 EP 0036494A2 EP 81101324 A EP81101324 A EP 81101324A EP 81101324 A EP81101324 A EP 81101324A EP 0036494 A2 EP0036494 A2 EP 0036494A2
Authority
EP
European Patent Office
Prior art keywords
substrate bias
clock generator
voltage
circuit
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81101324A
Other languages
German (de)
English (en)
Other versions
EP0036494B1 (fr
EP0036494A3 (en
Inventor
Kurt Dr. Hoffmann
Dieter Dipl.-Ing. Kantz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0036494A2 publication Critical patent/EP0036494A2/fr
Publication of EP0036494A3 publication Critical patent/EP0036494A3/de
Application granted granted Critical
Publication of EP0036494B1 publication Critical patent/EP0036494B1/fr
Expired legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators

Definitions

  • the invention relates to a monolithically integrated digital semiconductor circuit with capacitively controlled field-effect transistors and with a clock generator which supplies the clock pulses required for controlling the operation of the actual digital semiconductor circuit, in which supply connections to which the actual digital semiconductor circuit together with the clock generator acted upon by a potential supplied by a DC voltage source receiving semiconductor plates are provided and with at least one conductive connection to the actual digital semiconductor circuit and to the clock generator.
  • digital semiconductor circuits often require not only two operating potentials but also a further operating potential which is used to produce a substrate bias lying between the rear side of the semiconductor die and the circuit parts on the front side thereof. If a clock is then provided in the circuit, it should be in the interest of avoiding destruction the integrated semiconductor circuit of the clock generator can only be switched on after the substrate bias voltage V BB has been built up. Furthermore, many digital circuits, for example dynamic memories, are interested in an auxiliary voltage V z which exceeds the voltage difference between the two connections of the semiconductor body being available, in particular if the circuit is provided with varactor capacitors to be charged. It is an object of the invention to provide a suitable circuit option.
  • an oscillator for controlling a substrate bias generator and this for controlling the clock generator is provided in such a way that the clock generator only comes into operation after the substrate bias voltage V BB has been completed .
  • This is done in particular by means of a converter which acts as a comparator and which activates the clock generator when the final value of the substrate bias is reached.
  • said oscillator is provided for controlling a voltage multiplication circuit which supplies an additional further operating potential V Z , for example a voltage doubling circuit.
  • This further operating potential is preferably used to apply MOS capacitors, that is to say the said varactor capacitors, which are used, for example, as storage capacitors.
  • MOS capacitors that is to say the said varactor capacitors, which are used, for example, as storage capacitors.
  • it can also form the second operating potential required to operate the actual integrated digital circuit ES instead of V cc .
  • the two supply connections of the semiconductor chip receiving the circuit are supplied with the operating potentials V CC and G ND , which are then supplied to the individual circuit parts in the manner shown in the drawing.
  • the presentation of the cable routes has not been carried out.
  • the following circuit parts are also provided:
  • the voltage multiplier is SV, the substrate bias generator SE.
  • a clocked substrate bias generator SE in which an oscillator 0 is provided as a clock generator, is described in DE-OS 28 12 378 (title: “Semiconductor circuit with at least two field-effect transistors combined in a semiconductor crystal” (VPA 78 P 1043)).
  • the circuit of a substrate bias generator shown in Fig. 1 of this OS can be applied directly.
  • the clock generator TG which is responsible for the actual integrated digital semiconductor circuit ES is in turn supplied with rectangular pulses from an external pulse source via an input TE. It has the task of operating the actual Lichen digital semiconductor circuit to derive necessary clock signals from the primary pulses obtained via the input TE.
  • the supply potentials V CC and G ND are provided both for the clock generator TG and for the substrate bias generator SE, which incidentally also applies to the converter provided between the two.
  • This converter or converter U is also supplied by the two operating potentials V 00 and G ND . It has the task of emitting an activation signal to the clock generator TG as soon as the substrate bias voltage supplied by the substrate bias generator SE is fully built up. It is therefore the purpose of the voltage supplied by the converter V to only start the clock generator TG when the substrate bias voltage V BB has reached its desired value.
  • the converter U thus acts as a comparator and can be given, for example, by a differential amplifier. The presence of the converter U prevents the actual digital semiconductor circuit ES, for example a semiconductor memory, from being put into operation before the substrate bias is built up and the short-circuit current which then occurs being damaged.
  • the circuit principle described there can also be used for DC voltage multipliers with a different integer ratio between input and output voltage.
  • the oscillator provided there can easily be replaced by the clock oscillator 0 provided to supply the substrate bias generator SE.
  • the task of the voltage multiplier SV is to generate an increased operational DC voltage required for operating the actual digital semiconductor circuit ES, as is required, for example, for charging storage capacities.
  • the output of the voltage multiplier SV is connected to the ground potential G ND via a limiter circuit BS. It is also connected directly to a further supply input of the actual digital semiconductor circuit ES and leads the increased additional operating potential U z required for operating selected circuit parts, for example for charging storage capacitors.
  • the substrate bias V BB which is provided by the substrate bias generator SE, on the other hand, benefits all the circuit parts provided in the semiconductor die.
  • the actual operating potential V CC is made available to the circuit parts 0, SE, U, TG and SV. It also serves as the main operating potential for the actual integrated circuit ES. The same applies to the reference potential G ND .
  • the limiter circuit BS can consist, for example, of two or more MOS field-effect transistors t connected in series, which are connected as resistors by connecting their gates to their drains.
  • the source of the last of these transistors t is at the reference potential G ND .
  • the number of transistors t lying in series depends on the number of field effect transistors connected in series in the voltage multiplication circuit SV with respect to the two operating potentials V CC and G ND .
  • the transistors t can also be connected as diodes in the reverse direction.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
EP81101324A 1980-03-11 1981-02-24 Circuit semiconducteur intégré du type MOS Expired EP0036494B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19803009303 DE3009303A1 (de) 1980-03-11 1980-03-11 Monolithisch integrierte digitale halbleiterschaltung
DE3009303 1980-03-11

Publications (3)

Publication Number Publication Date
EP0036494A2 true EP0036494A2 (fr) 1981-09-30
EP0036494A3 EP0036494A3 (en) 1981-11-25
EP0036494B1 EP0036494B1 (fr) 1984-07-25

Family

ID=6096869

Family Applications (1)

Application Number Title Priority Date Filing Date
EP81101324A Expired EP0036494B1 (fr) 1980-03-11 1981-02-24 Circuit semiconducteur intégré du type MOS

Country Status (4)

Country Link
US (1) US4454431A (fr)
EP (1) EP0036494B1 (fr)
JP (1) JPS56142663A (fr)
DE (2) DE3009303A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175152A3 (fr) * 1984-08-21 1986-11-20 Lattice Semiconductor Corporation Méthode et appareil pour empêcher l'effet "latchup" dans un dispositif CMOS
EP0217065A1 (fr) * 1985-08-26 1987-04-08 Siemens Aktiengesellschaft Circuit intégré en technique complémentaire comportant un générateur de polarisation de substrat

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618249B2 (ja) * 1984-10-17 1994-03-09 富士通株式会社 半導体集積回路
US4794278A (en) * 1987-12-30 1988-12-27 Intel Corporation Stable substrate bias generator for MOS circuits
KR950002015B1 (ko) * 1991-12-23 1995-03-08 삼성전자주식회사 하나의 오실레이터에 의해 동작되는 정전원 발생회로
CN105024674B (zh) * 2015-03-13 2018-06-12 苏州迈瑞微电子有限公司 一种异步复位装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3794862A (en) * 1972-04-05 1974-02-26 Rockwell International Corp Substrate bias circuit
US3838357A (en) * 1973-10-25 1974-09-24 Honeywell Inf Systems Apparatus for using start-up of a crystal oscillator to synchronize power turn-on in various portions of a system
IT1073440B (it) * 1975-09-22 1985-04-17 Seiko Instr & Electronics Circuito elevatore di tensione realizzato in mos-fet
US4030084A (en) * 1975-11-28 1977-06-14 Honeywell Information Systems, Inc. Substrate bias voltage generated from refresh oscillator
US4142114A (en) * 1977-07-18 1979-02-27 Mostek Corporation Integrated circuit with threshold regulation
DE2812378C2 (de) * 1978-03-21 1982-04-29 Siemens AG, 1000 Berlin und 8000 München Substratvorspannungsgenerator für integrierte MIS-Schaltkreise
JPS5525220A (en) * 1978-08-11 1980-02-22 Oki Electric Ind Co Ltd Substrate bias generation circuit
US4229667A (en) * 1978-08-23 1980-10-21 Rockwell International Corporation Voltage boosting substrate bias generator
JPS5951750B2 (ja) * 1978-11-24 1984-12-15 富士通株式会社 基板バイアス発生回路
US4296340A (en) * 1979-08-27 1981-10-20 Intel Corporation Initializing circuit for MOS integrated circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0175152A3 (fr) * 1984-08-21 1986-11-20 Lattice Semiconductor Corporation Méthode et appareil pour empêcher l'effet "latchup" dans un dispositif CMOS
EP0217065A1 (fr) * 1985-08-26 1987-04-08 Siemens Aktiengesellschaft Circuit intégré en technique complémentaire comportant un générateur de polarisation de substrat

Also Published As

Publication number Publication date
US4454431A (en) 1984-06-12
DE3009303A1 (de) 1981-09-24
EP0036494B1 (fr) 1984-07-25
EP0036494A3 (en) 1981-11-25
DE3164950D1 (de) 1984-08-30
JPH0213821B2 (fr) 1990-04-05
JPS56142663A (en) 1981-11-07

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