EP0051531A1 - Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit - Google Patents

Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit Download PDF

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Publication number
EP0051531A1
EP0051531A1 EP81401716A EP81401716A EP0051531A1 EP 0051531 A1 EP0051531 A1 EP 0051531A1 EP 81401716 A EP81401716 A EP 81401716A EP 81401716 A EP81401716 A EP 81401716A EP 0051531 A1 EP0051531 A1 EP 0051531A1
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EP
European Patent Office
Prior art keywords
circuit
discharge
current
integration circuit
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP81401716A
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English (en)
French (fr)
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EP0051531B1 (de
Inventor
Michel Geesen
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Thales SA
Original Assignee
Dassault Electronique SA
Electronique Serge Dassault SA
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Publication date
Application filed by Dassault Electronique SA, Electronique Serge Dassault SA filed Critical Dassault Electronique SA
Priority to AT81401716T priority Critical patent/ATE13780T1/de
Publication of EP0051531A1 publication Critical patent/EP0051531A1/de
Application granted granted Critical
Publication of EP0051531B1 publication Critical patent/EP0051531B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time
    • G04F10/105—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time with conversion of the time-intervals
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an AC

Definitions

  • the subject of the invention is an apparatus for dating an event with respect to clock signals, in particular an event represented by the arrival of a pulse edge at a place provided with a clock.
  • the determination of this time interval is carried out by dating the respective arrival of each of these laser pulses on the satellite using a clock with which the satellite is provided and by measuring the difference between the two corresponding dates. This last measurement can be carried out on the ground using the information retransmitted by the satellite on the dates. respective arrival of the two pulses.
  • the present invention solves this problem and allows dating with very high precision events such as the arrival of a laser pulse on a satellite.
  • the charge signal is composed by the superposition of the first predetermined current and a discharge current, of much smaller amplitude and in the opposite direction to the current grip, which is applied to the integration circuit from the start of the charging period.
  • a discharge current of much smaller amplitude and in the opposite direction to the current grip, which is applied to the integration circuit from the start of the charging period.
  • the first predetermined current is again switched to pass through the first circuit and the discharge current remains applied at least until the end of the discharge period of the integration circuit.
  • the control of this discharge current outside the charge and discharge periods can be effected by means of a switching device which establishes a short circuit at the terminals of the integration device through which the discharge current flows outside. periods of operation of the latter.
  • provision is made to regulate the first predetermined current in order to maintain the current flowing through the first circuit at a constant level at the output of the first switching member to compensate for variations in the electrical characteristics of the latter.
  • this indirectly provides regulation of the level of current at the output of the second switching device in the integration circuit during short periods of operation under load of the latter.
  • a delay circuit is provided for delaying the instant of interruption of the charge (and therefore the start of the discharge) of the integration circuit for a time. at least equal to the time taken by the latter to reach a linear charge regime after the reception of the pulse representative of the event to be dated.
  • the discharge time of the integration circuit provides a measure of the time interval separating the arrival of the event to date from the clock pulse which immediately follows.
  • the discharge duration is preferably read by letting these counting means operate continuously and by reading the instantaneous state of the counter at the beginning and at the end of the discharge period in response to the corresponding signals.
  • the invention is advantageously used for dating laser pulses received by a satellite, in particular for the synchronization of atomic clocks located at separate sites on the ground.
  • the satellite S which can be a "spinned" satellite, that is to say stabilized by rotation, comprises an optical apparatus 21 (FIG. 2) suitable for projecting onto a photoelectric converter 22 a laser brush coming from one and / or the other from a multiplicity of stations P1 , P2, P 3, etc ... each equipped with a clock, for example an atomic clock.
  • a clock for example an atomic clock.
  • the purpose of the installation is to synchronize said clocks by determining the time interval which separates a pulse from one clock from a pulse from another clock, in order to determine the synchronism difference between the clocks.
  • the converter 22 can comprise a photodiode or other single photoelectric cell, as shown, or else a multiplicity of photodiodes, each of which is assigned to a wavelength used by one or more transmitting stations.
  • Each station P emits a laser pulse in a time slot allocated to it, and advantageously benefits from a multiplicity of slots, for example, one hundred, so that the measurement corresponds to an average of measurements.
  • the emissions of laser pulses by each of the stations are dated using their atomic clock and the installation carried by satellite S aims to date the arrival of a laser pulse emitted by a station and the arrival from that issued by another station so that it is possible to know the time interval separating these arrivals and to make on the atomic clocks of one and / or the other station the adjustments required to bring these last in exact synchronism to take account of their offset or to be informed about the value of it.
  • the information on the instant of impact of each laser pulse on the satellite S, instant determined by reference to clock signals available on the satellite is, for this purpose, sent by telemetry each of the stations or, preferably , to a central station C linked by telemetry not only to satellite S but also to the various stations.
  • the optical equipment 21 comprises a reflector for reflecting towards each station the laser brush that it receives from said station.
  • the measurement at each station, for example at said station Pl, of the time interval which separates the instant of emission from the pulse of the echo thus received by reflection provides information on the journey time of l pulse between said station and the satellite.
  • the optical apparatus 21 includes means for directing the laser energy reaching the satellite towards a photodiode 22 through an optic such as a lens not shown.
  • the electrical output 24 of the photodiode 22 is connected through an amplifier-detector 25 to an input CE27 of a flip-flop 28 of type D, the input D29 of which is fixed at a stable level equivalent to a logic level 1 permanently.
  • the flip-flop 28 has a reset input R30 and two outputs, direct and reverse, respectively Q 31 and Q 32.
  • the output Q 31 of the flip-flop 28 is connected, on the one hand, to a control input 35 of a switching circuit 36 capable, in a first condition, of short-circuiting two terminal terminals 37 and 38 and, in a second condition, of interrupting the short circuit between the terminals 37 and 38.
  • the output Q 31 is also connected to the input D40 of a flip-flop 41 of type D, by a link 33.
  • the flip-flop 41 receives on its clock input CE42 output signals from an amplifier 43, itself supplied by a clock circuit 44, operating in the example chosen at a frequency of 15 MHz.
  • the flip-flop circuit 41 includes an output Q 45 connected, through a delay circuit 46, which can be constituted by a series connection of two logic gates, to an input 47 of an OR gate 48 of which the other input 49 is connected to the output Q 32 of the flip-flop 28.
  • the output of the delay circuit 46 is also connected to an interface circuit 50 by a link 51 transmitting to this circuit information known as the start of conversion. Given the operating time of the interface 50, it is also possible to connect the line 51 upstream of the delay circuit 46. In this interface 5 0 is derived a line 53 resetting reset connected to the R input 30 of flip-flop 28.
  • the interface 50 also receives at an input 54 signals from d an inverting output 55 of the clock signal amplifier 43. This interface moreover has a certain number of outputs which will be explained below.
  • the OR gate 48 has a direct output 58 and an inverting output 60, the first output 58 being connected to the base 61 of an NPN type transistor Q71 while the inverting output 60 of the OR gate 48 is connected to the base 62 of a transistor Q72 chosen to have characteristics as close as possible to those of transistor Q71.
  • These two transistors Q71 and Q72 have their transmitters connected in common to a terminal 65 of an adjustable current generator 66 supplying a current designated hereinafter by the letter I.
  • the generator 66 is connected to a voltage source which, in the example considered, is -15 volts.
  • the nominal current of generator 66 is approximately 20 milli-amperes in this example.
  • the current generator 66 has an input 68 capable of receiving a voltage signal from a comparison circuit 70 controlling the level of current supplied by this generator for the purpose of regulation as will be explained below.
  • the comparison circuit 70 receives on its input 73 a voltage signal taken from the collector 75 of the transistor Q71 to which this input 73 is connected.
  • the comparator circuit 70 has a second input 74 capable of receiving a reference voltage stabilized by Z ener diode and providing a reference from which the level of the current of the generator 66 is regulated.
  • the collector 75 of transistor Q71 is connected to ground M via a resistor R78. An input terminal 37 of the switching circuit 36 is also grounded.
  • the collector 76 of the transistor Q72 is directly connected to the terminal 38 of the switching circuit 36, this terminal 38 being itself connected to one end of a second constant current generator 80, the other end 81 of which is connected to a source voltage, for example +12 volts.
  • This generator 80 is suitable for producing a current to which reference will be made below under the designation i, i being in the example chosen of an order of magnitude of 20 micro-amps, that is to say about a thousand times lower than current I.
  • a capacitor C 84 is also connected between terminals 37 and 38, its armature 85 being connected to terminal 37 and therefore to ground, while its armature 86 is connected to terminal 38.
  • This armature 86 is also connected to the input of a level detector 88 whose output 90 is connected, on the one hand to an i end of conversion line 92 suitable for transmitting information when the discharge of the capacitor C84 has ended, and on the other hand, via a line 94, to an input 95 of the switching circuit 36 in order to re-establish the connection between the terminals 37 and 38 as soon as a signal appears on the output 90 of the comparator or level detector 88 .
  • the input 35 of the switching circuit 36 is connected (FIG. 6) to an armature of a capacitor 103, the other armature of which is connected to the base 104 of a PNP transistor 105 and, through a resistor 107 to the input 95 of circuit 36 from output 90 of detector 88.
  • a resistor 110 connected between a source of negative potential (-v) and the base 104 forms with the resistor 1 0 7 a bias circuit of this base at a sufficiently low value, when the detector 88 is at rest, so that the transistor 105, the emitter 111 of which is connected to junction 37 and the collector 113 to junction 38 through a resistor 112, that is to say.
  • the transistor 105 short-circuits the capacitor C84 while maintaining only between the plates 85 and 86 a residual voltage equal to the potential drop of the current i in the resistor 112. This potential drop is always greater than the voltage of offset of the comparator 88 in order to allow a frank switching of the latter when a capacitor charge signal is applied to its negative input 120, the positive input 121 being connected to ground.
  • the general operating principle is as follows: As soon as a laser pulse arrives, the capacitor C84 begins to charge at a stable and relatively high rate. the charge is stopped upon reception of the first signal from the reference clock 44 carried by the satellite following reception of the laser pulse. From this moment, the capacitor C84 is discharged at a known rate, about a thousand times lower than the charge rate and the discharge time of this capacitor is measured. Clock 44 is used for this timing, as will be indicated below. The end of the discharge is detected by the detector 88 which then emits an end of conversion signal which is dated to measure the elapsed time.
  • FIG. 2 Detailed operation will be clearly understood if reference is made to FIG. 2 at the same time as to the signal diagrams represented in FIG. 5.
  • the switching circuit 36 Before receiving a laser pulse, the switching circuit 36 is in its closed position (level O in the diagram SA in FIG. 5).
  • the output Q 31 is at its level O, Q32 being at the level 1 (figure 5 C).
  • the clock 44 produces a crenellated signal H , as shown in FIG. 5 D, on the input C E42 of the flip-flop 41; the output Q45 of this rocker is on level O; the base of Q71 is supplied by the output Q32 of the flip-flop 28 through the OR gate 48, which keeps the transistor Q71 in the conducting state.
  • the base of Q 72 is not supplied and this latter transistor is blocked (FIG. 5 G).
  • the capacitor C84 is discharged, its armatures being short-circuited by the switching circuit 36 (FIG. 5H).
  • Terminal 38 is therefore now connected to current generator 66 and capacitor C 84, whose armatures are no longer short-circuited, begins to charge negatively (Figure 5H) under the effect of a current equal to ( Ii) if we ignore for the moment the base emitter current of transistor Q72.
  • the signal of the output Q31 (FIG. 6) charges the capacitor 103 at a level which causes the transistor 105 to switch off. Under the effect of the charge of the capacitor C84, the level voltage at the output of detector 88 rises and confirms by input 95 the non-conduction polarization of base 104.
  • the capacitor C84 begins to discharge under the effect of the current i, the current I being deflected by the transistor Q71.
  • This discharge is represented in FIG. 5H by the line of low positive slope which, in reality is about a thousand times less inclined than the straight line of negative slope charge preceding it.
  • the duration of this discharge is timed by means which will be ex plicites below.
  • the return of the armature 86 to a potential level close to 0, causes the output voltage 90 of the detector 88 to drop.
  • the voltage of the base 104 drops and the transistor 105 allows sufficient current to pass through to prevent capacitor C84 from charging substantially in the opposite direction under the action of current i at an undesirable level.
  • the fallout of the output voltage 90 of the detector 88 controls the transfer of the dating information in a memory described below, and at the end of this, the resetting of the flip-flop 28 whose outputs Q31 and Q32 change state and cause, on the one hand, the return to its resting voltage of the capacitor C84 and on the other hand, to the next clock signal, the delivery of the output Q45 to its initial state.
  • the capacitor C 84 is returned to its resting voltage when the output Q 31 returns to its initial state by reducing the bias voltage of the base 1 0 4 to a level which restores the full conduction of the transistor 105 (FIG. 6).
  • the frequency of the clock signal specific to the satellite originating from circuit 44 is for example, 15 MHz
  • the corresponding period between two clock fronts is very large with respect to the accuracy, by one nanosecond or less, required to date the arrival of the above-mentioned laser pulses.
  • the circuit which has just been described makes it possible to locate in time the position of the arrival of such a pulse between two successive clock fronts, such as FA in FIG. 5 D, by measuring the discharge time of the capacitor . This time is, in fact, very long and can be measured by counting a corresponding number of slots of this same clock.
  • the capacitor discharge rate is a thousand times lower than the latter's charge rate
  • the charge level corresponding to the continuous integration between two successive clock slots will be discharged over an expanded time interval corresponding to a thousand slots of this same clock. If the timed discharge time corresponds for example to 600 slots, it is deduced therefrom that the laser pulse had been received at an instant preceding the arrival of the clock signal which triggered the discharge by an interval equal to sixty percent ( 60%) of the period of this clock to within a constant depending on the delay ⁇ .
  • the curve representing the charge of the capacitor C84 is shown in FIG. 4. It has a non-linear initial part a, followed by a linear part b. Charging continues until the time H of arrival of the delayed clock signal on the input 47 of the OR gate 48. The transistor Q72 is blocked, while the transistor Q71 is turned on and the capacitor C84 is discharged linearly.
  • the dotted line is shown in FIG. 4, on the right of the theoretical charge of the capacitor C84 after the arrival of the laser pulse at time t l .
  • the theoretical and real charge and discharge curves have also been shown for a laser pulse arriving at time t 2 .
  • the end of conversion signals are provided respectively at times T 1 and T 2 for the real curves (solid line) and T ' l and T' 2 for the theoretical curves (dotted line).
  • T l -T 2 T ' 1 -T' 2 and therefore that the information of. dating corresponds to theoretical conditions as long as the clock signal passing from fast charge to slow discharge occurs on a straight part of the charge curve.
  • the delay circuit 46 shown in FIG. 2 has the function of delaying the application to the OR gate 48 of the clock signal immediately following the arrival of the laser pulse for a time at least equal to the time ⁇ necessary for the capacitor C84 to acquire a linear load regime.
  • the instant H at which the transistors Q71 and Q72 are switched to approach the discharge of C84 is therefore always separated from the arrival of the laser pulse by an interval which can be taken, for example, equal to one tenth of the period of l clock 44.
  • the discharge cannot start at a point of a por non-linear tion of the charge curve of the capacitor C 84.
  • the charge time of the capacitor may be slightly greater than one period of this clock. Under these conditions, the number of pulses counted during the discharge of the capacitor may be slightly greater than K, K being the expansion factor of the time scale used to date the reception of a laser pulse between two pulses clock.
  • the charging current of the capacitor C84 is not strictly equal to the difference (Ii) of the currents from the generators 66 and 80, but to the difference between the collector current (point 76) of the transistor Q72 and current i.
  • This collector current is itself equal to the difference of current I and base-emitter current of transistor Q72. Since the base-emitter current of this transistor can vary, the current I is regulated and, since the transistor Q72 only comes into operation for short periods, regulation of the collector current Q71 is preferably carried out.
  • the collector voltage (voltage at point 75) is taken by comparator 70 and compared to a reference voltage admitted on input 74 of this comparator.
  • the current of the generator 66 is adjusted according to the error signal appearing at the output of comparator 7 0 .
  • the collector voltage signal is representative of the collector current passing through the resistor R78. Since the transistors Q71 and Q72 are very close to each other, as regards both their environment and their characteristics, the compensation of the current I, to take account of variations in the base-emitter current of one, is suitable , except for a very small error, to take account of variations in the base-emitter current of the other. When the transistor Q72 goes into conduction, its collector current, which ensures the charge of the capacitor C84 in combination with the current i is thus well maintained at a constant value, with an accuracy depending on that of the reference voltage Zener on the entry 74.
  • the interface 50 of FIG. 2 has the role of converting or adapting the signals produced or received by the circuits shown, which are produced in ECL logic, to a TTL or C HOS logic, in which the other portions of the information processing and dating system according to the invention.
  • a reset reset signal is applied to input 205 of the interface, which causes the flip-flop 28 to be reset by line 53.
  • An output 201 of interface 50 provides the clock signals at the frequency of the signals present on line 54.
  • An output 203 transmits to the outside of the interface a conversion start signal as soon as such a signal appears on line 51.
  • line 92 connected to the output of the level detector 88 transmits an end of conversion signal as explained above.
  • the measurement circuit represented in this figure is intended for timing the discharge time of the circuit of the capacitor C84 under the action of the discharge current i.
  • a counter 221 is supplied on its input 223 by the clock pulses coming from the output 201 of the interface 50 at the frequency of these pulses at the input of the flip-flop 41.
  • This counter "rotates" freely, it is that is, it counts in per manence from its initial value to its maximum capacity, after which it resumes counting at its initial value and so on, as long as it receives clock pulses. It is connected, by a multi-bit link 219, to two registers 218 and 229.
  • the register 218 has a control input 217 connected to the output 2 0 3 of the interface 50 to read in the register 218 the content of the counter at the time where the conversion start pulse is generated at the output 203 of the interface 50.
  • the register 229 is suitable for reading the state of the least significant stages, for example twelve in number, of the counter 221 when its input 231 receives the indication of the end of conversion signal from line 92 of FIG. 2. It therefore records the instantaneous state of these low-order stages of counter 221 at the moment when the end of the discharge is detected.
  • the outputs of registers 218 and 229 are respectively connected to inputs 225 and 234 of a writing device which introduces the content of this register into a memory 237 by a line 235 connecting the output of the writing device to the input 236 of this memory.
  • the memory 237 is associated with a reading device 238 which controls the serial output of the information stored on an output 242 via a control line 240.
  • This reading circuit comprises two inputs, a timing input 241 and a transfer authorization input 239 to allow control by the read circuit of the bit-by-bit transfer out of the memory on the output 242.
  • serial output bits on line 242 are transmitted by telemetry to a ground station responsible for centralizing the information necessary for the synchronization of clocks.
  • the very high operating precision of the dating circuit which has just been described makes it possible to take advantage of very large time scale expansion ratios, greater than L 500 and possibly exceeding one thousand, for measuring the separate time. rant the arrival of the pulse from the next clock pulse.
  • Such expansion factors which result from the ratio between the charge and discharge rate of the capacitor used for expansion would be illusory in the absence of very high precision in time of the switching operations linked to the dating, precisions authorized by the various implementation characteristics which have been described.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Optical Radar Systems And Details Thereof (AREA)
  • Pulse Circuits (AREA)
  • Gyroscopes (AREA)
  • Electric Clocks (AREA)
  • Time Recorders, Dirve Recorders, Access Control (AREA)
EP81401716A 1980-10-31 1981-10-27 Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit Expired EP0051531B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT81401716T ATE13780T1 (de) 1980-10-31 1981-10-27 Einrichtung zur genauen datierung eines ereignisses bezueglich einer referenzzeit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8023404 1980-10-31
FR8023404A FR2493553A1 (fr) 1980-10-31 1980-10-31 Appareillage pour la datation precise d'un evenement par rapport a une reference de temps

Publications (2)

Publication Number Publication Date
EP0051531A1 true EP0051531A1 (de) 1982-05-12
EP0051531B1 EP0051531B1 (de) 1985-06-12

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EP81401716A Expired EP0051531B1 (de) 1980-10-31 1981-10-27 Einrichtung zur genauen Datierung eines Ereignisses bezüglich einer Referenzzeit

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US (1) US4408895A (de)
EP (1) EP0051531B1 (de)
AT (1) ATE13780T1 (de)
CA (1) CA1171290A (de)
DE (1) DE3170949D1 (de)
ES (1) ES8300207A1 (de)
FR (1) FR2493553A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141122A1 (de) * 1983-09-08 1985-05-15 Siemens Aktiengesellschaft Schaltungsanordnung zur Messung Kurzer Zeit
EP0142644A1 (de) * 1983-09-08 1985-05-29 Siemens Aktiengesellschaft Schaltungsanordnung zur Messung von Zeiten

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4516861A (en) * 1983-10-07 1985-05-14 Sperry Corporation High resolution and high accuracy time interval generator
JPH02297021A (ja) * 1989-05-12 1990-12-07 Nippon Soken Inc 物理量測定装置
FR2730830B1 (fr) * 1995-02-22 1997-06-06 Dassault Electronique Chronometrie electronique tres precise d'un evenement
DE69707851T2 (de) * 1996-04-02 2002-05-16 Lecroy Corp., Chestnut Ridge Verfahren und vorrichtung zum hochgenauen messen von zeitintervallen

Citations (2)

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Publication number Priority date Publication date Assignee Title
US3983481A (en) * 1975-08-04 1976-09-28 Ortec Incorporated Digital intervalometer
FR2468153A1 (fr) * 1979-10-25 1981-04-30 Tektronix Inc Systeme chronometrique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104590A (en) * 1976-11-30 1978-08-01 Sergei Vasilievich Zhevnerov Digital device for measuring instantaneous parameter values of slowly varying processes
US4339712A (en) * 1980-05-01 1982-07-13 The Boeing Company Method and system for measuring width and amplitude of current pulse
US4362394A (en) * 1980-09-30 1982-12-07 Marconi Instruments Limited Time interval measurement arrangement

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983481A (en) * 1975-08-04 1976-09-28 Ortec Incorporated Digital intervalometer
FR2468153A1 (fr) * 1979-10-25 1981-04-30 Tektronix Inc Systeme chronometrique

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Nuclear Instruments and Methods, Volume 109, No. 3, 15 Juin 1973, Amsterdam (NL) R.E.H. JONES et al. "The Time Stretcher", pages 461-477 * page 469, colonne de droite, lignes 21-44; page 471, colonne de droite, lignes 14-18; figures 4,7,9 * *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141122A1 (de) * 1983-09-08 1985-05-15 Siemens Aktiengesellschaft Schaltungsanordnung zur Messung Kurzer Zeit
EP0142644A1 (de) * 1983-09-08 1985-05-29 Siemens Aktiengesellschaft Schaltungsanordnung zur Messung von Zeiten

Also Published As

Publication number Publication date
ATE13780T1 (de) 1985-06-15
US4408895A (en) 1983-10-11
ES506724A0 (es) 1982-10-01
FR2493553A1 (fr) 1982-05-07
FR2493553B1 (de) 1985-05-03
DE3170949D1 (en) 1985-07-18
EP0051531B1 (de) 1985-06-12
CA1171290A (en) 1984-07-24
ES8300207A1 (es) 1982-10-01

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