EP0053487B1 - Testgerät zur Signalzeitmessung - Google Patents

Testgerät zur Signalzeitmessung Download PDF

Info

Publication number
EP0053487B1
EP0053487B1 EP19810305596 EP81305596A EP0053487B1 EP 0053487 B1 EP0053487 B1 EP 0053487B1 EP 19810305596 EP19810305596 EP 19810305596 EP 81305596 A EP81305596 A EP 81305596A EP 0053487 B1 EP0053487 B1 EP 0053487B1
Authority
EP
European Patent Office
Prior art keywords
signals
flip
flop
transistors
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP19810305596
Other languages
English (en)
French (fr)
Other versions
EP0053487A1 (de
Inventor
Bruce C. Keene
Raymond E. Nielsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Bull Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US06/211,162 external-priority patent/US4370574A/en
Priority claimed from US06/210,950 external-priority patent/US4370573A/en
Application filed by Honeywell Bull Inc filed Critical Honeywell Bull Inc
Publication of EP0053487A1 publication Critical patent/EP0053487A1/de
Application granted granted Critical
Publication of EP0053487B1 publication Critical patent/EP0053487B1/de
Expired legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Definitions

  • the present invention relates to test apparatus for measuring the time difference between two signals, particularly signals which are cycled repeatedly.
  • Such apparatus is frequently required in the development and monitoring of digital electronic circuitry.
  • the primary need is often merely to determine which of two signals is the first to undergo a transition, but it is often desirable also to be able to measure the time interval between the two signals.
  • a bi-stable trigger circuit employing a flip-flop to determine the polarity of an input signal which is applied between the two input points of the flip-flop, the flip-flop being constructed so that it is balanced and having its power supply turned on for the measurement, the flip-flop thereby taking up one or other state in dependence on the input difference as it becomes bistable as a result of the power supply rising.
  • the object of the present invention is to provide test apparatus for measuring the time difference between two signals which is both simple and fast.
  • the present invention provides test apparatus for determining the time relationship between two signals, and comprises a pair of probes for picking up the two signals, circuitry for adjusting the polarities and levels of the signals, a cross-coupled transistor pair forming a flip-flop, detection circuitry connected to said flip-flop to determine the difference between the outputs of its two transistors, and display means fed by said detection circuitry and input circuitry to the flip-flop.
  • the apparatus is characterized by said input circuitry comprising two transistors, each with its emitter-collector path connected in parallel with the emitter-collector path of a respective one of the two cross-coupled transistors of the flip-flop, to apply the signals to the cross-coupled transistor pair so as to cause the cross-coupled pair to change from an initial state with both transistors in the same, i.e. abnormal, state to a state with the two transistors in opposite, i.e. normal, state.
  • bias means for adding a variable bias to one of the signals, preferably, said bias means to generate a sinusoidal signal of a frequency much lower than the cycle frequency of the two signals.
  • a circuit is known from US patent 2,962,609 to generate a pulse train in which the repetition rate and duty cycle of the pulses can be varied infinitely and independently of each other even though the switches which generate the pulse have finite operate and release times. While this circuit may be of interest as technological background with respect to the generation of the variable bias mentioned above, it is less relevant to the main object of this invention, i.e. test apparatus for measuring time difference between signals, because it is concerned with the opposite problem to the subject apparatus, i.e. generating signals of known time spacing.
  • FIG. 1 shows the main units of the test apparatus.
  • Two probes 16 and 18 are attached to the two points at which the two signals, whose timings are to be compared, appear.
  • Two switches 20 and 21 select the probe outputs either direct or via level changing circuits 10 and 13, which are TTL to CML level shifters.
  • the switches 20 and 21 feed respective CML buffers 11 and 14, from which either the positive (direct) or negative (inverted, complemented) outputs can be selected by two more switches 22 and 23.
  • the two switches 22 and 23 feed a CML flip-flop circuit 12, which is the key to the signal comparison process.
  • This circuit 12 feeds a detection circuit 24, which in turn feeds a display unit 15 which displays an indication of the timing difference between the two signals.
  • a bias oscillator 20 which produces a sine wave output of frequency low compared to that of the signals being compared, is coupled to one input to the flip-flop 12.
  • a power supply 25 provides power for the remainder of the circuitry. In some circumstances, the circuitry can obtain its power supplies from the computer being tested instead of having its own independent power supply 25.
  • FIG. 2 shows the CML flip-flop 12 in detail. This comprises two transistors Q2 and Q3, cross-coupled and connected in series with two resistors R1 and R2 respectively as shown, to form a bistable circuit, together with two input transistors Q1 and Q2 connected across Q2 and Q3 as shown.
  • This circuit is a very simple and primitive form of flip-flop, without any of the elaboration of input circuitry and clocking which is normally included in flip-flops as understood nowadays.
  • logical 1 is high, logical 0 is low.
  • the "normal" or quiescent state of the inputs to the flip-flop is both 0 (low). This means that Q1 and Q4 are both turned off.
  • the flip-flop can be either of its two "normal” states: either Q2 on and Q3 off, or Q2 off and Q3 on.
  • a "normal” change of flip-flop state is accomplished by one or other, but not both, of the inputs going momentarily to 1. Say the input to Q1 goes briefly to 1. This turns on Q1, forcing the collector of Q1 and hence the base of Q3 low, and hence turning off Q3 and forcing the base of Q2 high, so turning on Q2. This forces the flip-flop to one of its two normal states, and it remains in that state when the input to Q1 goes back to 0.
  • signals Q1 b and Q4b are the input signals applied to the bases of Q1 and Q4, and signals Q2c and Q3c are the signals appearing at the collectors of Q2 and Q3.
  • the input signals are both initially at 1; the full line graphs show what happens when the input to Q1 is the first to fall to 0, and the broken line graphs show what happens when the input to Q4 is the first to drop to 0.
  • the two inputs to the flip-flop are the two signals picked off by the probes 16 and 18. It is assumed that these two signals are both initially at 1, and it is required to determine which is the first to drop to 0. (If either or both is changing from 0 to 1, the CML buffers 11 and 14 can be used to invert them appropriately.) At time t0, when both have dropped to 0, the state of flip-flop 12 is dependent on which of the two signals was the first to change.
  • the detection circuit 24 is fed by the collectors of both transistors Q2 and Q3 of flip-flop 12 as shown, and forms the difference between the two voltages. This difference has a polarity dependent on the state of the flip-flop when the flip-flop is in either normal state, as indicated in Figure 3. Hence a positive voltage from circuit 24 indicates that the signal on probe 16 was the first to change, a negative voltage, that the signal on probe 18 was the first to change.
  • the display device 15 indicates the sign of this voltage.
  • the system under test will be cycling, and the signals picked up by the probes will return to 1 at some time after tO, probably (but not necessarily) in the same sequence that they went to 0.
  • the flip-flop 12 will then be forced back to the abnormal state, and will return to the normal state as soon as one or other of its input signal goes back to 0.
  • the output from the detection circuit 24 will probably be a pulse signal of one or other polarity.
  • This bias oscillator 20 provides a sinusoidal bias signal whose frequency is low compared to the cycle frequency of the system under test. This bias signal enables the time interval between the changes of the two signals being picked up by probes 16 and 18 to be measured, instead of merely the sign of this time interval being determined, as has been described so far.
  • a slow sine wave bias is used, as already stated.
  • the effect of this is shown in Figure 5.
  • the two signals V1 and V2 are shown cycling repeatedly.
  • the slow sine wave Vb carries the signal V1 up and down with respect to the critical voltage, so the instant at which the voltage V1 + Vb crosses the critical voltage will move relative to the instant at which the signal V2 crosses Vc.
  • the output Q2c - Q3c of the flip-flop 12 will consist of a series of positive pulses, as the flip-flop is repeatedly set to the same state on each signal cycle.
  • the flip-flop will be set to the other state, and its outputwill therefore be a series of pulses of the opposite polarity, until the bias voltage Vb drops back to the level where the change-over occurred.
  • the detection circuit 24 will therefore be fed with a signal somewhat as shown in Figure 5. It is evident that by smoothing this signal, a steady voltage can be obtained having a magnitude and polarity which indicate the magnitude and sign of the timing difference between the two signals V1 and V2.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)

Claims (3)

1. Testapparat zur Bestimmung des Zeitverhältnisses zwischen zwei Signalen, aufweisend
ein Paar von Sonden (16,18) zur Aufnahme der beiden Signale, eine Schaltung zur Einstellung bzw. Justierung der Polaritäten und der Niveaus der Signale (10, 20, 11, 22;-13, 21, 14, 23),
ein kreuz-gekoppeltes Transistorpaar, das einen Flip-Flop (12; Q2, Q3) bildet,
eine Detektorschaltung (24), die mit dem Flip-Flop (12) verbunden ist, um die Differenz zwischen den Ausgängen ihrer zwei Transistoren zu bestimmen,
eine Anzeigeeinrichtung (15), die durch die Detektorschaltung (24) gespeist wird, und
eine Eingangsschaltung zum Flip-Flop (12), dadurch gekennzeichnet, daß die Eingangsschaltung zwei Transistoren (Q1, Q4) umfaßt, deren Emitter-Kollektor-Weg jeweils parallel mit dem Emitter-Kollektor-Weg jeweils eines entsprechenden von zwei kreuz-gekoppelten Transistoren (Q2, Q3) des Flip-Flops (12) verbunden ist, um die Signale an das kreuz-gekoppelte Transistorpaar derart anzulegen, daß das kreuz-gekoppelte Paar dazu veranlaßt wird, von einem Initialzustand, wobei beide Transistoren (Q2, Q3) im gleichen, das heißt abnormalen Zustand sind, in einen Zustand hin zu verändern, wobei die beiden Transistoren im entgegengesetzten, das heißt normalen Zustand sind.
2. Testapparat nach Anspruch 1, gekennzeichnet durch Vorspannungseinrichtungen (20), um einem der Signale eine variable Spannung hinzufügen.
3. Testapparat nach Anspruch 2, dadurch gekennzeichnet, daß die Vorspannungseinrichtungen ein Sinussignal erzeugen, dessen Frequenz viel kleiner ist, als die Zyklusfrequenz der beiden Signale.
EP19810305596 1980-11-28 1981-11-26 Testgerät zur Signalzeitmessung Expired EP0053487B1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US06/211,162 US4370574A (en) 1980-11-28 1980-11-28 Detector for time difference between transitions in two wave forms
US211162 1980-11-28
US210950 1980-11-28
US06/210,950 US4370573A (en) 1980-11-28 1980-11-28 Wave form transition sequence detector

Publications (2)

Publication Number Publication Date
EP0053487A1 EP0053487A1 (de) 1982-06-09
EP0053487B1 true EP0053487B1 (de) 1987-12-23

Family

ID=26905675

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19810305596 Expired EP0053487B1 (de) 1980-11-28 1981-11-26 Testgerät zur Signalzeitmessung

Country Status (4)

Country Link
EP (1) EP0053487B1 (de)
AU (1) AU549448B2 (de)
DE (1) DE3176582D1 (de)
YU (1) YU279681A (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006005635A1 (de) * 2006-02-08 2007-08-09 Sms Demag Ag Rollenherdofen zum Aufheizen und/oder Temperaturausgleichen von Stranggiessprodukten aus Stahl oder Stahllegierung und dessen Anordnung vor einer Warmband-Fertigwalzstrasse
EP3835886B1 (de) 2019-12-10 2022-08-10 The Swatch Group Research and Development Ltd Armbanduhr mit steuerungsorgan
CN115047743B (zh) * 2022-08-16 2022-11-01 中国船舶重工集团公司第七0七研究所 一种基于反馈的用时端高精度时延补偿方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2962609A (en) * 1954-12-27 1960-11-29 Cons Electrodynamics Corp Pulse generator
US3509381A (en) * 1967-01-11 1970-04-28 Honeywell Inc Multivibrator circuit including output buffer means and logic means
US3534271A (en) * 1967-07-25 1970-10-13 Ryan Aeronautical Co Circuit for measuring the time differential between two pulses
GB1242855A (en) * 1967-11-01 1971-08-18 Joseph Kirkley Hourie Bi-stable trigger circuit
US3641443A (en) * 1969-12-11 1972-02-08 Westinghouse Electric Corp Frequency compensated pulse time discriminator

Also Published As

Publication number Publication date
AU549448B2 (en) 1986-01-30
AU7690681A (en) 1982-06-03
DE3176582D1 (en) 1988-02-04
YU279681A (en) 1983-10-31
EP0053487A1 (de) 1982-06-09

Similar Documents

Publication Publication Date Title
US4041381A (en) Methods and equipment for testing reflection points of transmission lines
EP0054111B1 (de) Schaltung zur Messung der Anstiegs- und Abfallverzögerung eines hochintegrierten Bausteins
US4070618A (en) Digital phase and frequency meter
FR1576123A (de)
EP0053487B1 (de) Testgerät zur Signalzeitmessung
US5686846A (en) Time duration trigger
US4489272A (en) Test circuit for turn-on and turn-off delay measurements
US6441602B1 (en) Method and apparatus for determining phase locked loop jitter
US6349267B1 (en) Rise and fall time measurement circuit
JPH07280857A (ja) パルス幅測定回路
US3691473A (en) Voltage ratio apparatus with logarithmic output
EP1226447B1 (de) Hochauflösende vorrichtung und verfahren zur ermittlung von taktverschiebungen
US3602809A (en) High speed function tester for integrated circuits
JP2571082B2 (ja) 伝送線路長測定装置
US4017794A (en) Circuit for measuring time differences among events
US4092605A (en) Phase delay simulator
JPS63233382A (ja) スキュー検出装置
KR19990053199A (ko) 테스트를 위한 고속 싱크로너스 메모리 소자
US3882390A (en) Flip-flop balance testing circuit
Nizamani A novel frequency comparator: applications in frequency meters and in difference clocks for generator frequency error monitors
SU1182412A1 (ru) Мостовое измерительное устройство
US3568056A (en) Phase measurement instrument
SU1138783A1 (ru) Рубидиевый стандарт частоты и времени
SU1302214A1 (ru) Измеритель динамических погрешностей аналоговых электронных устройств
SU1350642A1 (ru) Устройство дл электроразведки

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Designated state(s): BE DE FR GB IT NL

17P Request for examination filed

Effective date: 19830114

ITF It: translation for a ep patent filed
RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: HONEYWELL BULL INC.

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): BE DE FR GB IT NL

REF Corresponds to:

Ref document number: 3176582

Country of ref document: DE

Date of ref document: 19880204

ET Fr: translation filed
PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

ITTA It: last paid annual fee
26N No opposition filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19891126

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Effective date: 19891130

BERE Be: lapsed

Owner name: HONEYWELL BULL INC.

Effective date: 19891130

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Effective date: 19900601

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee
GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19900731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19900801

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST