Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
  • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
  • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
  • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Definitions

• the present invention pertains to integrated, semiconductor memories and in particular to such a memory adapted for use in conjunction with an error detecting and correcting circuit.
• the alpha particles are primarily derived from radioactiv impurities used in the packaging of the semiconductor chip.
• Single bit errors such as caused by alpha particle are referred to soft errors and occur rather infrequently.
• the semiconductor memories in computer systems are becoming quite large and in many cases data must be store in the memories for an appreciable period of time, days, weeks and even longer. As the memories become larger and the storage time becomes longer, the probability of incurring soft errors due to alpha particle radiation increases. In many applications the accuracy of the data stored in the semiconductor memory is critical and the loss of a single bit within a field of data can produce a serious problem in the application being conducted by the computer.
• the present invention is a dynamic, integrated, semiconductor memory circuit wherein a memory cell is accessed through row and column lines at a given memory address.
• the memory address is stored in an address buffer.
• the memory cell is accessed in response to the memory address and in response to a row address strobe (RAS) signal and a column address strobe (CAS) signal.
• RAS row address strobe
• CAS column address strobe
• the RAS signal generates row clock signals which access and refresh the memory cells on the row corresponding to the memory address in the address buffer.
• the CAS signal generates column clock signals for connecting the addressed memory cell to a data bus.
• the circuit of the present invention includes a terminal for receiving a refresh signal. Within the memory circuit row clock signals are generated upon receipt of the refresh signal as with receipt of the RAS signal.
• Logic circuitry is provided for inhibiting the generation of the column clock signals and/or the input/output circuitry in the absence of the. RAS signal.
• the circuit further " provides for transferring an externally supplied memory address to an address buffer when either the RAS signal or the refresh signal has been received at the circuit.
• FIGURE 1 is a schematic illustration of a dynamic semiconductor memory circuit in accordance with the present invention.
• FIGURE 2 is an illustration of various signal waveforms which are used in the circuits shown in FIGURE 1;
• FIGURE 3 is a semiconductor memory system which utilizes the memory circuit illustrated in FIGURE 1 and operates in conjunction with an error detecting and correcting circuit to correct single bit errors while refreshing the dynamic memory cells.
• Semiconductor memories can be particularly susceptible to alpha particle radiation which is generated by radioactive elements that are present as trace materials in connectors and packages for integrated circuits. This problem is discussed in "Hardening RAMS against Soft Errors” by Bradsky, Mark published in Electronics, Vol. 53, No. 10, April 1980, pp. 117-122.
• a memory circuit 10 comprises an integrated semiconductor memory chip. Circuit 10 receives a number of control signals which are illustrated in FIGURE 2.
• a RAS (Row Address Strobe) signal 12 is transmitted to circuit 10 through a terminal 14.
• a CAS (Column Address Strobe) signal 16 is transmitted through a terminal 18 to circuit 10.
• a refresh signal 20 is provided to circuit 10 through a terminal 22.
• An external address counter 24 generates sequential memory addresses and transmits these addresses through a path 26 to a -pin 23 of circuit 10. There is included a pin 23 for each of the bits of the address. Path 26 typically comprises multiple conductors which transfer addresses in parallel.
• the RAS signal 12 is transmitted through line 14 to the input of an inverter 28.
• the output of inverter 28 is connected to the first input of a NOR gate 30 and to the input of an inverter 32.
• the CAS signal 16 is transmitted through line 18 to the first input of a NOR gate 34 while the output of inverter 32 is connected to the second input of NOR gate 34.
• the output of gate 34 is connected to drive a column clock chain generator circuit 36 which generates a group of column clock signal for operating the column access circuits, including input/output circuits, within a memory cell array 38.
• U.S. Patent Nos. 3,902,082 and 3,969,706 illustrate the preferred circuitry for array 38.
• the refresh signal 20 is transmitted through line 22 to the input of an inverter 40 which has the output thereof connected to the second input of the NOR gate 30.
• the output of gate 30 is connected to an inverter 42 which is in turn connected to drive a row clock chain generator circuit 44.
• the row clock chain generator 44 produces a group of row clock signals which control the operation and timing of the access transistors for the row lines within the memory cell " array 38.
• the RAS signal 12 is further transmitted to the gate terminal of a transistor 46.
• the refresh signal 20 is also transmitted to the gate terminal of a transistor 48.
• the source terminals of transistors 46 and 48 are connected to the drain terminal of a transistor 50 which has a source terminal thereof grounded.
• the gate terminal of transistor 50 is connected to the output of inverter 42.
• the drain terminal of transistor 46 is connected to the source terminal of a transistor 52 and the drain terminal of transistor 48 is connected to the source terminal of a transistor 54.
• the drain terminal of transistor 52 is connected to a node 56 while the drain terminal of transistor 54 is connected to a node 58.
• the gate terminal of transistor 52 is connected to node 58 and the gate terminal of transistor 54 is connected to node 56.
• a precharge transistor 53 has the source terminal thereof connected to node 56, the drain thereof connected to V and the gate terminal thereof connected to the output terminal of gate 30.
• a precharge transistor 57 has the source terminal thereof connected to node 58, the drain terminal thereof connected to V critiquec outreachc and the g -ate terminal connected to the output terminal of gate 30.
• a CPU 89 is connected through line 26 to provide addresses for routine read or write operations. _
• the combination of transistors 46, 48, 52, 53, 54 and 57 functions as a differential amplifier 55 in which the inputs are the RAS signal 12 and the refresh signal 20 and the differential outputs are at nodes 56 and 58.
• the node 58 is connected to the drain terminal of a transistor 60 which has a source terminal thereof connected to the drain terminal of transistor 50.
• the gate terminal of transistor 60 is connected to the first terminal of a resistor 62 which has a second terminal thereof connected to ground.
• the gate terminal of transistor 60 is further connected to a first terminal 64.
• a second terminal 66 is connected to the voltage source V •
• a strap 68 is optionally installed to connect terminals 64 and 66. The optional functions related to strap 68 are described below.
• Node 56 is connected to the gate terminal of a transistor 70 which has the source terminal thereof connected to the drain terminal of a transistor 72.
• the source terminal of transistor 72 is grounded.
• the gate terminal of transistor 72 is connected to line 23 for receiving an externally supplied address generated by the address counter 24 or CPU 89.
• the drain terminal of transistor 70 is connected to a node 74 which is in turn connected to the drain terminal of a transistor 76 and an address input buffer 78.
• the gate terminal of transistor 76 is connected to node 58.
• the source terminal of transistor 76 is connected to the drain terminal of a transistor 80 which has the source terminal thereof grounded.
• the gate terminal of transistor 80 is connecte to an internal address counter 82, which generates sequential memory addresses for the memory locations in array 38.
• the address input buffer 78 transfers the memory addresses stored therein to the memory cell array 38 which includes decoders that receive the row and column portions of the memory address and utilize this address information to activate the appropriate rows and columns within the memory cell array.
• a data bus line 88 is connected to the memory cell array 38 for transferring data into and out of the memory cells. Referring now to FIGURE 2, the row address information is strobed into the memory cell array 38 when the RAS signal 12 transitions from the inactive to the active state (high level to low level) .
• the column address information is strobed into the memory cell array when the CAS signal 16 transitions from the inactive to the active state (high level to low level) .
• a write enable signal 88 is activated to write into the selected memory cell.
• the data is read out of the memory at the time sequence indicated by data signal 90.
• the "one" and “zero" data states are defined arbitrarily for the particular system.
• the memory circuit 10 is designed to function in either of two modes.
• the circuit 10 is designed to operate as a dynamic memory which has an internal address counter for providing the address sequence for refresh operation.
• the circuit 10 functions in conjunction with external circuitry to provide an error detection and correction capability.
• ci cuit In the nonerror correcting embodiment of ci cuit
• the refresh command operates in conjunction with the internally generated address to cause sequential rows of memory cells to be refreshed.
• the refresh operation for the dynamic memory cells included within circuit 10 is thus carried out by periodically driving to the active state the refresh signal 20.
• the RAS signal 12 is driven to the active state in which a low level is applied to the input of inverter 28 which produces a high level at the output thereof.
• a high level applied- to one input of the NOR gate 30 causes the output to be driven to a low level.
• the low level input to inverter 42 produces a high level output that activates the row clock chain generator 44 to produce the row clock signals which are applied to the memory cell array 38.
• the low level signal on the RAS input produces a high level at the input of inverter 32 driving the output of the inverter to a low level. If and when the CAS input 16 goes low, a high level is generated at the output of NOR gate 34 to initiate the sequence of column clocks.
• the row address is transmitted through the external address, input 23 and supplied to the address input buffers 78 and from the buffer to the memory cell array 38. This activates all of the memory cells along the row defined by the row address.
• the CAS signal 16 transitions to the active state thus applying a low signal level to the first input of NOR gate 34.
• the RAS signal 12 has driven the output of inverter 28 to a high level which is converted to a low level at the output of inverter 32.
• the low level signal applied from inverter 32 to the input of NOR gate 34 enables the CAS signal 16 to be transmitted to the output of NOR gate 34 as a high level signal to activate the column clock chain generator 36.
• the generator 36 produces the column clock signals for activating the column circuitry.within the memory cell array 38.
• the column portion of the memory address is entered into the memory cell array 38 as indicated by the strobe in signal 16. After both the row and column address information has been supplied to the memory cell array 38 the appropriate memory location is accessed for data transfer through data bus 88.
• transistor 50 brings the common source terminal of transistors 46 and 48 to ground, node 58 is discharged faster than node 56, turning off transistor 52. Node 58 is discharged to ground leaving node 56 at a high level. This leaves transistor 70 on and turns transistor 76 off.
• node 74 The discharge of node 74 is independent of the internal address counter state since transistor 76 is turned off. If the input address at pin 23 is high, transistor 72 discharges node 74 through conductive transistor 70. If the input at node 23 is low, transisto 72 is off, so node 74 is not discharged. The data on node 74 is thus the complement of the address received at pin 23.
• the differential amplifier 55 would have performed as described above except that node 56 is discharged to ground while node 58 remains high. In this case, transistor 70 would be turned off so that the externally supplied address has no effect on node 74 while transistor 76 remains on so that node 74 is discharged if the internal address counter has a high output at the gate of transistor 80.
• the memory cells in the row selected by the internal address counter 82 within the memory cell array 38 are refreshed when the refresh signal 20 is applied to circuit 10.
• the memory cells in the row selected by the externally supplied address are refreshed when the RAS signal 12 is applied to circuit 10.
• the row clock chain generator 44 produces the row clock signals which activate the rows in array 38 addressed by the address in buffer 78. But whenever the RAS signal 12 is in the inactive state the CAS signal 18 cannot be transmitted to the column clock chain generator by operation of the inverters 28 and 32 and the NOR gate 34.
• the refresh signal 20 is in the low state and the RAS signal 14 is in the high state the differential amplifier 55 drives node 56 to a low state and leaves node 58 in a high state. This causes transistor 70 to be turned off and transistor 76 to be turned on.
• transistor 70 is turned off the external address pin 23 is isolated from the address input buffer 78. But when transistor 76 is turned on the internal address counter 82 is connected to the address input buffer 78.
• the address generated by the address counter 82 is supplied to the memory cell array 38.
• Counter 82 sequentially produces a new address following each time that it is used to supply an address to the memory cell array 38.
• the periodic application of the refresh signal 20 to the refresh terminal causes all of the rows within the memory cell array 38 to be sequentially activated thereby restoring the data in the memory cells in the arra .
• the strap 68 is provided to interconnect terminals 64 and 68.
• This connection applies a high level to the_gate terminal of transistor 60 to provide a low impedance path between node 58 and the drain terminal of transistor 50.
• the output of inverter 42 is driven to a high level.
• the high level from inverter 42 turns on transistor 50 which pulls the source terminals of transistors 46 and 48 to ground.
• transistor 60 is conductive and is designed to have a very low impedance. This causes node 58 to be discharged through transistor 60 to the
• the RAS command is used for normal memory access cycles for writing or reading the memory in which the external address is supplied to the memory.
• the refresh command is used to activate the memory with the internally generated address being selected.
• each of the circuits 10 process the same address so that the data word read out as bits from individual memory circuits represent parts of the same data word.
• an external address is supplied to cause the refreshing.
• the strap from terminal 64 to terminal 68 is included in the circuit 10. With the strap the functionality of the differential amplifier 55 is modified so that independent of whether refresh or RAS is activated, in either case the internal address counter is disabled and the external address, supplied through pins 23, is transfered to the address input buffer 78.
• the RAS signal 12 and the CAS signal 16 are applied together with an externally supplied address to access a given memory location and transfer data through the data bus 88.
• the external address counter 24 With the strap 68 connecting terminals 64 and 66 the circuit 10 is configured to permit simultaneous refreshing of the memory cells in array 38 and reading out of data for error detection and correction operations
• the external address counter 24 generates sequential addresses for each of the memory locations within array 38. The least significant or fastest toggling addresses are used to select the row address to be refreshed.
• the combined refresh and readout occurs upon the application of the RAS signal 14, the CAS signal 18, the refresh signal 20 and an address supplied from the counter 24 through line 26 to pins 23.
• the row clock signals are produced by generator 44 and the column clock signals are produced by generator 36 for the memory circuits whic receive a RAS signal.
• the address from counter 24 is transmitted to the input address buffer 78 and a location specified by the address is read from the array 38.
• all of the memory cells along the addressed row are refreshed.
• a complete memory system for a compute system a plurality of the circuits 10 will be utilized but only a small number of the circuits can be read out during each refresh cycle. The remainder of the memory cell locations must however be sequenced through the refresh operation in order to maintain the data within the cells.
• the remaining circuits 10 receive the refresh signal 20 and the CAS signal 16 but do not receive the RAS signal 12 which is supplied through a decoder to only a selected group of circuits 10.
• the row clock signals are produced by the generator 44 and the externally supplied address from the counter 24 is transmitted to the address input buffer 78.
• the row clock signals cause the memory locations defined by the row portion of the address to be refreshed.
• the inverter 32 and NOR gate 34 are disabled and the CAS signal 16 cannot initiate the column clock chain generator 36.
• the memory cell array is activated to refresh a given row of memory cells but no data is read from the memory cell array 38 because no column clock signals are provided to the array.
• FIGURE 3 there is shown a computer system 100 which incorporates a plurality of the circuits 10 to make up a computer memory array 102 which is a part of a complete memory system.
• the computer memory array 102 is made up of a four by twelve matrix of circuits 10.
• the memory array 102 is divided into a data portion 102a and an error control portion 102b.
• the memory array 102 is designed to have an eight bit data word and four error control bits as defined by the Hamming code referenced above.
• the computer system 100 has a central processing unit 104 which is connected to a memory control circuit 106.
• a RAS signal is generated by memory control 106 and transmitted through a line 133 to an external RAS decoder 110.
• the RAS signal transmitted through line 133 is used to generate the
• the memory control circuit 106 also transmits the most significant bits of the memory address through a line 112 through the RAS decoder 110.
• the most significant bits of the address are logically de ' coded by the RAS decoder 110 to produce a RAS signal on any one of the lines 114, 116, 118 and 120.
• the lines 114-120 are connected respectively to banks 122, 124, 126 and 128 of memory array 102. All of the RAS inputs for the circuits 10 within a given bank are connected in common to one of the output lines of RAS decoder 110.
• the least significant bits of the memory addresses are transmitted from the memory control circuit 106 through a group of lines 130 to the input terminals of all of the circuits 10 within the memory array 102.
• the memory control circuit 106 produces the CAS signal 16 and transmits it through line 132 to each of the memory circuits 10 within the memory array 102.
• the memory control circuit 106 also produces the refresh signal 20 which is transmitted through line 134 to each of the circuits 10 within the memory array 102.
• the data outputs from the vertically stacked columns of circuits 10 are transmitted respectively through lines 136-158 to an error detecting and correcting circui 160.
• the data from the memory array 102 is corrected as necessary by the circuit 160 and is transmitted to the CP 104 through lines 162-176.
• the circuit 160 commands the memory control 106 through a line 178 to write a corrected data entry in the memory array 102.
• error detecting and correcting circuit 160 A functional embodiment of the error detecting and correcting circuit 160 is described in the article by Wall, Ernest L. "Applying the Hamming Code to Microprocessor-Based Systems", Electronics, Vol. 52, No. 24, November 22, 1979, pages 103-110.
• Each of the memory circuits 10 is configured to have the strap 68 connecting terminal 64 and 66 as shown in FIGURE 1. This strapping establishes the circuits 10 for operation in conjunction with the error detecting and correcting circuit 160.
• the circuits 10 make it possible to have a very simple connecting arrangement for operation within the memory array 102. All of the CAS signal terminals 18 of the memory circuits 10 are connected in common to line 132. All of the refresh signal terminals 22 are connected in common to the line 134.
• the RAS terminals for the circuits 10 within each of the banks 122-128 are-connecte in common to the respective lines 114-120.
• the address ports for the least significant bits of the address are connected in common for all of the circuits 10 through the group of lines 130.
• Each of the columns of memory circuits 10 are connected to a common data path. It can be seen that the layout of memory array 102 is mad very simple and straightforward by the design of the circuits 10.
• the memory control circuit 106 periodically reads the address produced by counter 24 and generates the appropriate signals to refresh the memory cells within the memory array 102 and to read out a given word of memory for error detection and correction.
• the error detection and correction is thus carried out in conjunction with the refresh operation so that no additional overhead time is required to accommodate the error detection and correction.
• the most significant bits of the address are transmitted from the control circuit 106 to the external RAS decoder 110 which decodes these bits and selects one of the memory banks 122-128.
• the selected bank will have the addressed row refreshed and the addressed word read out for error detection and correction.
• the remaining banks of memory cells will only have the addressed rows refreshed .
• a data word is read out together with the four bits of error detection code. These twelve bits are received by the error detecting and correcting circuit 160 which processes the twelve bits to determine if one of the bits is erroneous. The erroneous bit is then corrected and the correct data word is transmitted from the circuit 160 back to the corresponding address in memory array 102.
• the memory control circuit 106 controls the memory array 102 to rewrite the corrected data word at the address which was accessed during the refresh cycle.
• the corrected data word including corrected error control bits is transferred from the circuit 160 through the data lines 136-158 back to the appropriate location in the memory array 102.
• a normal read or write cycle accomplishes the refresh operation but is normally too specific in nature to guarantee to refresh every row of each circuit 10 at least every two milliseconds.
• special refresh cycles are generated. Each refresh cycle goes to all circuits 10 in the memory array 102 and one cycle is required for each row during each refresh
• the row addresses during refresh would be 0, 1, 2, ... 126, 127, 0, 1, 2, ... etc.
• the error correction during the very first cycle would be on the memory word located at row 0, column 0 and bank 122, followed by the word located at row 1, column 0, bank 122, followed in sequence by the rest of the rows through row 127, column 0, bank 122. These are followed similarly by rows 0-127 for column 1, bank 122. After all rows and columns of bank 122 have beer error corrected banks 124, 126 and 128 are similarly error corrected.
• a purpose of the present invention is to facilitate activting a given row of all circuits for a refresh cycle while enabling only one of the banks 122-128 for reading data for error correction purposes during this refresh cycle. This is accomplished in the present invention by providing the row and error correction address to the entire memory array 102 and applying the refresh command 20 to all circuits 10 within array 102.
• the external RAS decoder 110 applies a RAS signal to one of the four banks 122-128 and only that bank can output data or accept new error corrected data since the CAS command is inhibited in each of the banks not receiving the RAS command. Therefore the RAS decoder selects the bank for error correction so that it is not necessary 'to perform additional logic operations on the RAS, CAS or refresh commands to accomplish either refresh, error correction or both.
• the present invention applies equally well to a memory circuit which does not have separate row and column strobe signals.
• Such circuits can have a single dedicated signal for strobing the entire address into the memory and a separate dedicated signal for strobing data out of the memory where the data strobe signal, by itself, does not enable data input or data output.
• the circuit 160 would normally perform error detection and correction for each read cycle in the memory array 102 as well as during the refresh cycles.
• the advantage of error correcting during the refresh cycle is to guarantee that every word in the memory, whether being processed or not, is error corrected periodically to decrease the likelihood of multiple errors in the same word between error correction cycles.

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• 1980
  • 1980-06-02 EP EP19800901909 patent/EP0054023A1/de not_active Withdrawn
  • 1980-06-02 WO PCT/US1980/000672 patent/WO1981003567A1/en not_active Ceased
• 1981
  • 1981-06-02 CA CA000378893A patent/CA1170766A/en not_active Expired

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