EP0066461A2 - Disque semiconducteur et procédé pour sa fabrication - Google Patents
Disque semiconducteur et procédé pour sa fabrication Download PDFInfo
- Publication number
- EP0066461A2 EP0066461A2 EP82302746A EP82302746A EP0066461A2 EP 0066461 A2 EP0066461 A2 EP 0066461A2 EP 82302746 A EP82302746 A EP 82302746A EP 82302746 A EP82302746 A EP 82302746A EP 0066461 A2 EP0066461 A2 EP 0066461A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor wafer
- heat treatment
- wafer
- manufacturing
- silicon wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P36/00—Gettering within semiconductor bodies
- H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
Definitions
- the present invention relates to a semiconductor wafer and a method of manufacturing the same. More particularly, it relates to a semiconductor wafer which has a high gettering effect and is very useful for forming various semiconductor devices, and a method of manufacturing the same.
- various semiconductor devices including integrated circuits, solid-state imaging devices, etc. are formed in surface regions of single-crystal silicon wafers.
- the silicon wafer is formed from a single-crystal silicon rod grown by the Czochralski method or the like, which is sliced into thin discs (having a thickness of approximately 0.2 - 0.8 mm). A damaged layer is induced by the slicing and is removed by lapping and etching.
- a most useful process is called “gettering”, in which the crystal defects or impurities within the front surface region are transferred to the inner part or rear surface region of the silicon wafer so they have no influence on the characteristics of the semiconductor device, thereby to eliminate the defects or impurities from the front surface region.
- One gettering process which has heretofore been practised, for example, is a method in which a high concentration of phosphorus is diffused or a high concentration of argon is implanted into the rear surface region of the silicon wafer, whereupon the wafer is heated.
- the mechanism of gettering based on the implantation of argon ions is essentially the same as that of the gettering based on the diffusion of phosphorus.
- the argon ions When the argon ions are implanted into the rear surface of the silicon wafer, a crystal deformation appears in the implanted region. As explained above, therefore, the atoms of the harmful impurities within the front surface region can be gathered into the area of deformation in the rear surface region by the heat treatment so as to render the front surface region nondefective.
- the present invention forms substantially only stacking faults in a silicon wafer by heat-treating the silicon wafer at a predetermined temperature and performs intrinsic gettering by utilising the stacking faults.
- one aspect of the present invention provides a semiconductor wafer having a denuded zone which is formed within a front surface region in which a device is to be formed, and a defect beneath the denuded zone; characterised in that said denuded zone is approximately 5 - 100 ⁇ m thick and that the defect consists substantially of stacking faults.
- Another aspect of the present invention provides a method of manufacturing a semiconductor wafer comprising:
- a silicon wafer for use in the formation of various semiconductor devices including large-scale integrated circuits etc. is formed by slicing into a thin disc a silicon rod produced by the Czochralski method.
- the Czochralski method is well known, and is a method wherein silicon is molten in a quartz crucible and a seed crystal is slowly pulled up in contact with the silicon melt, thereby to grow single-crystal silicon.
- the quartz (Si0 2 ) of which the crucible is made cannot be prevented from entering the silicon melt in the course of growing the single crystal.
- the single-crystal silicon produced contains supersaturated interstitial oxygen.
- the prior-art intrinsic gettering method makes precipitates of the interstitial oxygen as Si0 2 within the silicon wafer by a heat treatment, and carries out another heat treatment so as to effect gettering by the dislocations generated from the precipitate.
- the present invention has been made on the basis of the discovery that the insufficiency of the gettering effect is due to the performance of gettering utilising dislocations generated by the precipitate.
- heat-treatment conditions are set into predetermined ranges, thereby to form a denuded zone having no crystal defects of a predetermined thickness and to perform gettering with only stacking faults, not with dislocations generated from precipitates.
- the preferred method comprises three steps to be described hereunder.
- the first step is that oxygen contained in the front surface region of a silicon wafer in which a device is to be formed is volatilised out by a heat treatment in an inert gas, to form an oxygen reduced region approximately 5- 100 ⁇ m thick within the front surface region.
- a single-crystal silicon rod formed by the Czochralski method or the like is sliced into a disc having a thickness of approximately 0.2 - 0.8 mm, whereupon a damaged layer in the front surface of the disc which appears in the slicing is removed by a well known expedient such as mechanical-chemical etching.
- the heat treatment is carried out at a temperature of about 1000 - 1200°C in an inert gas such as nitrogen, argon and helium.
- an inert gas such as nitrogen, argon and helium.
- the thickness of the oxygen reduced region is smaller than approximately 5 um, some stacking faults existing in the inner part of the wafer can appear in the front surface region.
- the thickness is greater than 100 um, it is feared that the gettering effect utilising the stacking faults will become insufficient, resulting in inferior characteristics of the front surface region.
- the thickness of the oxygen reduced region to to formed in this step should preferably be approximately 5 - 100 pm.
- the thickness of the oxygen reduced region formed in this step is determined by the conditions of the heat treatment.
- a heat treatment at 1200°C for 16 hours is conducted, an oxygen reduced region 50 pm thick is formed, and when a heat treatment at 1000°C for 30 minutes is conducted, an oxygen reduced region 5 ⁇ m thick is formed.
- the thickness of the oxygen reduced region formed is substantially proportional to the square root of the heat treatment time. It is therefore easy to control the thickness of the oxygen reduced region to a desired value.
- the heat treatment temperature in this step should preferably be set at about 1000 - 1200°C.
- the second step is the step of forming the nuclei of defects from the interstitial oxygen within the silicon wafer.
- the first step is followed by a heat treatment at a temperature of about 600 - 1000°C, the migration of the interstitial oxygen begins, and the defect nuclei are formed.
- the heat treatment temperature is below about 600°C, little migration of the interstitial oxygen takes place, so that it is difficult to form defect nuclei.
- the degree of supersaturation of the interstitial oxygen lowers, so that the formation of defect nuclei becomes difficult.
- the temperature of the heat treatment in this step should preferably be set at about 600 - 1000°C.
- the heat treatment time is set at about one hour or more, and a heat treatment for a long period of time does not form any hindrance.
- the third step is the step of forming stacking faults within the silicon wafer by a heat treatment.
- heat treatment at a temperature of about 1050 - 1150°C is carried out after the silicon wafer has been treated by the first and second steps. Then, beneath the oxygen-reduced region in the silicon wafer which has been formed by the first step, stacking faults are formed in contact with this oxygen-reduced region so as to perform gettering.
- the stacking fault signifies a "new lattice plane having a limited area formed by the heat treatment in lattice planes existent originally". It has been discovered that when gettering is performed with such stacking fault, the removal of defects and impurities from the front surface region proceeds very favorably.
- the gettering effect based on the stacking fault is conspicuously reduced. It is therefore necessary that the heat treatment in the third step is conducted at about 1050 - 1150°C so as to prevent the occurrence of the other defects, whereupon gettering is performed.
- Table 1 compares the characteristics of three kinds of silicon wafers subjected to gettering operations by methods different from one another.
- the silicon wafer A is a wafer which was formed by only the foregoing steps 2 and 3 without performing the step 1.
- the second step was carried out by a heat treatment at 1000°C for 8 hours in an oxygen atmosphere, and the third step by a heat treatment at 1200°C for 3 hours in the oxygen atmosphere.
- the silicon wafer B was formed by adding the step 1 for forming a denuded zone, to the aforementioned method for forming the silicon wafer A.
- a heat treatment at 1200°C for 16 hours was performed in a nitrogen atmosphere, to form a denuded zone approximately 50 ⁇ m thick.
- the second and third steps were carried out under the same conditions as those for preparing the silicon wafer A.
- the silicon wafer C was formed according to the present invention.
- the same method as in the case of the wafer B was employed except that the heat treatment temperature in the step 3 was 1100°C.
- solid-state imaging devices were formed by the well known MOS process (refer to, for example, "IEEE Transactions on Electron Devices", August 1980, pp. 1676-1681, or “IEEE Transactions on Electron Devices", Vol. ED-27, No.8, August 1980, pp. 1682-1687). Comparisons were made on the densities of defects appearing in the substrates of these devices and on the numbers of white blemishes (image defects) on the screen of a monitor television.
- the silicon wafer A for which the step 1 was not performed and which was not formed with the oxygen reduced region has a very large number of both surface defects and white blemishes. Of course, it is quite unusable.
- the silicon wafer B has the denuded zone, it includes precipitates and dislocations ascribable thereto besides stacking faults, and hence, its surface defect density is considerably high. Four white blemishes were also noted.
- the silicon wafer C formed by the present invention contains only stacking faults though the bulk defect density is somewhat lower than in the silicon wafer B. Therefore, it exhibited a very excellent gettering effect, and both the surface defect density and the number of white blemishes thereof were zero.
- the effect of the present method has been described in connection with a solid-state imaging device. Needless to say, however, the present invention is also very useful for the formation of other large-scale integrated circuits of extremely high packaging density.
- the step 1 is to volatilise out oxygen contained in the front surface region. It is therefore favourable to denude the front surface region of the wafer and to heat the wafer in a non-oxidising atmosphere in order to prevent oxidation of the front surface.
- the steps 2 and 3 need not volatilise oxygen. Therefore, the front surface may be covered or be left uncovered. Either an oxidising or non-oxidising gas may be used as the heating atmosphere.
- the steps 1, 2 and 3 may be performed as steps which are respectively independent. Needless to say, however, they may well be performed jointly with various steps for forming a semiconductor device, for example, the steps of oxidation and diffusion.
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56081047A JPS57197827A (en) | 1981-05-29 | 1981-05-29 | Semiconductor substrate |
| JP81047/81 | 1981-05-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0066461A2 true EP0066461A2 (fr) | 1982-12-08 |
Family
ID=13735503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP82302746A Withdrawn EP0066461A2 (fr) | 1981-05-29 | 1982-05-27 | Disque semiconducteur et procédé pour sa fabrication |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0066461A2 (fr) |
| JP (1) | JPS57197827A (fr) |
| KR (1) | KR860000228B1 (fr) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| US4622082A (en) * | 1984-06-25 | 1986-11-11 | Monsanto Company | Conditioned semiconductor substrates |
| US4645546A (en) * | 1984-07-13 | 1987-02-24 | Kabushiki Kaisha Toshiba | Semiconductor substrate |
| US4666532A (en) * | 1984-05-04 | 1987-05-19 | Monsanto Company | Denuding silicon substrates with oxygen and halogen |
| US4681983A (en) * | 1984-09-18 | 1987-07-21 | The Secretary Of State For Defence In Her Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Semiconductor solar cells |
| WO1992009101A1 (fr) * | 1990-11-15 | 1992-05-29 | Memc Electronic Materials S.P.A. | Procede d'obtention de profils de precipitation regules dans les tranches de silicium |
| WO1993020582A1 (fr) * | 1992-03-31 | 1993-10-14 | Mitel Corporation | Methode de preparation de semi-conducteurs avec une bonne aptitude inherente au piegeage de contaminants |
| US5506154A (en) * | 1990-09-14 | 1996-04-09 | Komatsu Electronic Metals Co., Ltd. | Process for preheat treatment of semiconductor wafers |
| KR960035771A (ko) * | 1995-03-14 | 1996-10-28 | 엔렌 에프 헨넬리 | 단결정 실리콘내의 산소 침착 생성핵 중심 농도 제어 방법 및 그 방법에 의해 제조된 단결정 실리콘 웨이퍼들로 이루어진 웨이퍼 세트 |
| US8733351B2 (en) | 1996-09-23 | 2014-05-27 | Resmed Limited | Method and apparatus for providing ventilatory assistance |
| GB2574879B (en) * | 2018-06-22 | 2022-12-28 | X Fab Semiconductor Foundries Gmbh | Substrates for III-nitride epitaxy |
-
1981
- 1981-05-29 JP JP56081047A patent/JPS57197827A/ja active Pending
-
1982
- 1982-05-27 EP EP82302746A patent/EP0066461A2/fr not_active Withdrawn
- 1982-05-28 KR KR8202363A patent/KR860000228B1/ko not_active Expired
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
| EP0131717A3 (fr) * | 1983-06-03 | 1986-07-23 | Motorola, Inc. | Procédé pour dénuder la surface d'un corps en silicium |
| US4666532A (en) * | 1984-05-04 | 1987-05-19 | Monsanto Company | Denuding silicon substrates with oxygen and halogen |
| US4622082A (en) * | 1984-06-25 | 1986-11-11 | Monsanto Company | Conditioned semiconductor substrates |
| US4645546A (en) * | 1984-07-13 | 1987-02-24 | Kabushiki Kaisha Toshiba | Semiconductor substrate |
| US4681983A (en) * | 1984-09-18 | 1987-07-21 | The Secretary Of State For Defence In Her Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Semiconductor solar cells |
| US5506154A (en) * | 1990-09-14 | 1996-04-09 | Komatsu Electronic Metals Co., Ltd. | Process for preheat treatment of semiconductor wafers |
| WO1992009101A1 (fr) * | 1990-11-15 | 1992-05-29 | Memc Electronic Materials S.P.A. | Procede d'obtention de profils de precipitation regules dans les tranches de silicium |
| GB2280312A (en) * | 1992-03-31 | 1995-01-25 | Mitel Corp | Method of preparing semiconductor with good intrinsic gettering |
| GB2280312B (en) * | 1992-03-31 | 1996-03-06 | Mitel Corp | Method of preparing semiconductor with good intrinsic gettering |
| WO1993020582A1 (fr) * | 1992-03-31 | 1993-10-14 | Mitel Corporation | Methode de preparation de semi-conducteurs avec une bonne aptitude inherente au piegeage de contaminants |
| KR960035771A (ko) * | 1995-03-14 | 1996-10-28 | 엔렌 에프 헨넬리 | 단결정 실리콘내의 산소 침착 생성핵 중심 농도 제어 방법 및 그 방법에 의해 제조된 단결정 실리콘 웨이퍼들로 이루어진 웨이퍼 세트 |
| US8733351B2 (en) | 1996-09-23 | 2014-05-27 | Resmed Limited | Method and apparatus for providing ventilatory assistance |
| US9974911B2 (en) | 1996-09-23 | 2018-05-22 | Resmed Limited | Method and apparatus for providing ventilatory assistance |
| GB2574879B (en) * | 2018-06-22 | 2022-12-28 | X Fab Semiconductor Foundries Gmbh | Substrates for III-nitride epitaxy |
| US12331426B2 (en) | 2018-06-22 | 2025-06-17 | X-Fab Semiconductor Foundries Gmbh | Substrates for III-nitride epitaxy |
Also Published As
| Publication number | Publication date |
|---|---|
| KR860000228B1 (ko) | 1986-03-15 |
| KR840000075A (ko) | 1984-01-30 |
| JPS57197827A (en) | 1982-12-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| 17P | Request for examination filed |
Effective date: 19820707 |
|
| AK | Designated contracting states |
Designated state(s): DE FR GB NL |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN |
|
| 18W | Application withdrawn |
Withdrawal date: 19840815 |
|
| RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: WATANABE, KIKUO Inventor name: TAKEMOTO, IWAO Inventor name: KISHINO, SEIGO Inventor name: TAKANO, YUKIO |