Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
  • H10W76/10—Containers or parts thereof
  • H10W76/12—Containers or parts thereof characterised by their shape
  • H10W76/13—Containers comprising a conductive base serving as an interconnection
  • H10W76/138—Containers comprising a conductive base serving as an interconnection having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/013—Manufacture or treatment of die-attach connectors
  • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
  • H10W72/07336—Soldering or alloying
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
  • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/321—Structures or relative sizes of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/381—Auxiliary members
  • H10W72/387—Flow barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads

Definitions

• This invention relates to a package for semiconductor diodes and, in particular, to button diodes in which the semiconductor die has a non-planar surface.
• the button diode is a particularly useful package configuration for semiconductor rectifiers and has achieved widespread commercial use.
• An example of this type of package is disclosed in U.S. patent 4,093,958.
• the improved, low-cost package described therein comprises a semiconductor diode chip or die soldered between two contact members, hereinafter called studs, having good thermal conductivity.
• the studs have a cross-section slightly larger than the semiconductor die.
• a planar face on each stud is soldered, respectively, to the planar and substantially parallel faces of the chip.
• the diode chip and the ends of the stud to which it is soldered are surrounded with' a suitable encapsulant which protects the chip and insulates the studs from each other. Because the major faces of the semiconductor chip are planar, the solder provides substantially uniform contact between the stud and semiconductor device across the whole area of the semiconductor die irrespective of its shape, whether round, square, or rectangular.
• the stud is provided with a boss or raised portion on the surface to be mated to the semiconductor chip. Since the studs have cylindrical symmetry, the boss usually also has cylindrical symmetry. Alternatively, a separate disk may substitute for the boss and be soldered to the stud at the same time as the die is attached.
• the circular boss or disk of the prior art provides a poor match to the rectangular semiconductor die typically utilized. The circular boss contacts less than 80% of available contact area on a rectangular chip which, in turn, increases the series resistance, and degrades the power handling capabilities of the device. Thus, a need continues to exist for a button diode design which overcomes the difficulties described above inherent in the use of non-planar die.
• a further object of the present invention is to provide improved transient response for semiconductor packages using non-planar rectangular die.
• solder of the appropriate strength, wetting and flow characteristics, melting temperature, shape, area and thickness will fill the moat present on the non-planar semiconductor die and reliably attach a non-planar die to a stud having a planar mounting face.
• solder-filling the moat metallic contact can be maintained between all portions of the die contact area and the planar stud mounting face so as to improve both thermal and electrical behavior of the device.
• FIG. 1 illustrates a cross-section of a package of the prior art for a rectangular planar chip, taken through the principal diagonal of the chip;
• FIG. 2 illustrates a cross-section of a package of the prior art for a rectangular non-planar chip taken through the principal diagonal of the chip
• FIG. 3 illustrates a cross-section of a package in accordance with the present invention utilizing a rectangular non-planar chip, taken through the principal diagonal of the chip.
• FIG. 1 shows semiconductor diode package 10 of the prior art wherein studs 11 and 12 having planar faces 16 and 17 are attached by solder regions 14 and 15 to rectangular semiconductor chip 13.
• semiconductor chip 13 has planar faces which may be readily attached by soldering to the planar faces of the studs.
• the studs are ordinarily cylindrically symmetric with respect to a line perpendicular to planar faces 16 and 17.
• Semiconductor die 13 may be of any shape so long as it fits within the perimeter of studs 11 and 12. Studs 11, 12 are normally identical in shape which is a significant manufacturing convenience.
• FIG. 2 shows semiconductor diode package 20.of the prior art for use with non-planar rectangular semiconductor chip 23.
• cylindrically symmetric stud 12 is soldered at 15 to semiconductor chip 23.
• Stud 21 of FIG. 2 has circular boss 26 which must fit within moat region
• FIG. 2 shows the approximate relationship of circular boss 26 lying within rectangular passivation region 25 so that non-contacted portion 29 of die contact surface 24 is readily apparent. Studs 21 and 22 are no longer identical, thus increasing the manufacturing cost and reducing the yield.
• Prior art attempts to overcome the deficiencies of the design of FIG. 2 include use of a small disk in place of boss 26 with additional solder joint 26a, and use of a rectangular boss or a rectangular insert to better match the shape of moat region 24-25. These approaches, however, are more costly and creates severe manufacturing problems, as for example, the rotational alignment of a rectangular insert or boss within a rectangular moat;
• cylindrically symmetric stud 31 of semiconductor diode package 30 is attached directly to semiconductor die 23 by solder region 37 which substantially fills moat region 24-25 and extends above
• solder 37 can extend beyond the perimeter of die 23 by a small amount 40, so long as shorts do not occur over the edge of the die onto edge 41 or to stud 12.
• Studs 31 and 12 are substantially identical which is a desirable manufacturing convenience.
• Die 23 may comprise any suitable shape. For example, where cost considerations are paramount, a square die can be.used. Where performance is paramount, a circular die slightly smaller in area than the studs can be used. Unlike most prior art devices for non-planar die, contact is made to the total exposed surface contact area 24 of semiconductor chip 23, irrespective of its shape.
• a 160 mil (4.1 mm) square, oxide passivated, platinum-silicide Schottky diode was soldered between electrodeless nickel plated copper studs of cylindrical form, each weighing 0.724 gm and having a 260 mil (6.6 mm) planar mounting face, utilizing a round solder preform of 125 mils (3.2 mm) diameter and 2.75 mils (0.069 mm) thick by heating the assembled parts in a controlled atmosphere furnace using hydrogen gas to a peak temperature of 372-385°C.
• upper stud 31 floats on molten solder puddle 37 whose area corresponds approximately to the die area plus small amount 40.
• Lead-tin solders in the composition range Pb (90%)/Sn (10%) to Pb (100%)/Sn (0%) are useful with Pb (95%)/Sn (5%) being preferred.
• the latter solder has a solidus-liquidus range of 306-314°C and yield strength of 3400 psi (23 MPa) .
• the solder completely fills moat 24-25 which is typically 0.04 mil, or (0.0001 mm) deep, and extends above passiva- tion region 25 by distance 39 of approximately 1.7 mils (0.04 mm).
• solder compositions were tried and found to be unsatisfactory, for example, Pb (92.5%)/In (5%)/Ag (2.5%) with a melting point of 307°C and yield strength of 4560 psi (31.4 MPa); Au (88%)/Ge (12%) with a melting point of 356°C and yield strength exceeding 7000 psi (48.2 MPa), and Au (80%)/Sn (20%) with melting point of 280°C and yield strength also exceeding 7000 psi (48.2 MPa). With these solders, die cracking and separation occurred.
• a first solder used to attach a die to studs or contact members must have a remelt temperature, that is, the temperature at which remelting occurs upon reheating a soldered device, which is greater than a second soldering temperature which will be employed by the user to mount the finished device.
• the minimum melt temperature of the first solder is chosen to be a few degrees above the minimum allowable remelt temperature, plus a safety margin. Typical values for these three temperatures are; a second soldering temperature of not more than about 250°C, a minimum first solder remelt temperature of 260-270°C, and a minimum first solder melt temperature of 270-280 c C. This combination gives satisfactory results.
• the maximum furnace temperature utilized must exceed the liquidus point, be below the point of destructive alloying with the silicon, and also be such that the solder does not become so fluid or the surface tension so low that it runs onto the stud surface significantly beyond the die perimeter and causes shorts.
• the maximum furnace tempera- ture may be conveniently determined by experiment.
• the solder shape, volume and surface tension, the stud weight and the die area must satisfy the following related criteria.
• the surface tension of solder is normally so high that if the molten solder is placed freely on the die it tends to form an oblate sphere. As the molten solder wets the die it spreads laterally and flattens, resembling an oblate hemisphere. A stud resting on the solder further compresses and spreads the molten puddle until the surface tension forces in the sidewall of the puddle balance the weight of the stud. If excessive weight or pressure is applied, the puddle effectively collapses so that the stud rests directly on passivation ring 25, the excess solder being squeezed beyond the chip periphery.
• solder wetting characteristics must also be considered.
• the solder must wet sufficiently well to insure a substantially void free bond to the contact surface of the die and the mating surface of the stud, but not so well as to flow across the stud surface and run out significantly beyond the die perimeter.
• the solder can extend for a small distance beyond the die perimeter on stud 31 as shown at 40 of FIG. 3, so long as it does not wet edge 41 of die 23 and cause shorts, or bridge the die and short to stud 12. Maintaining a solder puddle of the currect size and shape between the stud and the die is necessary.
• Pb (95%)/Sn (5%) solder provides the desired wetting characteristics on platinum-silicide and nickel plated copper contact surfaces, but not on gold or copper surfaces * Other solder combinations for other contact surfaces are readily determined by experiment.
• Solder is conveniently provided for the soldering operation as a preform, that is, a thin solder sheet cut to the appropriate size and shape and placed between the die and the studs prior to insertion in a soldering furnace.
• a simple alignment fixture holds the pieces in a stacked relationship. Since solder wetting is desired to be limited substantially to an area within or approximately coincident with the chip perimeter plus small extension 40, it is desired to use a solder preform smaller than the die and preferably able to fit within moat 24-25.
• a solder preform area 45-55% of the die area is a convenient value. The preform is aligned to lie within the chip boundary prior to soldering.
• the thickness of the preform is adjusted to give a solder volume sufficient to fill the moat and give a predetermined additional thickness 39. Satisfactory values for total solder thickness 38 have been found experimentally to be from approximately 0.5 mil (0.013 mm) to approximately 3 mils (0.076 mm) with 1.0 to 2.0 mils (0.025 - 0.051 mm) being a preferred range. Beyond approximately 3 mils (0.076 mm), excess solder runs out beyond the die perimeter and edge shorting occurs. Below 0.5 mil (0.013 mm) die cracking is increasingly troublesome.
• the area of the frozen solder should preferably cover the contact area within the moat.
• the maximum area is limited to approximately the chip area, the determining requirement being to avoid edge shorts at the die periphery.
• the differential thermal expansion and contraction of the stud and the semiconductor die create large shear forces which, unless relieved, can fracture the relatively brittle semiconductor die or the interfaces with the solder.
• the thickness of the frozen solder must be sufficient to fill the moat plus provide a stress relief cushion whose thickness 38 must be in the range of approximately 0.5-3 mils (0.013-0.076mm) preferably 1.0-2.0 mils (0.025 - 0.051 mm).
• solder must be chosen from the class of materials whose yield strength is less than that of the semiconductor die or interfaces, but larger than the value corresponding to the minimum pull strength, e.g. 1250 psi or 8.6 MPa, which the finished device must withstand.
• Materials having yield strength of 3400 psi (23.4 MPa) have been found to be acceptable. They allow the solder to undergo plastic flow to relieve stress without damage to the device. Solder materials with yield strength equal to or greater than 4560-7000 psi (31-48 MPa) produced excessive breakage. This is an unexpected result, since from the known breaking strength of single crystal silicon (25,000-60,000 psi; 172-413 MPa) one would not expect solders with yield strength as low as 4560-7000 psi (31-48 MPa) to produce breakage.
• the thermal impedance between the junction and an external heat sink is different for the upper and lower studs because of the presence of boss 26 in FIG. 2, this difference typically being in the range of 20-40%.
• the thermal impedance of the invented device structure of FIG. 3 is substantially symmetrical, and superior to that of the prior art device.
• Assembly is facilitated with structures in accordance with the present invention. Since the studs are identical, no additional piece parts are required and no special alignment is needed. This results in lower manufacturing cost and higher yield.

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• 1981
  • 1981-12-21 EP EP19820900484 patent/EP0070862A4/fr not_active Withdrawn
  • 1981-12-21 BR BR8108967A patent/BR8108967A/pt unknown
  • 1981-12-21 WO PCT/US1981/001731 patent/WO1982002798A1/fr not_active Ceased
• 1982
  • 1982-01-08 CA CA000393799A patent/CA1177580A/fr not_active Expired
  • 1982-01-13 IT IT47549/82A patent/IT1147576B/it active
  • 1982-01-29 MX MX191200A patent/MX151124A/es unknown

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