EP0077771A1 - Circuit de commande de limitation d'intensite - Google Patents

Circuit de commande de limitation d'intensite

Info

Publication number
EP0077771A1
EP0077771A1 EP19810901625 EP81901625A EP0077771A1 EP 0077771 A1 EP0077771 A1 EP 0077771A1 EP 19810901625 EP19810901625 EP 19810901625 EP 81901625 A EP81901625 A EP 81901625A EP 0077771 A1 EP0077771 A1 EP 0077771A1
Authority
EP
European Patent Office
Prior art keywords
transistor
terminal
gate
node
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19810901625
Other languages
German (de)
English (en)
Inventor
Robert J. Proebsting
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CTU of Delaware Inc
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Publication of EP0077771A1 publication Critical patent/EP0077771A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Definitions

  • the present invention pertains to driver circuits in logic applications and more particularly pertains to such driver circuits which must have a current limited output.
  • an output data state is produced at an output terminal.
  • the output terminal is then connected to deliver the output signal to other circuit elements.
  • the output terminal is typically driven to high and low voltage states. If the output terminal should become grounded when the circuit is attempting to drive it to a high voltage state there may be a heavy current flow through the driving circuit. If no means are provided for limiting current flow through the output terminal, the surge of current can frequently be sufficient to damage the driving circuit.
  • the provision of a current limiting resistor has the disadvantage that it slows the driver circuit in driving the output terminal to the desired voltage state.
  • a current limiting circuit which drives an output node to selected logic states in response to an input signal.
  • a driver transistor is included in the circuit and has the gate terminal thereof connected to receive a control signal, the drain terminal thereof connected to a power terminal and the source terminal thereof connected to the output node.
  • Circuitry is connected between the gate and source terminals of the driver transistor to limit the maximum voltage difference therebetween to a predetermined voltage thereby limiting the current flow through the driver transistor.
  • circuitry is provided to isolate the output node to leave it in a high impedance condition.
  • FIGURE 1 is a schematic illustration of a first embodiment of a current limiting driver circuit
  • FIGURE 2 is a schematic illustration of a second embodiment of a current limiting driver circuit.
  • FIGURE 1 A first embodiment of a current limiting driver circuit in accordance with the present invention is illustrated in FIGURE 1 and designated generally by the reference numeral 10.
  • Circuit 10 includes a depletion mode pull-up transistor 12 which has the gate and source terminals thereof connected to a node 14. The drain terminal of transistor 12 is connected to a first power terminal V •
  • a pull-down transistor 16 has the gate terminal connected to receive a logic level input signal 0 ⁇ - - The drain terminal of transistor 16 is connected to node 14 and the source terminal of transistor 16 is connected to ground.
  • a pull-down transistor 17 has the gate terminal thereof connected to receive a logic level input signal 9>2 ' Tne drain terminal of transistor 17 is connected to node 14 and the source terminal is connected to ground.
  • a transistor 18 has the gate and drain terminals thereof connected to node 14.
  • a transistor 20 has the gate and drain terminals thereof connected to the source terminal of transistor 18.
  • a transistor 22 has the gate and drain terminals thereof connected to the source terminal of transistor 20.
  • the source terminal of transistor 22 is connected to an output node 24 which is in turn connected to an output pin 26. Output data is transmitted through the pin 26.
  • a driver transistor 28 has the gate terminal thereof connected to node 14, the drain terminal thereof connected to the power terminal V nd the source terminal thereof connected to the output node 24.
  • a pull-down transistor 30 has the gate terminal thereof connected to receive the logic level input signal 0-, , the drain terminal thereof connected to node 24 and the source terminal thereof connected to ground.
  • a pull-down transistor 32 has the gate terminal thereof connected to receive the 0 ⁇ input signal, the
  • OMPI /., WIPO drain terminal thereof connected to the line which receives the 0-, signal and the source terminal thereof grounded.
  • circuit 10 Operation of circuit 10 is now described in reference to FIGURE 1.
  • the purpose of circuit 10 is to drive the output pin 26 to a logic state determined by the state of the input signal 0-. • It is the objective of circuit 10 that the output pin be driven very quickly between the logic states and that the output pin be pulled to a high voltage state, typically one V. (voltage threshold) below the supply voltage V • However, there is the possibility through a system fault that the output pin 26 can become grounded when circuit 10 is attempting to drive it to a high logic state.
  • transistors 16, 17 and 32 When the 0- ⁇ and 0 ⁇ signals are at the low voltage state transistors 16, 17 and 32 will be turned off. When transistors 16 and 17 are turned off transistor 12 pulls node 14 to a high voltage state. Note that the maximum voltage at node 14 can be limited as described below.
  • transistor 28 When node 14 is at a high voltage state transistor 28 is turned on thereby pulling the output node 24 high. The 0 ⁇ - signal turns off transistor 30 thereby isolating node 24 from ground. Under these conditions the output pin 26 is driven to a high voltage state.
  • transistors 16 and 30 When the input signal 0-, is at a high voltage state and the input signal 0 ⁇ is at a low voltage state transistors 16 and 30 will be turned on while transistors 17 and 32 will be turned off.
  • transistor 16 When transistor 16 is turned on node 14 is pulled to ground which causes transistor 28 to be turned off.
  • transistor 30 When transistor 30 is turned on the output node 24 is pulled to ground. The output pin 26 is thus driven to a low voltage state.
  • the logic state at pin 26 is the complement of the logic state of 0- ⁇ - Whenever the input signal 02 goes to a high voltage state transistors 17 and 32 are turned on. When transistor 17 is turned on node 14 is pulled to ground
  • the transistors 18, 20 and 22 serve to limit the maximum voltage difference between the gate and source terminals of driver transistor 28.
  • the gate-to- source voltage of transistor 28 exceeds the cumulative threshold voltages (V ⁇ ) of transistors 18, 20 and 22 these transistors will be turned on thereby providing a relatively low impedance path between nodes 14 and 24 which in turn holds down the gate-to-source voltage of transistor 28. Since the current flow through transistor 28 is a function of the gate-to-source voltage the limiting of the bias voltage serves to also limit the maximum current flow through transistor 28.
  • transistors 18, 20 and 22 will be turned on reducing the voltage on node 14 to reduce the gate-to-source voltage of transistor 28 thereby limiting the current which flows into the output pin 26.
  • Transistors 17 and 32 are included in circuit 10 to provide a high impedance state to the output pin 26. If such a high impedance state is not required, these transistors can be deleted from circuit 10.
  • each of the transistors is designed to have a minimum channel length.
  • the transistors 18, 20 and 22 can have a width of 300 microns.
  • the combined "on" impedance of transistors 18, 20 and 22 is made substantially smaller than the "on” impedance of transistor 12 such that node 14 is limited to a maximum voltage slightly more than 3 V. above the voltage at node 24.
  • FIGURE 2 A further embodiment of the present invention is illustrated in FIGURE 2 and the circuit therein is designated generally by the reference numeral 40.
  • the first logic level input signal 0- is supplied to the gate terminal of a pull-down transistor 42.
  • the drain terminal of transistor 42 is connected to a node 44 and the source terminal of transistor 42 is connected to ground.
  • a pull-down transistor 45 receives the 2 ⁇ ignal at the gate terminal thereof, has the drain terminal thereof connected to node 44 and the source terminal thereof grounded.
  • a pull-up depletion node transistor 46 has the gate and source terminals thereof connected to node 44 and the drain terminal thereof connected to the power terminal
  • Node 44 is connected to the gate terminal of a driver transistor 48 which has the drain terminal thereof connected to the power terminal V •
  • the source terminal of transistor 48 is connected to an output node 50 which is in turn connected to a data output pin 52.
  • a transistor 54 has the gate and drain terminals thereof connected to node 44.
  • a transistor 56 has the gate and drain terminals thereof connected to the source terminal of transistor 54.
  • a transistor 58 has the gate and drain terminals thereof connected to a node 60 and the source terminal thereof connected to node 50. The source terminal of transistor 56 is connected to node 60.
  • a transistor 64 has the gate terminal thereof connected to node 60, the drain terminal thereof connected to node 44 and the source terminal thereof is connected to node 50.
  • a pull-down transistor 66 is connected to receive the logic level input signal 0-, at the gate terminal thereof. The drain terminal of transistor 66 is connected to node 50 and the source terminal thereof is connected to ground.
  • a pull-down transistor 67 has the gate terminal thereof connected to receive the input signal 02 ' the drain terminal thereof connected to the line which receives the 0-, signal and the source terminal thereof connected to ground.
  • a further transistor 68 is connected to receive the input signal 02 at the gate terminal thereof.
  • the drain terminal of transistor 68 is connected to node 60 and the source terminal of transistor 68 is connected to ground.
  • circuit 40 The function of circuit 40 is the same as that of circuit 10 in that the output pin 52 is driven to logic states in response to the input signal 0 ⁇ - - Further, circuit means are provided for limiting the current flow through transistor 48 of circuit 40 when pin 52 is grounded.
  • transistors 42, 45, 66, 67 and 68 are turned off.
  • node 44 is pulled to a high voltage state by transistor 46.
  • the high voltage state on node 44 turns on transistor 48 thereby pulling node 50 to a high state.
  • the low voltage state of signal 0- produces a high voltage state at the output pin 52.
  • Node 50 is isolated from ground since transistor 66 is turned off.
  • transistors 42 and 66 When the input signal 0-, is at a high voltage state and the input signal 02 ⁇ s a *- a l° w voltage state transistors 42 and 66 will be turned on while transistors 45, 67 and 68 will be turned off.
  • transistor 42 When transistor 42 is turned on node 44 is pulled to ground thereby turning off transistor 48.
  • transistor 66 When transistor 66 is turned on the output node 50 is pulled to ground thereby driving the output pin 52 to a low voltage state.
  • the logic state at output 52 is the complement of the logic state of signal 0-, when output disable signal 2 is at a low voltage state.
  • transistor 68 When the input terminal 0 2 ⁇ s at a -*- ow voltage state transistor 68 is turned off thereby permitting transistors 58 and 64 to be turned on or off depending upon the voltage differential between nodes 44 and 50.
  • transistors 45, 67 and 68 will be turned on.
  • transistor 45 When transistor 45 is turned on node 44 is pulled to a low voltage state thereby turning off transistor 48.
  • transistor 67 is turned on the line carrying signal 0-, is forced to ground thereby turning transistor 66 off.
  • transistor 68 When transistor 68 is turned on the node 60 is pulled to a low voltage state thereby turning off transistors 64 and 58.
  • transistors 48, 64, 66 and 68 turned off node 50 is left in a floating condition thereby providing a high impedance to the output pin 52.
  • the high impedance condition is produced whenever the input signal 02 goes to a high voltage state.
  • the transistor 58 is fabricated to have a substantially greater "on" impedance than that of either of the transistors 54 and 56.
  • V ⁇ combined voltage thresholds
  • transistor 58 Since the impedance of transistor 58 is substantially greater than that of transistors 54 and 56 when all three transistors are turned on, most of the voltage difference in excess of 2 V. between nodes 44 and 50 will be developed between nodes 60 and 50. This serves to turn on transistor 64 to reduce the voltage on node 44 to approximately 3 V. above that of node 50. Therefore, if node 44 should be at a high state and pin 52 should become grounded the transistors 54, 56 and 58 will be turned on thereby applying a positive bias to the gate terminal of transistor 64 which is then turned on to lower the voltage on node 44 thereby limiting the current flow through transistor 48.
  • the "on” impedance of transistor 64 is made to be substantially less than that of transistor 46 such that the maximum voltage on node 44 can be limited to slightly more than 3 V. above the voltage at node 50.
  • circuit 40 provides essentially the same function as that of circuit 10 it offers substantial space savings over that of circuit 10.
  • the transistors 54 and 56 can be 20 microns wide while the transistor 58 is made five microns wide.
  • the transistor 64 is fabricated to be 100 microns wide. It can be seen that the combined serial "on" impedance of transistors 18, 20 and 22 in FIGURE 1 is essentially equal to the "on" impedance of transistor 64.
  • the circuit 40 utilizes approximately 145 units of area while the circuit of FIGURE 1 utilizes approximately 900 units of area.
  • the current limiting portion of circuit 40 provides essentially the same current limiting function as circuit 10 but has approximately a factor of six savings in area on an integrated circuit chip.
  • the transistors 45, 67 and 68 are included in circuit 40 to provide a high impedance state to output pin 52. If such a high impedance state is not required, these transistors can be deleted from circuit 40.
  • the present invention comprises a current limiting driver circuit in which the output terminal can be rapidly charged and pulled to a relatively high voltage state but with the provision that the maximum current through the driver transistor is limited to a predetermined safe level.
  • transistors described herein are n-channel, enhancement mode devices, however, it is recognized that an equivalent circuit can be fabricated using p-channel type devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)

Abstract

Un circuit de commande de limitation d'intensite (10) recoit un premier signal d'entree de niveau logique (01) et commande une broche de sortie (26). Un noeud (14) est tire a la terre par un transistor d'abaissement (16) qui recoit le premier signal d'entree (01) et est entraine vers un etat de haute tension par un transistor de montee (12). Un transistor de commande (28) est excite par un etat de haute tension au niveau du noeud (14) et est coupe par un etat basse tension au niveau du noeud (14). Le transistor de commande (28) est connecte pour fournir un etat haute tension sur la broche de sortie (26). Un transistor d'abaissement (30) est connecte pour recevoir le premier signal d'entree (01) de maniere a ramener la broche de sortie (26) a la terre. Une serie de transistors (18, 20, 22) sont connectes entre les bornes de porte et de source du transistor de commande (28) de sorte que lorsque la tension de porte-a-source du transistor de commande (28) depasse les seuils combines des trois transistors (18, 20, 22) ceux-ci seront excites et limiteront par consequent la tension maximum porte-a-source du transistor de commande (28). Ceci, a son tour, sert a limiter l'intensite maximum du courant passant par le transistor de commande (28). Des transistors d'invalidation (17, 32) sont prevus pour produire une sortie d'impedance elevee sur la broche de sortie (26).
EP19810901625 1981-04-16 1981-04-16 Circuit de commande de limitation d'intensite Withdrawn EP0077771A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1981/000497 WO1982003737A1 (fr) 1981-04-16 1981-04-16 Circuit de commande de limitation d'intensite

Publications (1)

Publication Number Publication Date
EP0077771A1 true EP0077771A1 (fr) 1983-05-04

Family

ID=22161187

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19810901625 Withdrawn EP0077771A1 (fr) 1981-04-16 1981-04-16 Circuit de commande de limitation d'intensite

Country Status (2)

Country Link
EP (1) EP0077771A1 (fr)
WO (1) WO1982003737A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE515490C2 (sv) * 1993-12-03 2001-08-13 Ericsson Telefon Ab L M Signaleringssystem

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651340A (en) * 1970-06-22 1972-03-21 Hamilton Watch Co Current limiting complementary symmetry mos inverters
US3913026A (en) * 1974-04-08 1975-10-14 Bulova Watch Co Inc Mos transistor gain block
US3906255A (en) * 1974-09-06 1975-09-16 Motorola Inc MOS current limiting output circuit
US4065678A (en) * 1976-07-02 1977-12-27 Motorola, Inc. Clamped push-pull driver circuit with output feedback
US4096398A (en) * 1977-02-23 1978-06-20 National Semiconductor Corporation MOS output buffer circuit with feedback
US4275313A (en) * 1979-04-09 1981-06-23 Bell Telephone Laboratories, Incorporated Current limiting output circuit with output feedback

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8203737A1 *

Also Published As

Publication number Publication date
WO1982003737A1 (fr) 1982-10-28

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