EP0077778A1 - Planar transistor structure - Google Patents

Planar transistor structure

Info

Publication number
EP0077778A1
EP0077778A1 EP82900350A EP82900350A EP0077778A1 EP 0077778 A1 EP0077778 A1 EP 0077778A1 EP 82900350 A EP82900350 A EP 82900350A EP 82900350 A EP82900350 A EP 82900350A EP 0077778 A1 EP0077778 A1 EP 0077778A1
Authority
EP
European Patent Office
Prior art keywords
zone
base
passivation layer
conductivity
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP82900350A
Other languages
German (de)
French (fr)
Inventor
Michel Hartmut
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP0077778A1 publication Critical patent/EP0077778A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/281—Base electrodes for bipolar transistors

Definitions

  • the invention is based on a planar transistor structure according to the preamble of the patent claim.
  • Such transistor structures are known. However, they have the disadvantage that external electrical fields, as they e.g. through the polarization of masking varnishes, stirring to the degradation of blocking characteristics.
  • planar transistor structure according to the invention has the advantage, in contrast, that the construction charge zone which forms, inter alia, the base zone herua is under the extended emitter bav. 3Asal metallization is limited within the annular zone and is shielded from the outer fields below the extended metallization.
  • FIG. 1 shows a partial section through the first exemplary embodiment
  • FIG. 2 shows a partial section through the second exemplary embodiment of the planar transistor structure according to the invention.
  • 10 denotes a semiconductor wafer with n conductivity.
  • a p-conductive base zone 11 is penetrated into the semiconductor die 10 from above.
  • An emitter zone 12 is infused into the base zone 11 from the same main surface of the semiconductor die 10. This has n + conductivity.
  • a passivation layer 13 extends over the top of the semiconductor die 10, but is interrupted at various points to form remote contacts.
  • a metallization 14 is provided for contacting the emitter zone 12. It forms the emitter connection, which is indicated at E.
  • a metallization 15 is provided, which at the same time forms the base connection, which is symbolically indicated at 3.
  • the collector connection is indicated.
  • an n-type annular zone 16 is diffused into the n-type collector material of the semiconductor die 10.
  • This zone 16 is arranged at a certain distance from the base zone 11 and completely surrounds the base zone 11.
  • the base metallization 15 also extends over the passivation layer 13 into the area above the annular zone 16.
  • the respective conductivity type of these areas 10, 11, 12 is designed in accordance with the exemplary embodiment according to FIG. 1.
  • the Eaitteraetallmaschine is vieder ait 14, the base metallization ait 15 designated.
  • the emitter connection is symbolically indicated at E, the base connection at 3 and the collector connection at C.
  • an n + -conductive annular zone 16 is also provided in the embodiment according to FIG. Zone 16 is also covered here by passivation layer 13.
  • the emitter metallization 14 is extended to the area above the annular zone 16.
  • the operation of the building charge zone forming around the base zone 11 is limited to the area between the base zone 11 and the zone 16 and is thereby shielded from external electrical fields.

Landscapes

  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Structure plane de transistor constitue d'une plaquette de semiconducteur de conductivite n- formant une zone de collecteur et presentant une zone de base (11) et une zone d'emetteur (12) de conductivite n+ diffusees dans sa surface superieure et une couche de passivation (13). La couche de passivation (13) recouvre les parties de la surface superieure de la plaquette (10) qui ne servent pas de fenetre de contact. Dans le materiau de collecteur de conductivite n- est diffusee une zone annulaire de conductivite n+ qui entoure complete ment la zone de base (11). La couche de passivation s'etend sur cette zone annulaire (16). Soit la metallisation d'emetteur (14), soit la metallisation de la base (15) est prolongee au-dessus de la couche de passivation jusque dans la region de la zone annulaire (16).Planar transistor structure consisting of a semiconductor wafer of n- conductivity forming a collector region and having a base region (11) and an emitter region (12) of n+ conductivity diffused in its upper surface and a passivation layer (13). The passivation layer (13) covers the parts of the upper surface of the wafer (10) which do not serve as a contact window. In the collector material of n- conductivity is diffused an annular region of n+ conductivity which completely surrounds the base region (11). The passivation layer extends over this annular region (16). Either the emitter metallization (14) or the base metallization (15) is extended above the passivation layer into the region of the annular region (16).

Description

Planare Transistorstruktur Planar transistor structure

Stand der TechnikState of the art

Die Erfindung geht aus von einer planaren Transistorstruktur nach der Gattung des Patentanspruchs. Derartige Transitorstrukturen sind bekannt. Sie haben aber den nachteil, daß äußere elektrische Felder, vie sie z.B. durch Polarisation von Abdecklacken entstehen, zur Degradation von Sperrkennlinien rühren kennen.The invention is based on a planar transistor structure according to the preamble of the patent claim. Such transistor structures are known. However, they have the disadvantage that external electrical fields, as they e.g. through the polarization of masking varnishes, stirring to the degradation of blocking characteristics.

Vorteile der ErfindungAdvantages of the invention

Die erfindungsgemäße planare Transistorstruktur mit den kennzeichnenden Merkaalen des Patentanspruchs hat demgegenüber den Vorteil, daß die sich is Betrieb ua die Basiszone herua ausbildende Bauciadungszone unter der verlängerten Emitter- bav. 3asismetallisierung innerhalb der ringfδraigen Zone begrenzt vird und unterhalb der verlängerten Metallisierung von den äußeren Feldern abgeschirmt vird.The planar transistor structure according to the invention, with the characterizing features of the patent claim, has the advantage, in contrast, that the construction charge zone which forms, inter alia, the base zone herua is under the extended emitter bav. 3Asal metallization is limited within the annular zone and is shielded from the outer fields below the extended metallization.

Zeichnungdrawing

Zwei Aus-Tüarungsbeispiele der erfinάunεsgeffiäßen planeren Transistorstruktur sind in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Es zeigen: Figur 1 einen Teilschnitt durch das erste Ausführungsbeispiel, Figur 2 einen Teilschnitt durch das zveite Ausführungsbeispiel der planaren Transistorstruktur gemäß der Erfindung.Two exemplary examples of the planer transistor structure according to the invention are shown in the drawing and explained in more detail in the description below. FIG. 1 shows a partial section through the first exemplary embodiment, FIG. 2 shows a partial section through the second exemplary embodiment of the planar transistor structure according to the invention.

Beschreibung der AusführungsbeispieleDescription of the embodiments

In Figur 1 ist mit 10 ein Halbleiterplättchen mit n--Leitfähigkeit bezeichnet. In das Halbleiterplättchen 10 ist von oben her eine p- leitfähige Basiszone 11 eindirfuπdiert. In die Basiszone 11 ist von derselben Hauptoberfläche des Halbleiterplättchens 10 aus eine Emitterzone 12 eindi'fundiert. Diese hat n+-Leitfähigkeit. Über die Oberseite des Halbleiterplättchens 10 erstreckt sich eine Passivierungsschicht 13, die jedoch an verschiedenen Stellen zur Bildung von Kontaktrfernstem unterbrochen ist. Zur Kontaktierung der Emitterzone 12 ist eine Metallisierung 14 vorgesehen. Sie bildet den Emitteranschluß, der bei E angedeutet ist. Zur Kontaktierung der Basiszone 11 ist eine Metallisierung 15 vorgesehen, die gleichzeitig den Basisanschluß bildet, der symbolisch bei 3 angedeutet ist. Bei C ist der KollektoranschluS angedeutet.In FIG. 1, 10 denotes a semiconductor wafer with n conductivity. A p-conductive base zone 11 is penetrated into the semiconductor die 10 from above. An emitter zone 12 is infused into the base zone 11 from the same main surface of the semiconductor die 10. This has n + conductivity. A passivation layer 13 extends over the top of the semiconductor die 10, but is interrupted at various points to form remote contacts. A metallization 14 is provided for contacting the emitter zone 12. It forms the emitter connection, which is indicated at E. For contacting the base zone 11, a metallization 15 is provided, which at the same time forms the base connection, which is symbolically indicated at 3. At C the collector connection is indicated.

Erfindungsgemäß ist in das n--leitende Kollektormaterial des Halbleiterplättchens 10 eine n -leitende ringförmige Zone 16 eindiffundiert. Diese Zone 16 ist in einem bestimmten Abstand von der Basiszone 11 angeordnet und umschließt die Basiszone 11 vollständig. Er- findungsgemäß erstreckt sieh ferner die Basismetallisierung 15 über die Passivierungsschicht 13 hinveg bis in den Bereϊch oberhalb der ringförmigen Zone 16. Durch diese Maßnahmen vird erreicht, daß die Haumladungszone, die sich um die Basiszone 11 herum beim Betrieb der Anordnung ausbildet, sich nur noch bis zu der ringförmigen Zone 16 erstreckt und so durch die verlängerte Metallisierung 15 ver äußeren elektrischen Feldern abgeschirmt vird. In Figur 2 ist ein zveites Ausführungsbeispiel dargestellt. Das Halbleiterplättchen ist vieder mit 10, die Basiszone ait 11 und die Emitterzone mit 12 bezeichnet. Der jeweilige Leitfähigkeitstyp dieser Bereiche 10, 11, 12 ist übereinstimmend mit dem Ausführungsbeispiel nach Figur 1 ausgebildet. Die Eaitteraetallisierung ist vieder ait 14, die Basismetallisierung ait 15 bezeichnet. Der Emitteranschluß ist vieder symbolisch bei E, der Basisansehluß bei 3 und der Kollektor- anschluß bei C angedeutet.According to the invention, an n-type annular zone 16 is diffused into the n-type collector material of the semiconductor die 10. This zone 16 is arranged at a certain distance from the base zone 11 and completely surrounds the base zone 11. According to the invention, the base metallization 15 also extends over the passivation layer 13 into the area above the annular zone 16. These measures ensure that the hair transhipment zone which forms around the base zone 11 when the arrangement is in operation is only formed extends up to the annular zone 16 and is thus shielded by the extended metallization 15 ver external electrical fields. A second exemplary embodiment is shown in FIG. The semiconductor wafer is denoted by 10, the base zone by 11 and the emitter zone by 12. The respective conductivity type of these areas 10, 11, 12 is designed in accordance with the exemplary embodiment according to FIG. 1. The Eaitteraetallisierung is vieder ait 14, the base metallization ait 15 designated. The emitter connection is symbolically indicated at E, the base connection at 3 and the collector connection at C.

Erfindungsgemäß ist auch bei dem Ausführungsbeispiel nach Figur 2 eine n+-leitfihige ringförmige Zone 16 vorgesehen, die die Basiszone 11 in einem bestimmten Abstand ringförmig uaschließt. Die Zone 16 ist auch hier von der Passivierungsschicht 13 bedeckt. In Unterschied zum Ausführungsbeispiel nach Figur 1 ist hier die Emitteraetallisierung 14 bis in den Bereich oberhalb der ringförmigen Zone 16 verlängert. Auch hier vird vieder ia Betrieb die sieh um die Basiszone 11 ausbildende Baualadungszone auf den Bereich zvischen der Basiszone 11 und der Zone 16 beschränkt und dadurch vor äußeren elektrischen Feldern abgeschirmt. According to the invention, an n + -conductive annular zone 16 is also provided in the embodiment according to FIG. Zone 16 is also covered here by passivation layer 13. In contrast to the exemplary embodiment according to FIG. 1, the emitter metallization 14 is extended to the area above the annular zone 16. Here too the operation of the building charge zone forming around the base zone 11 is limited to the area between the base zone 11 and the zone 16 and is thereby shielded from external electrical fields.

Claims

Anspruchclaim Planare Transistorstruktur mit einem die Kollektorzone bildenden Halbleiterplättchen (10) ait n--Leitfähigkeit, einer in eine Hauptoberfläche des Halbleiterplättchens (10) eindiffundierten Basiszone (11) ait p-Leitfähigkeit, einer in die Basiszone (11) einciffundierten Emitterzone (12) mit n+-Leitfähigkeit und mit einer Passivierungsschicht (13), die diejenigen Teile der Eauptoberflache des Halbleiterplättchens (10) bedeckt, die nicht als Kontaktfenster dienen, dadureh gekennzeichnet, da£ in das n--leitende Kollektoraaterial eine a -leitende ringförmige Zone (10) eindiffundiert ist, die die Basiszone (11) vollständig uaschließt, daß die Passivierungsschicht (13) sieh über diese ringförmige Zone (16) hinweg erstreckt und daß entweder die Emitter metallisierung (14) oder die Basismetallisierung (15) über die Passivierungsschicht (13) hinveg bis in den Bereich oberhalb der ringförmigen Zone (15) verlängert ist. Planar transistor structure with a semiconductor wafer (10) with n conductivity forming the collector zone, a base zone (11) with p conductivity diffused into a main surface of the semiconductor wafer (10), an emitter zone (12) with n diffused into the base zone (11) + Conductivity and with a passivation layer (13) which covers those parts of the main surface of the semiconductor die (10) which do not serve as a contact window, characterized because £ in the n-type collector material an a-type annular zone (10) is diffused, which completely closes the base zone (11), that the passivation layer (13) extends over this annular zone (16) and that either the emitters metallization (14) or the base metallization (15) over the passivation layer (13) is extended to the area above the annular zone (15).
EP82900350A 1981-05-06 1982-02-05 Planar transistor structure Withdrawn EP0077778A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3117804 1981-05-06
DE19813117804 DE3117804A1 (en) 1981-05-06 1981-05-06 "PLANAR TRANSISTOR STRUCTURE"

Publications (1)

Publication Number Publication Date
EP0077778A1 true EP0077778A1 (en) 1983-05-04

Family

ID=6131535

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82900350A Withdrawn EP0077778A1 (en) 1981-05-06 1982-02-05 Planar transistor structure

Country Status (4)

Country Link
EP (1) EP0077778A1 (en)
JP (1) JPS58500679A (en)
DE (1) DE3117804A1 (en)
WO (1) WO1982003949A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3276091D1 (en) * 1981-12-24 1987-05-21 Nippon Denso Co Semiconductor device including overvoltage protection diode
DE3201545A1 (en) * 1982-01-20 1983-07-28 Robert Bosch Gmbh, 7000 Stuttgart PLANAR SEMICONDUCTOR ARRANGEMENT
JPS61114574A (en) * 1984-11-09 1986-06-02 Hitachi Ltd semiconductor equipment
EP0309784A1 (en) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Contact strip structure for bipolar transistors
EP0360036B1 (en) * 1988-09-20 1994-06-01 Siemens Aktiengesellschaft Planar pn-junction having a high withstand voltage

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1249812A (en) * 1969-05-29 1971-10-13 Ferranti Ltd Improvements relating to semiconductor devices
GB1348697A (en) * 1970-07-31 1974-03-20 Fairchild Camera Instr Co Semiconductors
JPS5139400B2 (en) * 1971-10-01 1976-10-27
JPS50137478A (en) * 1974-04-18 1975-10-31
JPS573225B2 (en) * 1974-08-19 1982-01-20
JPS5412793A (en) * 1977-06-29 1979-01-30 Mitsubishi Electric Corp Concentration measuring method of solutions
JPS5556656A (en) * 1978-10-23 1980-04-25 Nec Corp Semiconductor device
JPS5674961A (en) * 1979-11-22 1981-06-20 Hitachi Ltd Smiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8203949A1 *

Also Published As

Publication number Publication date
JPS58500679A (en) 1983-04-28
DE3117804A1 (en) 1982-11-25
WO1982003949A1 (en) 1982-11-11

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Inventor name: HARTMUT, MICHEL