EP0077778A1 - Structure plane de transistor - Google Patents

Structure plane de transistor

Info

Publication number
EP0077778A1
EP0077778A1 EP82900350A EP82900350A EP0077778A1 EP 0077778 A1 EP0077778 A1 EP 0077778A1 EP 82900350 A EP82900350 A EP 82900350A EP 82900350 A EP82900350 A EP 82900350A EP 0077778 A1 EP0077778 A1 EP 0077778A1
Authority
EP
European Patent Office
Prior art keywords
zone
base
passivation layer
conductivity
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP82900350A
Other languages
German (de)
English (en)
Inventor
Michel Hartmut
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP0077778A1 publication Critical patent/EP0077778A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/281—Base electrodes for bipolar transistors

Definitions

  • the invention is based on a planar transistor structure according to the preamble of the patent claim.
  • Such transistor structures are known. However, they have the disadvantage that external electrical fields, as they e.g. through the polarization of masking varnishes, stirring to the degradation of blocking characteristics.
  • planar transistor structure according to the invention has the advantage, in contrast, that the construction charge zone which forms, inter alia, the base zone herua is under the extended emitter bav. 3Asal metallization is limited within the annular zone and is shielded from the outer fields below the extended metallization.
  • FIG. 1 shows a partial section through the first exemplary embodiment
  • FIG. 2 shows a partial section through the second exemplary embodiment of the planar transistor structure according to the invention.
  • 10 denotes a semiconductor wafer with n conductivity.
  • a p-conductive base zone 11 is penetrated into the semiconductor die 10 from above.
  • An emitter zone 12 is infused into the base zone 11 from the same main surface of the semiconductor die 10. This has n + conductivity.
  • a passivation layer 13 extends over the top of the semiconductor die 10, but is interrupted at various points to form remote contacts.
  • a metallization 14 is provided for contacting the emitter zone 12. It forms the emitter connection, which is indicated at E.
  • a metallization 15 is provided, which at the same time forms the base connection, which is symbolically indicated at 3.
  • the collector connection is indicated.
  • an n-type annular zone 16 is diffused into the n-type collector material of the semiconductor die 10.
  • This zone 16 is arranged at a certain distance from the base zone 11 and completely surrounds the base zone 11.
  • the base metallization 15 also extends over the passivation layer 13 into the area above the annular zone 16.
  • the respective conductivity type of these areas 10, 11, 12 is designed in accordance with the exemplary embodiment according to FIG. 1.
  • the Eaitteraetallmaschine is vieder ait 14, the base metallization ait 15 designated.
  • the emitter connection is symbolically indicated at E, the base connection at 3 and the collector connection at C.
  • an n + -conductive annular zone 16 is also provided in the embodiment according to FIG. Zone 16 is also covered here by passivation layer 13.
  • the emitter metallization 14 is extended to the area above the annular zone 16.
  • the operation of the building charge zone forming around the base zone 11 is limited to the area between the base zone 11 and the zone 16 and is thereby shielded from external electrical fields.

Landscapes

  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Structure plane de transistor constitue d'une plaquette de semiconducteur de conductivite n- formant une zone de collecteur et presentant une zone de base (11) et une zone d'emetteur (12) de conductivite n+ diffusees dans sa surface superieure et une couche de passivation (13). La couche de passivation (13) recouvre les parties de la surface superieure de la plaquette (10) qui ne servent pas de fenetre de contact. Dans le materiau de collecteur de conductivite n- est diffusee une zone annulaire de conductivite n+ qui entoure complete ment la zone de base (11). La couche de passivation s'etend sur cette zone annulaire (16). Soit la metallisation d'emetteur (14), soit la metallisation de la base (15) est prolongee au-dessus de la couche de passivation jusque dans la region de la zone annulaire (16).
EP82900350A 1981-05-06 1982-02-05 Structure plane de transistor Withdrawn EP0077778A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3117804 1981-05-06
DE19813117804 DE3117804A1 (de) 1981-05-06 1981-05-06 "planare transistorstruktur"

Publications (1)

Publication Number Publication Date
EP0077778A1 true EP0077778A1 (fr) 1983-05-04

Family

ID=6131535

Family Applications (1)

Application Number Title Priority Date Filing Date
EP82900350A Withdrawn EP0077778A1 (fr) 1981-05-06 1982-02-05 Structure plane de transistor

Country Status (4)

Country Link
EP (1) EP0077778A1 (fr)
JP (1) JPS58500679A (fr)
DE (1) DE3117804A1 (fr)
WO (1) WO1982003949A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3276091D1 (en) * 1981-12-24 1987-05-21 Nippon Denso Co Semiconductor device including overvoltage protection diode
DE3201545A1 (de) * 1982-01-20 1983-07-28 Robert Bosch Gmbh, 7000 Stuttgart Planare halbleiteranordnung
JPS61114574A (ja) * 1984-11-09 1986-06-02 Hitachi Ltd 半導体装置
EP0309784A1 (fr) * 1987-09-30 1989-04-05 Siemens Aktiengesellschaft Structure de bandes de contact pour transistors bipolaires
EP0360036B1 (fr) * 1988-09-20 1994-06-01 Siemens Aktiengesellschaft Jonction pn plane à tenue en tension élévée

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1249812A (en) * 1969-05-29 1971-10-13 Ferranti Ltd Improvements relating to semiconductor devices
GB1348697A (en) * 1970-07-31 1974-03-20 Fairchild Camera Instr Co Semiconductors
JPS5139400B2 (fr) * 1971-10-01 1976-10-27
JPS50137478A (fr) * 1974-04-18 1975-10-31
JPS573225B2 (fr) * 1974-08-19 1982-01-20
JPS5412793A (en) * 1977-06-29 1979-01-30 Mitsubishi Electric Corp Concentration measuring method of solutions
JPS5556656A (en) * 1978-10-23 1980-04-25 Nec Corp Semiconductor device
JPS5674961A (en) * 1979-11-22 1981-06-20 Hitachi Ltd Smiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8203949A1 *

Also Published As

Publication number Publication date
JPS58500679A (ja) 1983-04-28
DE3117804A1 (de) 1982-11-25
WO1982003949A1 (fr) 1982-11-11

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 19821207

AK Designated contracting states

Designated state(s): AT BE CH DE FR GB LI NL SE

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19850529

RIN1 Information on inventor provided before grant (corrected)

Inventor name: HARTMUT, MICHEL