EP0122984B1 - Zeitmessschaltung - Google Patents

Zeitmessschaltung Download PDF

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Publication number
EP0122984B1
EP0122984B1 EP83302263A EP83302263A EP0122984B1 EP 0122984 B1 EP0122984 B1 EP 0122984B1 EP 83302263 A EP83302263 A EP 83302263A EP 83302263 A EP83302263 A EP 83302263A EP 0122984 B1 EP0122984 B1 EP 0122984B1
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EP
European Patent Office
Prior art keywords
clock pulse
gate signal
signal
output
measuring circuit
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Expired
Application number
EP83302263A
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English (en)
French (fr)
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EP0122984A1 (de
Inventor
Tadao Hiramatsu
Sunao Katayama
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Hagiwara Electric Holdings Co Ltd
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Hagiwara Electric Co Ltd
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Publication date
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Priority to EP83302263A priority Critical patent/EP0122984B1/de
Priority to DE8383302263T priority patent/DE3377748D1/de
Publication of EP0122984A1 publication Critical patent/EP0122984A1/de
Application granted granted Critical
Publication of EP0122984B1 publication Critical patent/EP0122984B1/de
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means

Definitions

  • the present invention relates to a time measuring circuit for meters of the pulse reflection type such as an ultrasonic axial force meter, an ultrasonic thickness meter or the like.
  • a time measuring circuit for use in meters of the pulse reflection type for measuring a parameter of an object, the circuit including: a pulse oscillator means for producing a clock pulse at a predetermined frequency; means for producing a transmission pulse signal for transmission to the object to be measured; receiving means for receiving an echo pulse signal reflected from said object; a gate signal generator responsive to the transmission and echo pulse signals for producing a gate signal the duration of which is dependent on the time interval to be measured between transmission of the transmission pulse signal and receipt of the echo pulse signal; means responsive to the gate signal and to the clock pulse for providing a periodic waveform; means for detecting the value of the periodic waveform on termination of the gate signal; and means for providing an output related to the duration of the gate signal from a combination of a counted value of pulses and a quantity derived from said detected value the time measuring circuit.
  • the first means comprises a complementary-output element responsive to the clock pulse from said oscillator means for producing said first and second clock pulse trains;
  • the third means is in the form of a counter connected to the flip-flop to count the pulses of the first clock pulse train
  • the second means is in the form of a pair of integration circuits connected to the flip-flop to selectively integrate the first and second clock pulses in response to the gate pulse signal
  • Fig. 1 illustrates a time measuring circuit adapted to an ultrasonic axial force meter of the pulse reflection type.
  • the time measuring circuit includes a crystal oscillator 1 for producing clock pulses A in the form of rectangular waves at a frequency of 100 KHz-10 MHz, and a JK flip-flop 2 connected at its clock terminal CK to the output terminal of oscillator 1 and at its other input terminals J and K to a DC voltage source Vcc.
  • the time measuring circuit further includes an RS flip-flop 3 which is applied at its set terminal S with a transmission pulse signal TTP from the ultrasonic axial force meter and at its reset terminal R with a reflection echo pulse RTP from the axial force meter.
  • RS flip-flop 3 is connected at its output terminal Q to a clear input terminal CLR of flip-flop 2, each first input terminal of NAND gates 4 and 5, and the input terminal of a timer 8.
  • the output terminal Q of RS flip-flop 3 is further connected to each set terminal S of first and second integration circuits 11 and 12 respectively through inverters 9 and 10.
  • NAND gates 4 and 5 are connected at their second input terminals to output terminals Q and Q of JK flip-flop 2 and at their output terminals to reset and set terminals R and S of a second flip-flop 6 respectively.
  • a first output terminal Q of RS flip-flop 6 is connected to the input terminal of a counter 7, a microcomputer 14 and a reset terminal R of the second integration circuit 12, while a second output terminal Q of RS flip-flop 6 is connected to a reset terminal R of the first integration circuit 11.
  • Each output terminal of integration circuits 11 and 12 is connected to an analog-to-digital (or A-D) converter 13 which is in turn connected to microcomputer 14.
  • the microcomputer 14 is commercially available, the interface of which is connected at its input terminals to respective output terminals of counter 7, timer 8 and A-D converter 13.
  • the ultrasonic axial force meter includes a frequency divider 21 in the form of a counter for dividing the frequency of the clock pulses A from oscillator 1, and a pulse width adjuster 22 in the form of a one-shot circuit or a differentiation circuit for forming rectangular impulse waves from the divided clock pulses.
  • the rectangular impulse waves are transmitted to a trigger circuit 23 and also transmitted as the transmission pulse signal TTP to RS flip-flop 3.
  • the ultrasonic axial force meter further includes a probe 30 connected to trigger circuit 23 for producing an ultrasonic pulse wave, which is transmitted to an object to be measured, a receiving amplifier 31 for receiving an echo pulse train output from probe 30, and a comparator 32 for comparing an output of the amplifier 31 with a predetermined value to produce the reflection echo pulse RTP.
  • the ultrasonic axial force meter includes a reset circuit 24 connected to a reset terminal R of counter 7 and responsive to the divided clock pulses from frequency divider 21 for producing a reset signal in accordance with the clock pulses from oscillator 1, a ten-key board 41 for applying an input signal indicative of a constant of the object such as a bolt to the computer 14, a select- key board 42 for selecting input data for the computer 14, an indicator 43 for indicating a value measured by the computer 14, and a thermometer 44 for measuring a temperature of the object and the ambient temperature.
  • RS flip- flop 3 is set in response to the transmission pulse signal TTP to produce a gate signal D at a high level and is reset in response to the reflection echo pulse RTP to make the gate signal low level.
  • the duration of gate signal D is proportional, for instance, to an axial length of the bolt to be measured.
  • the gate signal D causes JK flip-flip 2 to divide clock pulses A from oscillator 1 to produce at its terminals Q and Q output signals B, C in the form of rectangular waves which are relatively inverted at half the frequency of the clock pulses.
  • the level of gate signal D becomes low, the output signal B from terminal Q is maintained at a high level, while the output signal C from terminal Q is maintained at a low level.
  • NAND gates 4 and 5 are responsive to the gate signal D to permit the output signals B and C to be applied to the second RS flip-flop 6 from JK flip-flop 2.
  • the timer 8 produces a high level signal therefrom after lapse of a time t
  • the computer 14 is responsive to the high level signal from timer 8 to receive output signals from counter 7 and A-D converter 13, as is described in detail later.
  • the output signals B and C from JK flip-flop 2 are relatively inverted to form the output signals E and F from NAND gates 4 and 5 during appearance of the gate signal D.
  • the output signals E and F are maintained at a high level respectively.
  • the second RS flip-flop 6 is applied at its terminals R and S with relatively inverted output signals E and F during appearance of the gate signal D, it produces relatively inverted output signals G and H at its terminals Q and Q. Upon disappearance of the gate signal D, the second RS flip-flop 6 acts to store each level of the output signals E and F.
  • the output signal G from RS flip-flop 6 is applied as an input signal with a high level to the counter 7, as is illustrated in (a) of Figure 3. If the level of gate signal D becomes low when the output signals B and C from JK flip-flop 2 are at high and low levels respectively, the output signal G from RS flip-flop 6 is applied as an input signal with a low level to the counter 7, as is illustrated in (b) of Figure 3. As a result, the counter 7 acts to count the number of the output pulses G from RS flip-flop 6 thereby to measure a timely. Furthermore, the computer 14 discriminates the operation of integration circuit 11 or 12 in relation to the level of the output signal G from RS flip-flop 6 to produce an output signal therefrom for activation of A-D converter 13.
  • the first integration circuit 11 When applied with the output signal H at a low level from RS flip-flop 6, the first integration circuit 11 operates to produce an output signal I in the form of saw tooth waves.
  • A-D converter 13 is responsive to the output signal from computer 14 to convert the final voltage level of output signal I into a digital value indicative of a time T 2 .
  • the time T 2 is measured by a digital value converted from the final saw tooth wave of signal I. This means that resolution or resolving power in measurement of the time T 2 can easily be enhanced up to e.g. 1 nS, in dependence on the capacity of the A-D converter 13 related to the frequency of the clock pulses.
  • the second integration circuit 12 When applied with the output signal G with the low level from RS flip-flop 6, as is illustrated in (b) of Figure 3, the second integration circuit 12 operates to produce an output signal J in the form of saw tooth waves.
  • A-D converter 13 is responsive to the output signal from computer 14 to convert the final voltage level of output signal J into a digital value indicative of a time T 3 . This means that resolution or resolving power in measurement of the time T 3 can be easily enhanced up to, e.g., 1 nS, in dependence on the capacity of the A-D converter 13 related to the frequency of the clock pulses.
  • integration circuits 11 and 12 startto integrate the low levels of input signals H and G applied to their reset terminals R respectively during appearance of the gate signal D and discharge when the levels of the input signals H and G become high.
  • the integration circuits 11 and 12 act to hold therein the finally integrated voltages respectively, and subsequently A-D converter 13 is activated in response to the output signal from computer 14 in relation to the level of the output signal G to convert the integrated voltage into the digital value and produces an output signal indicative of the digital value upon completion of the voltage conversion.
  • the computer 14 receives an output signal from counter 7 to measure a sum of the time T, and the time T 2 or T 2 and T 3 , and the counter 7 is reset by a reset signal from reset circuit 24.
  • the microcomputer 14 In the case that the microcomputer 14 is applied with the input signal G with high level upon disappearance of the gate signal D, it measures the time T on the basis of the following equation:
  • the microcomputer 14 In the case that the microcomputer 14 is applied with the input signal G with low level upon disappearance of the gate signal D, it measures the time T on a basis of the following equation-: where the value of T 2 is determined in its full scale.
  • FIG 4 there is illustrated a modification of the time measuring circuit described above, in which JK flip-flop 2 in Figure 1 is replaced with a complementary-output element 200, and the integration circuits 11 and 12 are replaced with a voltage generator 90, a selector 100 and a single integration circuit 110.
  • the complementary-output element 200 is arranged to produce relatively inverted clock pulses A and A at the same phase in response to input clock pulses from oscillator 1.
  • the voltage generator 90 is arranged to produce positive and negative voltage signals +V s , -V s which have the same voltage levels and different polarities
  • the selector 100 is, for example, in the form of an analogue switch which is connected to voltage generator 90 to produce a positive voltage signal +Vg in response to the low level signal H from RS flip-flop 6 and to produce a negative voltage signal -V s in response to the low level signal G from RS flip-flop 6, and the integration circuit 110 is arranged to charge in response to the positive voltage signal +V s and discharge in response to the negative voltage signal -V s thereby to produce an output signalla in the form of triangular waves as is illustrated in Fig. 5.
  • the other arrangements are substantially the same as those in the time measuring circuit of Fig. 1.
  • A-D converter 13 of the above embodiment may be replaced with a voltage-frequency converter with a counter.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)

Claims (7)

1. Zeitmeßschaltung zur Verwendung in Meßgeräten der Impulsreflexart zur Messung eines Parameters eines Objekts, wobei die Schaltung aufweist: eine Impulsoszillatoreinrichtung (1) zur Erzeugung eines Taktpulses (A) mit einer vorbestimmten Frequenz, eine Einrichtung (21, 22, 23) zum Erzeugen eines Sendeimpulssignals (TTP) zur übertragung an das zu messende Objekt, eine Empfangseinrichtung (31) zum Empfang eines von dem Objekt reflektierten Echoimpulssignals (RTP, einen Torsignalgenerator (3), der auf das Sendeimpulssignal und das Echoimpulssignal anspricht, um ein Torsignal (D) zu erzeugen, dessen Dauervon dem zu messenden Zeitintervall zwischen der Übertragung des Sendeimpulssignals und dem Empfang des Echoimpulssignals abhängt, eine Einrichtung (2,4,5,6,11,12), die auf das Torsignal (D) und den Taktpuls (A) anspricht, um eine periodische Wellenform zu liefern, eine Einrichtung (13) zur Erfassung des Werts der periodischen Wellenform nach dem Ende des Torsignals, und eine Einrichtung (14) zur Lieferung eines Ausgangssignals, das zur Dauer des Torsignals im Verhältnis steht, und zwar aus einer Kombination eines Zählwerts von Impulsen und einer von dem erfaßten Wert abgeleiteten Menge, dadurch gekennzeichnet, daß
die Einrichtung (2, 4, 5, 6, 11, 12), die auf das Torsignal anspricht, um eine periodische Wellenform zu liefern, eine erste Einrichtung (2, 4, 5, 6) aufweist, die auf den Taktpuls (A) von der Oszillatoreinrichtung und das Torsignal (D) von dem Generator anspricht, um bei Anwesenheit des Torsignals, einen ersten und einen zweiten Taktimpulszug (G H) mit gleicher Phase und relativ zueinander invertiert zu erzeugen, und eine zweite Einrichtung (11, 12 oder 90, 100, 110) aufweist, die so angeschlossen ist, daß sie den ersten und den zweiten Taktimpulszug empfängt und auf das Torsignal anspricht, um aus dem ersten und dem zweiten Taktimpulszug die eine oder mehr als eine periodische Wellenform (I, J, la) zu erzeugen, die dieselbe Periode wie der erste und der zweite Taktimpulszug aufweist, wobei der erfaßte Wert der periodischen Wellenform oder Wellenformen von der Dauer des Torsignals abhängt,
die Zeitmeßschaltung eine dritte Einrichtung (7) aufweist zum Zählen der Impulse des ersten Taktimpulszugs (G) von der ersten Einrichtung und zum Erzeugen eines Ausgangssignals, das diesem Zählwert der Impulse entspricht,
die Einrichtung (14) zur Lieferung eines Ausgangssignals so angeschlossen ist, daß sie zusätzlich zu dem Zählwert und dem erfaßten Wert den ersten oder den zweiten Taktimpulszug empfängt, wobei das Ausgangssignal zusätzlich vom Zustand des ersten oder des zweiten Taktimpulszugs abgeleitet wird.
2. Zeitmeßschaltung nach Anspruch 1, bei der die erste Einrichtung umfaßt:
ein Element (2 oder 200) mit komplementären Ausgängen, das auf den Taktpuls (A) der Oszillatoreinrichtung anspricht, um den ersten und den zweiten Taktimpulszug zu erzeugen,
eine Toreinrichtung (4, 5), die auf das Torsignal (D) von dem Torsignalgenerator anspricht, um den ersten und den zweiten Taktimpulszug in Anwesenheit des Torsignals auszugeben, und
eine Flipflop (6) zum Anlegen des ersten Taktimpulszugs (G) an die dritte Einrichtung und zum Anlegen des ersten und des zweiten Taktimpulszugs (G, H) an die zweite Einrichtung.
3. Zeitmeßschaltung nach Anspruch 1 oder 2, bei der die Einrichtung (13) zur Erfassung des Werts der periodischen Wellenform(en) nach dem Ende des Torsignals einen Analog-Digital-Umsetzer (13) umfaßt, der an die zweite Einrichtung angeschlossen ist, um den erfaßten Wert in einen Digitalwert umzusetzen.
4. Zeitmeßschaltung nach Anspruch 1, oder 3, bei der die zweite Einrichtung eine erste und eine zweite Integrierschaltung (11, 12) aufweist, die mit der ersten Einrichtung und dem Torsignalgenerator (3) verbunden sind, um Impulse des ersten bzw. des zweiten Taktimpulszugs (G, H) zu integrieren und eine ersten une eine zweite periodische Wellenform in der Form jeweiliger erster und zweiter integrierter Signale zu liefern, wobei der erfaßte Wert des ersten oder des zweiten integrierten Signals von der Dauer des Torsignals abhängt.
5. Zeitmeßschaltung nach Anspruch 1, oder 3, bei der die zweite Einrichtung umfaßt: einen Spannungsgenerator (90) zum Erzeugen positiver und negativer Spannungssignale (+Vs' -VS) gleicher Spannung, eine Wähleinrichtung (100), die mit dem Spannungsgenerator verbunden ist, um ein positives Spannungssignal als Antwort auf Impulse von einem (H) von dem ersten und dem zweiten Impulszug (G, H) zu erzeugen und eine negative Spannung als Antwort auf Impulse des anderen (G) von dem ersten und dem zweiten Impulszug (G, H) zu erzeugen, und eine Integrierschaltung (110), die mit der Wähleinrichtung und dem Torsignalgenerator verbunden ist, um als Antwort auf das positive Spannungssignal von der Wähleinrichtung aufzuladen und als Antwort auf das negative Spannungssignals von der Wähleinrichtung zu entladen, um so die periodische Wellenform zu liefern.
6. Zeitmeßschaltung nach Anspruch 2 oder Anspruch 3, 4 oder 5 in Verbindung mit Anspruch 2, bei der das Element mit komplementären Ausgängen ein JK Flipflop (2) umfaßt, das auf den Taktpuls (A) von der Oszillatoreinrichtung anspricht, um den ersten und den zweiten Taktimpulszug (G, H) zu erzeugen, und bei dem die Toreinrichtung ein erstes und ein zweites NAND-Glied (4, 5) aufweist, die den ersten und den zweiten Taktimpulszug und das Torsignal empfangen.
7. Zeitmeßschaltung nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die Einrichtung zu Lieferung eines Ausgangssignals an einen Mikrocomputer (14) umfaßt.
EP83302263A 1983-04-21 1983-04-21 Zeitmessschaltung Expired EP0122984B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP83302263A EP0122984B1 (de) 1983-04-21 1983-04-21 Zeitmessschaltung
DE8383302263T DE3377748D1 (en) 1983-04-21 1983-04-21 Time measuring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP83302263A EP0122984B1 (de) 1983-04-21 1983-04-21 Zeitmessschaltung

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EP0122984A1 EP0122984A1 (de) 1984-10-31
EP0122984B1 true EP0122984B1 (de) 1988-08-17

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0820473B2 (ja) * 1987-02-04 1996-03-04 株式会社 アドバンテスト 連続的周期−電圧変換装置
DE4222643A1 (de) * 1992-07-10 1994-01-13 Bodenseewerk Geraetetech Einrichtung zur Messung von Pulslaufzeiten
JP6299516B2 (ja) * 2014-08-05 2018-03-28 株式会社デンソー 時間計測回路

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52123670A (en) * 1976-04-09 1977-10-18 Takeda Riken Ind Co Ltd Digital frequency measuring device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 4, no. 5, October 1961, New York (US), J. DIAZ: "Radar pulse measuring", p. 27 *
IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, vol. IM-21, no. 4, November 1972, R.A. BENSON et al.: "The folded ramp: A new technique for computer-controlled time-interval measurement", p. 409-412 *

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Publication number Publication date
EP0122984A1 (de) 1984-10-31
DE3377748D1 (en) 1988-09-22

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