EP0149097A2 - Procédé et dispositif pour l'évaluation sûre d'une alarme d'une ligne de signalisation d'un dispositif de signalisation de danger - Google Patents

Procédé et dispositif pour l'évaluation sûre d'une alarme d'une ligne de signalisation d'un dispositif de signalisation de danger Download PDF

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Publication number
EP0149097A2
EP0149097A2 EP84114714A EP84114714A EP0149097A2 EP 0149097 A2 EP0149097 A2 EP 0149097A2 EP 84114714 A EP84114714 A EP 84114714A EP 84114714 A EP84114714 A EP 84114714A EP 0149097 A2 EP0149097 A2 EP 0149097A2
Authority
EP
European Patent Office
Prior art keywords
signal
flip
input
swsi
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP84114714A
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German (de)
English (en)
Other versions
EP0149097A3 (fr
Inventor
Joachim Böhm
Hans Michael Dipl.-Ing. Sojka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0149097A2 publication Critical patent/EP0149097A2/fr
Publication of EP0149097A3 publication Critical patent/EP0149097A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING SYSTEMS, e.g. PERSONAL CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/18—Prevention or correction of operating errors
    • G08B29/185—Signal analysis techniques for reducing or preventing false alarms or for enhancing the reliability of the system
    • G—PHYSICS
    • G08—SIGNALLING
    • G08B—SIGNALLING SYSTEMS, e.g. PERSONAL CALLING SYSTEMS; ORDER TELEGRAPHS; ALARM SYSTEMS
    • G08B29/00—Checking or monitoring of signalling or alarm systems; Prevention or correction of operating errors, e.g. preventing unauthorised operation
    • G08B29/18—Prevention or correction of operating errors
    • G08B29/20—Calibration, including self-calibrating arrangements
    • G08B29/24—Self-calibration, e.g. compensating for environmental drift or ageing of components

Definitions

  • the invention relates to a method for fail-safe alarm evaluation according to the preamble of claim 1 and to an arrangement for performing this method.
  • delay elements with RC constants or differentiators were provided in the system.
  • time delay elements were arranged which only give an alarm signal after a certain time has passed when a predetermined alarm threshold is exceeded.
  • shortly occurring interference pulses which are caused for example by smoke bursts, lead to an integration of the alarm signal in such fire detectors.
  • false alarm triggering may be delayed.
  • a window discriminator supplied, which generates an threshold signal at the output of the window discriminator as long as an event occurs, as long as the input signal lies outside the window of the window discriminator, ie exceeds an upper or lower threshold value.
  • the window discriminator is followed by a digital disturbance suppression device according to the invention, which periodically checks for a predeterminable time when the threshold signal occurs, that is to say when an event occurs on the detection line, whether the threshold signal is still present. If the threshold signal is still present after this predetermined time has elapsed, the signal is passed on to a message evaluation device which then triggers an alarm or fault message. However, if the threshold signal disappears during the test process because the event on the detection line has disappeared, the test process is stopped immediately. The test process starts again when a threshold signal appears again at the output of the threshold circuit.
  • Another advantage is that operating voltage fluctuations in the method according to the invention cannot have any influence on the disturbance-suppression device, because an integration element with capacitors is not necessary, through which undesired compensating currents flow when the operating voltage changes and could therefore cause false alarms.
  • a clock generator for control can expediently be provided for the periodic test process, the clock frequency of which can be changed automatically in accordance with these disturbance variables in the case of periodically occurring disturbance variables.
  • a plurality of disturbance variable masking devices can be provided, namely one for each detection line, all disturbance variable masking devices being controlled by a common clock generator.
  • the disturbance variable masking device is formed by two storage elements which are either connected in parallel or in series.
  • the memory elements are supplied with a clock signal from the clock generator and with the threshold signal from the window discriminator. Further details of the arrangement of the invention will become apparent from the subordinate rüchen p arrangement drive.
  • Fig. 1 the arrangement of the invention is shown schematically in a control center Z of a hazard alarm system Disturbance suppression device SAE shown. Only one zone ML is shown, although in general several zones are routed to the central office. For example, the following arrangement, which is shown in the block diagram, can be provided for each detection line.
  • the detection line ML leads to a window discriminator FD via a signal limit SB known per se, which protects the subsequent switching devices from overvoltages.
  • the window discriminator FD is, for example, a threshold circuit with an upper and a lower threshold.
  • the quiescent current-monitored DC signaling line (primary line) ML has a quiescent value of 6 volts
  • the upper threshold can be 6.1 volts and the lower threshold 5.9 volts. Fluctuations in idle value within the idle window thus formed do not lead to a signaling status (MZ). If an event on the detection line ML changes the idle state (RZ) because the upper or lower threshold value has been exceeded, the window discriminator FD outputs a threshold signal SWSI at its output A to the disturbance variable deflection device SAE, which is arranged downstream of the window discriminator FD.
  • the digital disturbance suppression device SAE checks periodically, e.g. clock-controlled, a predetermined time, whether the threshold signal SWSI is still present. After the specified time has elapsed, an output signal ASI is sent to a message evaluation device MAE if the threshold signal is still present: With the disappearance of the threshold signal, i.e. When the event disappears on the detection line, the test process is stopped immediately. A new test procedure begins with the occurrence of a new event or with the threshold signal.
  • the message evaluation device MAE which is not shown here and is not the subject of the invention, evaluates the signal now present as a real alarm signal and initiates a corresponding alarm, e.g. optically or acoustically, or gives an alarm message to a downstream device, e.g. to the police or to a security service, or suppresses an alarm message because the area from which the alarm message comes is not armed.
  • a corresponding alarm e.g. optically or acoustically
  • Two series-connected delay flip-flops DFF1 and DFF2 are supplied with the clock signal TS by a clock generator TG at the respective clock input TE of the D flip-flops DFF1 and DFF2.
  • the threshold signal SWSI leads from the output of the window discriminator to the D input of the first flip-flop DFFI and to the respective set input S of the two D flip-flops DFF1 and DFF2.
  • the output Q of the first D flip-flop DFF1 leads to the D input of the second D flip-flop DFF2.
  • the output signal ASI leads from the output Q of the second D flip-flop DFF2 to the message evaluation device MEA.
  • FIG. 3 shows a pulse diagram corresponding to FIG. 2.
  • the threshold signal SWSI is shown, which is either in the idle state RZ or in the signaling state MZ.
  • the output signal ASI which represents an actual idle state RZ 'or a real signaling state MZ' in accordance with the disturbance-suppression device.
  • the positive clock edge of the clock signal TS is present at the time t1.
  • the second positive clock edge of the clock signal is present at time t2.
  • the threshold signal SWSI changes from the idle state RZ to the signaling state MZ.
  • This signal is now at the D input of the first D flip-flop DFF1 and at the same time at the respective set input S of the two D flip-flops.
  • the threshold signal SWSI is still present, so that the first D flip-flop DFF1 is triggered with the rising edge of the clock signal TS (positive edge control) and the input signal, ie the threshold signal SWSI, is output Q from the first D flip-flop DFF1 pending.
  • This threshold signal SWSI is thus present at the D input of the second D flip-flop DFF2, so that the second D flip-flop DFF2 is prepared for the acceptance of the signal present at the D input.
  • the pending signal is accepted, so that the threshold signal SWSI is present as output signal ASI at the output Q of the second D flip-flop DFF2, unless the threshold signal has disappeared in the meantime. Therefore, the threshold signal SWSI must also be present at the set input S of the respective D flip-flop.
  • the flip-flops are reset immediately, so that the output signal ASI also disappears immediately.
  • the output signal ASI as a real detector state MZ 'thus only reaches the message evaluation device MAE if the threshold signal SWSI is present continuously for at least one cycle length T.
  • the threshold signal SWSI disappears, so that the output signal ASI disappears again (RZ ').
  • Further occurring threshold signals SWSI i.e. briefly occurring events (interference pulses) on the detection line, which mean a detection state, are only taking effect as a real signaling state MZ 'at time t9 after the threshold signal SWSI has occurred at time t7.
  • the threshold signal SWSI is applied to the D input of the second D flip-flop DFF2.
  • the threshold signal is given to the Q output of the second D flip-flop with the positive clock pulse at time t9.
  • the output signal ASI also disappears.
  • FIG. 4 shows another embodiment of the disturbance variable masking device. It is formed by two D-flip-flops 0FFl and DFF2 connected in parallel, which are supplied with the clock signal TS by a clock generator TG in such a way that the first D-flip-flop DFF1 is driven at its clock input TE with the positive clock edge and with the negative clock edge, the second D flip-flop DFF2 is driven at its clock input TE.
  • a negation element G2 is connected upstream of the clock input TE of the second D flip-flop DFF2.
  • the threshold signal SWSI is fed to both D inputs and simultaneously to both set inputs S of the respective D flip-flops DFF1 and DFF2.
  • the respective output Q of the two flip-flops leads to a NOR gate Gl, whose output signal ASI leads to the message evaluation device MAE, not shown here.
  • 5 shows the pulse diagram corresponding to FIG. 4.
  • the clock frequency of the clock signal TS is chosen to be half as large and shown as in FIG. 3 in order to have similar relationships as shown in FIG. 3.
  • 5 shows the threshold signal SWSI with the different idle and signaling states RZ and MZ under the clock signal TS. Below this, the output signal ASI is shown, which shows the actual idle state RZ 'and the real message state MZ'.
  • FIGS. 2 and 3 it was said that a threshold signal is present when an event occurs on the detection line. Since it is common practice to work with negative logic, it is the case that with the occurrence of an event on the detection line an otherwise normally occurring threshold signal disappears and the corresponding processes in the circuit accordingly take place, so that the output signal actually disappears when a real message status (MZ ') is pending. An output signal ASI is present when an actual idle state RZ 'is present. In the exemplary embodiment according to FIG. 4 and the corresponding FIG. 5, the facts are to be explained accordingly. With the occurrence of an event on the detection line, the input signal of the interference suppressor device disappears, i.e.
  • the threshold signal SWSI changes from the idle state RZ ("H” state) to the signaling state MZ ("L” state). Since this signal is very short-term and signals that appear later only have an effect for a short time, the actual idle state RZ '(output signal ASI) changes until time t4.
  • the threshold signal SWSI is changed from its idle state RZ to the signaling state MZ. This means that the message status MZ, i.e. the threshold signal SWSI is logic "L” at the respective D input of the D flip-flop.
  • the "L signal” is given to the output Q of the second D flip-flop DFF2 and thus to the second input of the OR gate Gl with the negative clock edge of the clock signal TS.
  • the "L-Wet" of the threshold signal SWSI is given to the output Q of the first D flip-flop DFF1 and thus to the first input of the OR gate Gl. This is how it works Output signal ASI of the OR gate Gl from “H” to the "L” state, so that a real message state MZ 'is given to the message evaluation device MAE at time t4. If the event on the detection line disappears at time t5, the threshold signal SWSI again becomes "H" (idle state RZ).
  • the two flip-flops DFF1 and DFF2 are set to "H" (output Q), so that the output signal ASI is "H” at the output of the OR gate Gl, ie an actual idle state RZ 'is given to the message evaluation device MAE.
  • threshold signal SWSI indicates a signaling state MZ ("L" state) at the time t6, however, this does not come into play because this signaling state already returns to the idle state RZ ("H" at the next possible positive clock edge (at the time t7). -State) has passed.
  • the signaling state MZ of the threshold signal SWSI that has been pending since the time t8 causes the signaling state MZ to be transferred to the output Q of the second flip-flop DFF2 (“L” state) at the time t9.
  • the "L" signal (signaling state MZ) is given to the output Q of the first flip-flop DFF1 at time t10, so that the output signal ASI of the OR gate Gl also has the "L” state and thus has a real reporting status MZ '.
  • the disturbance variable masking device has two D flip-flops DFF1 and DFF2 connected in series, which are acted upon by a clock signal TS from a clock generator TG at the respective clock input TE.
  • the input signal ie the threshold signal SWSI, is fed to the D input of the first flip-flop DFF1 and, in contrast to the exemplary embodiment according to FIG. 2, to an AND gate G3 and to a NOR gate G4.
  • the output of the AND gate G3 leads to the set input S of the two D flip-flops DFF1 and DFF2 and the output of the NOR gate G4 leads to the resept input R of both D flip-flops DFF1 and DFF2.
  • the output Q of the first flip-flop DFF1 is connected to the D input of the second flip-flop DFF2.
  • the output signal ASI is present at the output Q of the second flip-flop DFF2, which leads on the one hand to the message evaluation device MAE and on the other hand to the respective second input of the AND gate G3 and the NOR gate G4.
  • the pulse diagram is shown in FIG. 7 corresponding to FIG. 6.
  • the threshold signal SWSI is shown with two message states MZ1 and MZ2, the first message state MZ1 corresponding to the "H” state and the second message state MZ2 corresponding to the "L” state.
  • the output signal ASI of the second flip-flop DFF2 indicates the real message states MZ ', namely the message state MZ'l with the "H” - and the message state MZ'2 with the "L” level. Short-term changes in the status of the signal, which are smaller than the time period T of the clock frequency, have no effect on the output signal ASI.
  • a change in the signaling state of the threshold signal SWSI from "L" - (MZ2) to the "H” - (MZI) state occurs at time t1 until time t4.
  • the output signal ASI goes in from the second reporting state MZ'2 at time t3 the first reporting status MZ'l.
  • the "H" level at the Q output of the second flip-flop DFF2 and the "H" level of the threshold signal SWSI causes an "H” level at the respective set input S of the two flip-flops DFF1 and D F F2.
  • the output signal ASI is only changed at the time t7, because the short-term changes in the state of the threshold signal SWSI after the time t4 still have no influence on the output signal ASI. Only after the second signaling state M Z2 of the threshold signal SWSI has been present continuously for two positive clock edges immediately following one another after the time t5, namely at the time t6 and at the time t7, is the output signal ASI from the signaling state MZ'l to the signaling state MZ'2 changed.
  • FIG. 8 shows an arrangement in the block diagram in which a plurality of disturbance variable masking devices SAE'1 to SAE'n are controlled in the central station using a common clock generator TG (TG). Otherwise, the arrangement is similar to FIG. 2.
  • One signal line ML1, ML2, ... leads to a signal limitation SB1, SB2, .... This in turn leads to the window discriminator FD1, FD2, ..., its output leads with the threshold signal to the interference suppression device SAI.
  • the output signal ASI leads to Meldungsauskra worn MAE1, MAE2, ....
  • the clock frequency to be changed at periodically occurring disturbance variables corresponding to these disturbances, so that such disorders are easier to eliminate.
  • An arrangement for recognizing the periodically occurring disturbance variables is not specifically shown here.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Alarm Systems (AREA)
EP84114714A 1983-12-22 1984-12-04 Procédé et dispositif pour l'évaluation sûre d'une alarme d'une ligne de signalisation d'un dispositif de signalisation de danger Withdrawn EP0149097A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19833346527 DE3346527A1 (de) 1983-12-22 1983-12-22 Verfahren und anordnung zur stoerungssicheren alarmauswertung einer meldelinie einer gefahrenmeldeanlage
DE3346527 1983-12-22

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Publication Number Publication Date
EP0149097A2 true EP0149097A2 (fr) 1985-07-24
EP0149097A3 EP0149097A3 (fr) 1985-09-04

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EP84114714A Withdrawn EP0149097A3 (fr) 1983-12-22 1984-12-04 Procédé et dispositif pour l'évaluation sûre d'une alarme d'une ligne de signalisation d'un dispositif de signalisation de danger

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DE (1) DE3346527A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2589609A1 (fr) * 1985-10-31 1987-05-07 Frere Emmanuel Dispositif d'arlarme, notamment pour la surveillance de locaux
EP0493741A3 (en) * 1990-12-21 1992-10-28 Critikon Gmbh Gravity infusion control device

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AT398859B (de) * 1990-05-11 1995-02-27 Siemens Ag Oesterreich Schaltung für die überwachung und betätigung eines meldeorgans
DE19960422C1 (de) * 1999-12-15 2001-01-25 Job Lizenz Gmbh & Co Kg Verfahren und Vorrichtung zur Bestimmung von als Stromsenken wirkenden gestörten Meldern in einer Gefahrenmeldeanlage

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599195A (en) * 1968-05-31 1971-08-10 Pinkerton S Inc Dual alarm, coaxial line resonator, intrusion detection system
JPS5231699A (en) * 1975-07-25 1977-03-10 Hochiki Corp Fire senser
JPS52153759A (en) * 1976-06-17 1977-12-21 Hochiki Co Storage type detector
DE2722338C3 (de) * 1977-05-17 1980-12-18 Preussag Ag Feuerschutz, 2060 Bad Oldesloe Brandmeldeeinrichtung

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2589609A1 (fr) * 1985-10-31 1987-05-07 Frere Emmanuel Dispositif d'arlarme, notamment pour la surveillance de locaux
EP0493741A3 (en) * 1990-12-21 1992-10-28 Critikon Gmbh Gravity infusion control device

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EP0149097A3 (fr) 1985-09-04
DE3346527A1 (de) 1985-07-04

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