EP0151585A4 - Halbleiteranordnung mit untiefem übergang. - Google Patents
Halbleiteranordnung mit untiefem übergang.Info
- Publication number
- EP0151585A4 EP0151585A4 EP19840902405 EP84902405A EP0151585A4 EP 0151585 A4 EP0151585 A4 EP 0151585A4 EP 19840902405 EP19840902405 EP 19840902405 EP 84902405 A EP84902405 A EP 84902405A EP 0151585 A4 EP0151585 A4 EP 0151585A4
- Authority
- EP
- European Patent Office
- Prior art keywords
- semiconductor arrangement
- deep transition
- deep
- transition
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
- H10P32/1406—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
Definitions
- This invention relates to shallow-junction semiconductor devices.
- MOSFET metal-oxide-semiconductor field-effect transistor
- a neutral species is initially implanted into a surface region of a semiconductor body.
- the neutral species is implanted to form a layer whose maximum concentration occurs at a depth greater than that of a p-n junction to be subsequently formed.
- the junction is subsequently established at a depth that is greater than the depth of the peak concentration of the neutral-species layer.
- a dopant species is then implanted into the surface region at a depth less than the depth of the maximum-concentration of the previously implanted neutral species. Annealing to activate the dopant species is then carried out.
- the neutral-species layer serves to getter point defects in the body of the device. Additionally, this layer serves as a physical barrier to diffusion of dopant species. As a result, the diffusivity of the dopant species in the body is significantly lowered relative to the case in which no neutral-species layer is provided. In any event, the result is that a p-n junction is formed in the body of the device at an extremely shallow depth.
- FIGS. 1 through 4 are schematic representations of a portion of a MOSFET device at successive stages of a fabrication sequence that embodies the principles of the present invention. Detailed Description
- shallow p-n junctions can be formed in a variety of semiconductor devices. These devices include, for example, p-n diodes, bipolar transistors and MOSFET devices. By way of example, the invention is described in connection with the provision of shallow p-n junctions in a MOSFET device.
- FIG. 1 A portion of such a MOSFET device at an intermediate stage of its fabrication cycle is shown in FIG. 1, such portion comprising a known gate-and-source-and -drain (GASAD) structure.
- the structure comprises a silicon body 10 having field-oxide (silicon dioxide) portions 12, 14 thereon.
- the structure further includes a gate-oxide (silicon dioxide) layer 16, a doped polysilicon layer 18, and a metallic suicide (e.g. tantalum disilicide) layer 20. Also, the structure includes additional silicon dioxide layers 22,24. Openings 25, 26 are defined by the oxide layers 12, 22 and 14, 24. Source and drain regions are later formed in the body 10 in approximate alignment with these openings.
- a so-called neutral species is implanted into regions of body 10 defined by the openings 25, 26.
- Known ion implantation techniques can be used.
- neutral species means ion species that do not produce active carriers in the semiconductor body and that are effective to limit the diffusivity of active species in the body.
- neutral species include carbon, oxygen, argon or any other inert gas.
- Group IV elements such as silicon, germanium and tin, and nitrogen (minor activity) .
- the peak or maximum concentration of the approximately Gaussian-shaped distribution of the neutral-species implant in the body 10 is schematically depicted by lines 30, 32 formed with x's.
- the dosage of the neutral-species implant represented in FIG. 2 is selected to provide approximately one or two monolayers of the neutral species at the peak-concentration depth.
- the energy of the incident ions is selected such that the peak concentration of the implanted neutral species occurs approximately 2000 A below the surface of the body 10.
- the peak concentration of the neutral-species implant is selected to occur at a depth greater than that of the p-n junction(s) to be subsequently formed in the body 10.
- the depth of the subsequently formed p-n junction(s) is, for example, approximately one-tenth to three-quarters that of the depth of the peak concentration of the neutral species. (In other devices, described below, the depth of the p-n junction(s) is greater than the depth of the peak concentration of the neutral-species implant.)
- dosages and energies can be used.
- One set of dosage and energy values for the aforelisted neutral species is as follows: carbon, 5 x 10 15 ions per square centimeter (i/cm 2 ), 80 kilo-electron-volts (keV); oxygen, 5 x 10 15 i/cm9 46 , 80 keV; silicon, 5 x
- the respective peak-concentration depth of each of the neutral species is approximately 2000 A below the surface of the body 10 shown in FIG. 2.
- the device structure represented in FIG. 2 is next subjected to an annealing step.
- active species such as arsenic
- the annealing is done, for example, at a temperature in the range 700-to-900 degrees Celsius in an inert ambient for about one-half hour. During annealing, no substantial vertical or lateral movement of the implanted neutral species occurs. Nor does any substantial movement occur later during the so-called activation annealing step described below.
- an active species is introduced into the structure by any of various known means, e.g., by ion implantation, as indicated by the arrows 34 in FIG. 3.
- the implanted active species comprises, for example, a pentavalent n-type impurity such as arsenic, phosphorus or antimony, or a trivalent p-type impurity such as boron or gallium.
- the depth of the peak or maximum concentration of the approximately Gaussian-shaped distribution of the active-species implant in the body 10 is schematically represented in FIG. 3 by " lines 36, 38 formed with dots.
- the peak concentration of the implanted active species is selected to occur relatively close to the top surface of the body 10, e.g., at a depth of approximately 200-to-1000 A.
- an arsenic implant having a peak- concentration depth 36, 38 of approximately 200 A is achieved by implanting 4 x 10 i/c ⁇ r at 30 keV.
- a carbon or nitrogen implant having a peak-concentration depth 30 , 32 ( FIG . 3 ) of about 2000 A a boron implant
- OMPI ⁇ ⁇ ⁇ Wl? ⁇ having a peak-concentration depth 36, 38 of approximately 1000 A is achieved by implanting 4 x 10 1 5 i/cm 2 at 30 keV.
- Extremely shallow p-n junctions are thereby formed.
- activation annealing is carried out at, for example, about 1000 degrees Celsius for approximately three hours in a standard mildly dry oxidizing atmosphere.
- the resulting p-n junction is at a depth of approximately 1400 A.
- the p-n junction is at a depth of about 3700 A.
- activation annealing is carried out at, for example, about 900 degrees Celsius for approximately five hours in a standard mildly dry oxidizing atmosphere.
- the p-n junction occurs at approximately 3300 A. without the presence of the neutral-species implant, but with all other processing conditions approximately the same, the p-n junction occurs at a depth of about 6700 A.
- the p-n junction is at a depth less than the depth of the peak concentration of an implanted neutral species layer.
- the p-n junction is at a depth greater than the depth of the peak concentration of the implanted neutral-species layer.
- the active impurity species can be initially introduced into the device structure at a shallower depth than specified above for boron and/or by activation annealing the structure at a lower temperature than specified above.
- the peak concentration of the neutral- species layer can be initially formed sufficiently deep that, after annealing, the junction is established at a depth less than the depth of the peak concentration of the neutral-species layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51675583A | 1983-07-25 | 1983-07-25 | |
| US516755 | 1983-07-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0151585A1 EP0151585A1 (de) | 1985-08-21 |
| EP0151585A4 true EP0151585A4 (de) | 1986-02-20 |
Family
ID=24056961
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP19840902405 Withdrawn EP0151585A4 (de) | 1983-07-25 | 1984-06-04 | Halbleiteranordnung mit untiefem übergang. |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0151585A4 (de) |
| JP (1) | JPS60501927A (de) |
| CA (1) | CA1222835A (de) |
| WO (1) | WO1985000694A1 (de) |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2578096A1 (fr) * | 1985-02-28 | 1986-08-29 | Bull Sa | Procede de fabrication d'un transistor mos et dispositif a circuits integres en resultant |
| NL8501992A (nl) * | 1985-07-11 | 1987-02-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
| US4683637A (en) * | 1986-02-07 | 1987-08-04 | Motorola, Inc. | Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing |
| US4786608A (en) * | 1986-12-30 | 1988-11-22 | Harris Corp. | Technique for forming electric field shielding layer in oxygen-implanted silicon substrate |
| US5654209A (en) * | 1988-07-12 | 1997-08-05 | Seiko Epson Corporation | Method of making N-type semiconductor region by implantation |
| EP0350845A3 (de) * | 1988-07-12 | 1991-05-29 | Seiko Epson Corporation | Halbleiterbauelement mit dotierten Gebieten und Verfahren zu seiner Herstellung |
| JP2773957B2 (ja) * | 1989-09-08 | 1998-07-09 | 富士通株式会社 | 半導体装置の製造方法 |
| JPH05190849A (ja) * | 1992-01-14 | 1993-07-30 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
| EP0717435A1 (de) * | 1994-12-01 | 1996-06-19 | AT&T Corp. | Verfahren zur Kontrolle der Diffusion eines Dotiermaterials in einer Halbleiterschicht und dadurch hergestellte Halbleiterschicht |
| JPH1041243A (ja) * | 1996-04-29 | 1998-02-13 | Texas Instr Inc <Ti> | ドープ領域作製方法 |
| DE69730019T2 (de) * | 1996-05-08 | 2004-12-30 | Advanced Micro Devices, Inc., Sunnyvale | Kontrolle der p-n-übergangstiefe und kanallänge durch erzeugung von die dotierstoffdiffusion hemmenden zwischengitterstellen-gradienten |
| US6051460A (en) * | 1997-11-12 | 2000-04-18 | Advanced Micro Devices, Inc. | Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon |
| US6146934A (en) * | 1997-12-19 | 2000-11-14 | Advanced Micro Devices, Inc. | Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof |
| US6013546A (en) * | 1997-12-19 | 2000-01-11 | Advanced Micro Devices, Inc. | Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof |
| US6087209A (en) * | 1998-07-31 | 2000-07-11 | Advanced Micro Devices, Inc. | Formation of low resistance, ultra shallow LDD junctions employing a sub-surface, non-amorphous implant |
| FR2828331A1 (fr) * | 2001-07-31 | 2003-02-07 | St Microelectronics Sa | Procede de fabrication de transistor bipolaire dans un circuit integre cmos |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2014797A1 (de) * | 1969-03-28 | 1970-10-08 | Hitachi Ltd., Tokio | Halbleiter-Bauelement und Verfahren zu seiner Herstellung |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3796929A (en) * | 1970-12-09 | 1974-03-12 | Philips Nv | Junction isolated integrated circuit resistor with crystal damage near isolation junction |
| JPS553828B2 (de) * | 1972-11-30 | 1980-01-26 | ||
| US4069068A (en) * | 1976-07-02 | 1978-01-17 | International Business Machines Corporation | Semiconductor fabrication method for improved device yield by minimizing pipes between common conductivity type regions |
| JPS53120263A (en) * | 1977-03-29 | 1978-10-20 | Nec Corp | Manufacture of semiconductor device |
| JPS5583263A (en) * | 1978-12-19 | 1980-06-23 | Fujitsu Ltd | Mos semiconductor device |
| JPS55121680A (en) * | 1979-03-13 | 1980-09-18 | Nec Corp | Manufacture of semiconductor device |
| JPS5627924A (en) * | 1979-08-14 | 1981-03-18 | Toshiba Corp | Semiconductor device and its manufacture |
| JPS5632742A (en) * | 1979-08-24 | 1981-04-02 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5693367A (en) * | 1979-12-20 | 1981-07-28 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS577161A (en) * | 1980-06-16 | 1982-01-14 | Toshiba Corp | Mos semiconductor device |
| JPS57106123A (en) * | 1980-12-24 | 1982-07-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5856417A (ja) * | 1981-09-30 | 1983-04-04 | Toshiba Corp | 半導体装置の製造方法 |
-
1984
- 1984-06-04 JP JP59502397A patent/JPS60501927A/ja active Pending
- 1984-06-04 WO PCT/US1984/000851 patent/WO1985000694A1/en not_active Ceased
- 1984-06-04 EP EP19840902405 patent/EP0151585A4/de not_active Withdrawn
- 1984-06-27 CA CA000457570A patent/CA1222835A/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2014797A1 (de) * | 1969-03-28 | 1970-10-08 | Hitachi Ltd., Tokio | Halbleiter-Bauelement und Verfahren zu seiner Herstellung |
Non-Patent Citations (3)
| Title |
|---|
| IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 8, January 1979, pages 3154-3156, New York, US; W.K. CHU et al.: "Method of reducing arsenic thermal diffusion by noble gas ion implantation" * |
| JOURNAL OF THE ELECTROCHEMICAL SOCIETY, vol. 116, no. 1, January 1969, pages 73-77, Princeton, US; T.H. YEH et al.: "Strain compensation in silicon by diffused impurities" * |
| See also references of WO8500694A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60501927A (ja) | 1985-11-07 |
| CA1222835A (en) | 1987-06-09 |
| EP0151585A1 (de) | 1985-08-21 |
| WO1985000694A1 (en) | 1985-02-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Designated state(s): BE DE FR GB NL |
|
| 17P | Request for examination filed |
Effective date: 19850717 |
|
| A4 | Supplementary search report drawn up and despatched |
Effective date: 19860220 |
|
| 17Q | First examination report despatched |
Effective date: 19871027 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 19881221 |
|
| RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: LEVINSTEIN, HYMAN, JOSEPH Inventor name: MURARKA, SHYAM, PRASAD Inventor name: YANEY, DAVID, STANLEY Inventor name: KELLY, MICHAEL, JAMES |