Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
  • H10P74/27—Structural arrangements therefor
  • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
  • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped

Definitions

• This invention relates to a wafer, a wafer scale device, a monolithic wafer and a hybrid monolithic wafer which incorporates commercial or custom fabricated chips into complete systems made thereon, " as well as techniques of the manufacture of wafer scale devices.
• the "chip” is the basis for many of today's advanced computer and electronic devices. However, even as the size of the chip has grown from the original integrated circuit, to a large scale integrated circuit, and to a very large scale integrated circuit, chips have always been manufactured on wafers as an intermediate step in their manufacturing process.
• the wafer when manufactured, is made with many usually identical circuits located in die spread out across the surface of the wafer. Thereafter, these circuits are diced and the individual die become what is referred to as chips.
• the circuits are tested on the wafer, the bad ones marked, and then the "chips" are diced and sorted for the individual good chips which are then packaged in packages such as the familiar dual in line packages- seen in many printed circuit boards today. Often the final high speed tests are only capable of being performed after the chip is in its package.
• FIG 1 is a single drawing illustrating the preferred embodiment of our invention.
• Figure 1 The details of Figure 1 can be understood by those skilled in the art who know that a wafer is usually a very thin cylinder of silicon on which die are deposited. Figure 1 represents a cross section of that silicon wafer
• the metal layers can have connections which are ' formed by amorphous semiconductor material. This is by way of an 5 amorphous via, as described therein. Connections between the metal layers or between the metal layers and the substrate can be made through via holes in the insulation layer between metals or between layers respectively.
• the real estate of the wafer is divided into special areas called cells and signal hookup areas and power hookup areas are provided.
• the cells were intended to host integrated circuit chips in a hybrid system of chips and metal layers with the interconnections providing signal connections between the chips on the surface..
• this application utilizes a different substrate.
• the preferred substrate has been replaced by a silicon wafer 1 with active die incorporated on it, which die are isolated one from the other, and which each have die contact sites 2 normally used for probing during testing and for bonding during packaging.
• a thin adhesive layer of poly mide resin insulation layer 4 To the wafer 1, and on- the upper die carrying surface, has been layered a thin adhesive layer of poly mide resin insulation layer 4.
• This resin during the process of manufacturing the monolithic wafer, is cured and then etched to provide holes through the surface of the wafer to the die contact sites 2 so that these are uncovered temporarily.
• the resin performs the principal task of smoothing the surface of the wafer, which is important to subsequent processing and improves step coverage. Thereafter, .
• a thin film interconnection system 3 of which the prior interconnection system which has been incorporated by reference is a preferred example, is deposited on the insulation layer 4.
• the interconnection system 3 has incorporated therein its own contact sites.
• bond contact sites 5 situated at sites suitable for wire bonding.
• probe contact sites .6 suitable for probing with a test probe 15, and there are coupling contact sites 7 suitable for coupling of the interconnection system to the underlying die at die contact site 2. While in general any contact site may be coupled to any contact site, there is a special direct connection 8 between the probe contact sites 6 and the coupling contact sites 7 for the purpose of making direct test access to the buried contact site of 7 and coupled die contact site 2.
• wafers with isolated die formed thereon are common techniques in the intermediate process of making circuits.
• the * wafer of the preferred embodiment is make like these wafers.
• the interconnection system which as been described, is programmable in the manner taught by the aforementioned prior application so that interconnection can be made for signal purposes throughout any or all of the dies on the wafer, which previously had been isolated.
• the underlying die can be a plurality of 64K or 256K RAM die, and these can be unified into a mass memory.
• These die can be unified into a full system, which can include instruction, processor chips, I/O interfaces, and many other chips which are required to make a full system.
• the die can be replaced if not working or unwanted by a substitute die.
• the additional chips used to make a full system or the substitute die can be placed over the die on the wafer by adhesively bonding the downbond hybrid chips 7 carrying the desired circuits where they are placed on the surface on the interconnection system 3. Then a wire bond 11 is made to selected bonding sites, as from a site on the chip 9 to an upper bond contact site 5.
• an upper bond contact site 5 can be used to bond an external wire bond 12 to a printed circuit board 10.
• Stitch bonds 13 may be made between upper bonding sites 5 of the wafer. All of the interconnections of the system make the wafer into a true monolithic wafer, and when additional or substitute chips are downbonded to the surface of the wafer, we consider this a hybrid monolithic wafer system.

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• 1984
  • 1984-09-12 EP EP19850900508 patent/EP0155965A4/fr not_active Withdrawn
  • 1984-09-12 JP JP60500707A patent/JPS60502234A/ja active Pending
  • 1984-09-12 WO PCT/US1984/001444 patent/WO1985001390A1/fr not_active Ceased

Patent Citations (3)

Non-Patent Citations (2)

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