EP0164735A2 - Microprocesseur avec circuit de rafraîchissement pour mémoire dynamique - Google Patents

Microprocesseur avec circuit de rafraîchissement pour mémoire dynamique Download PDF

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Publication number
EP0164735A2
EP0164735A2 EP85107211A EP85107211A EP0164735A2 EP 0164735 A2 EP0164735 A2 EP 0164735A2 EP 85107211 A EP85107211 A EP 85107211A EP 85107211 A EP85107211 A EP 85107211A EP 0164735 A2 EP0164735 A2 EP 0164735A2
Authority
EP
European Patent Office
Prior art keywords
refresh
signal
request signal
microprocessor
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85107211A
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German (de)
English (en)
Other versions
EP0164735A3 (fr
Inventor
Takahiro Tokuume
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59119593A external-priority patent/JPS60263395A/ja
Priority claimed from JP59241002A external-priority patent/JPS61120396A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0164735A2 publication Critical patent/EP0164735A2/fr
Publication of EP0164735A3 publication Critical patent/EP0164735A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Definitions

  • the present invention relates to a microprocessor having a dynamic memory refresh circuit, and particularly to a microprocessor capable of accessing an external dynamic.memory in which a refresh operation of stored information is required.
  • a refresh operation is controlled by a refresh controller generating sequential refresh - addresses and is performed by means of sense amplifiers coupled to bit lines in a dynamic memory.
  • the refresh operation information stored in all memory cells coupled to a word line activated by one refresh address are simultaneously refreshed. Since all information stored in the dynamic memory must be refreshed, a plurality of refresh addresses for activating all word lines are to be generated by the refresh controller.
  • a refresh cycle is predetermined in accordance with a dynamic memory to be used. In a 64 K dynamic memory, for example, 128 refresh addresses are required to active all of the 128 word lines for the refresh operation within normally 2 m sec..
  • refresh addresses have to be applied to these dynamic memories from external terminals at the predetermined time intervals.
  • a - dynamic memory including a counter for generating sequential refresh addresses is provided.
  • a timing signal for controlling a count operation according to a predetermined time interval must be applied to the counter from external of the memory.
  • a data processing system employing a dynamic memory is provided with a refresh controller to generate fefresh addresses and/or a refresh timing signal.
  • the refresh controller is in general provided separately from or independently of a microprocessor having a central processing unit (CPU).
  • CPU central processing unit
  • the refresh controller must request the CPU to allow a memory access. This request is conventionally done by'means of an interruption.
  • the CPU sends an access grant signal to the refresh controller when the CPU is in no operation. If the CPU is performing an operation, the access grant signal is not sent to the refresh controller till that operation is finished.
  • the refresh controller starts the refresh operation by using a signal bus to which the dynamic memory, the refresh controller and the CPU are coupled.
  • the CPU can not access both the dynamic memory and the bus during the refresh operation. Namely, an operation of the CPU is stopped in the period of the refresh operation. Particularly, even if the operation to be performed by the CPU does not require the dynamic memory access but requires an access to a peripheral equipment, CPU, ROM, or the like which is commonly coupled to the bus, the CPU can not access them because the bus is busy in the refresh operation. Further the CPU has to stop its operation periodically with a time interval to carry out the memory refresh operation. Thus, in the case the operating frequency of the microprocessor is, for instance, 4 MHz, the processing capability of the microprocessor which is stopped by the refresh operation will decrease by about 10% in.comparison with that of the microprocessor which does not participate in the refresh operation.
  • the microprocessor of this type has such shortcomings that a refresh operation can not be performed when the CPU is in a wait condition because in this period the CPU execution cycle is indefinite.
  • the signal bus to which the ROM and the dynamic memory are coupled is employed not only by the CPU but also by the instruction prefetch circuit. In general access to the ROM and the dynamic memory, that is, employed of the bus is independently and asynchronously performed. Therefore, the above-mentioned refresh control circuit can not be adapted to the microprocessor including the instruction prefetch circuit.
  • An object of the present invention is to provide a microprocessor having a refresh control circuit capable of carrying out a dynamic memory refresh operation without reducing the processing capability.
  • Another object of the present invention is to provide a novel microprocessor which can perform both an instruction prefetch operation and a memory refresh operation.
  • Still another object of the present invention is to provide a microprocessor in which a memory refresh operation is hindered by a CPU operation and/or an instruction prefetch operation.
  • Still another object of the present invention is to provide a novel microprocessor in which a CPU, an instruction prefetch circuit and a memory refresh control circuit are integrated on a single semiconductor chip.
  • Still another object of the present invention is to provide a microprocess in which a CPU operation and/or an instruction prefetch operation is not hindered by a memory refresh operation.
  • a microprocessor of the present invention includes a central processing unit (CPU), an instruction prefetch circuit, a bus interface circuit coupling the microprocessor to an external bus through which information transmission is performed between the microprocessor and another microprocessor a peripheral unit, a dynamic memory, or the like, a memory refresh control circuit and a bus arbiter.
  • the instruction prefetch circuit reads instructions to be executed by the CPU out of an instruction memory (ROM) and preliminarily stores a plurality of the read-out instructions in a prefetch register provided therein.
  • the prefetch register may be constructed by a queue memory.
  • the CPU fetches one instruction stored in the prefetch register in an instruction fetch cycle and executes a data processing according to the instruction.
  • the CPU When a data transmission is required in the data processing, the CPU generates a bus access request signal (hereinafter called a first bus access request signal) which is sent to the bus arbiter.
  • the instruction prefetch circuit generates a bus access request signal (hereinafter called a second bus access request signal) when the prefetch register has an empty area storing-no instruction.
  • the bus arbiter receives the first bus access request signal or the second bus access request signal, it controls the bus interface circuit such that the CPU or the instruction prefetch circuit is coupled to the external bus.
  • the bus arbiter selects the one having a high priority and grants the external bus usage.
  • the refresh control circuit sends'a refresh request signal to the bus arbiter at predetermined time intervals.
  • the bus arbiter grants to use the external bus for the refresh operation when the first and the second bus access request signals are absent but inhibits the refresh request when at least one of these two bus access request signals is present.
  • the refresh control circuit performs a refresh operation by use of the -external bus only when the refresh request is granted by the bus arbiter.
  • a bus access is controlled by the bus arbiter, so that the refresh operation can be performed without exerting a harmful influence upon the CPU operation and the instruction prefetch operation.
  • the refresh control circuit may send a refresh address for activating a word line of a dynamic memory and a refresh control signal indicating a refresh timing to the dynamic memory.
  • the dynamic memory includes a timer or a counter for generating refresh addresses o R in the case a refresh address generating circuit is independently provided, the refresh control circuit may generate only the refresh control signal when the refresh request is granted.
  • the bus arbiter latches the received bus access request signal until the refresh operation is finished.
  • This latch operation in the bus arbiter may be avoided by providing a status signal generating circuit in the CPU and/or the instruction prefetch circuit.
  • the status signal generating circuit generates a status signal which indicates that the CPU or the instruction prefetch circuit does not access the external bus during the period of time equal to or longer than the period of a refresh cycle in which a refresh operation of memory cells coupled to at least one word line can be enough performed.
  • This status signal can be obtained by, for example, an instruction decoding. Namely, when the CPU executes an instruction which includes no external bus access, the external bus is in an idle state. If the refresh operation is performed during the period when the CPU executes that instruction, the first bus access request. from the CPU will never occur.
  • CPU may send the status signal to the bus arbiter.
  • the bus arbiter grants the refresh request in the case the refresh request signal is applied thereto from the refresh control circuit only when the status signal is present.
  • the instruction prefetch circuit also can produce the status signal when the prefetch register is storing instructions more tnan a predetermined number.
  • the bus arbiter grants the refresh request only when these two status signals are both present, if both of the CPU and the instruction prefetch circuit include the status signal generating circuits. This function is very useful in the case that the microprocessor executes a program wherein the external bus access instructions are few.
  • the first bus access request signal and/or the second bus access request signal is generated many times.
  • a specific circuit may be added to the refresh control circuit.
  • the specific circuit generates a specific refresh request signal when a predetermined number of the refresh requests are rejected by the bus arbiter or the refresh requests are not granted during in a predetermined period of time.
  • the specific refresh request signal is applied to the bus arbiter.
  • the bus arbiter Upon receipt of the specific refresh request signal the bus arbiter stops a bus usage of the CPU or the instruction prefetch circuit immediately or after the operation of the CPU or the prefetch circuit is finished. Thus, the refresh operation can be smoothly performed without destroying the information stored in the dynamic memory.
  • Fig. 1 shows the construction of a conventional microprocessor system including a microprocessor 1, a refresh controller 2, a dynamic memory 3, a memory access signal 4, a memory refresh signal 5, a memory refresh request signal 6, a memory refresh grant signal 7.
  • the following procedure is employed to execute the refresh operation:
  • a microprocessor 10 embodying the present invention comprises an execution unit (CPU) 11, a bus interface control unit 12, and a refresh control circuit 19, which are integrated on a single semiconductor chip 10.
  • the bus interface control unit 12 includes a timing control circuit 13, an instruction prefetch circuit 14, a bus interface circuit 15, and a bus arbiter 22, which receives a first bus access request signal 16 from the CPU 11, a second bus access request signal 17 from the prefetch circuit 14, and a refresh request signal 20 from the refresh control circuit 19 and sends a refresh grant signal 21 to the refresh control circuit 19.
  • the bus interface circuit generates an access signal 18 to an outside dynamic memory (not shown) or input/output unit (not shown) provided outside the microprocessor 10.
  • the access signal 18 includes a data, an address and a control information and is transferred through an external bus 100 to a peripheral unit, another microprocessor, a program memory, a dynamic memory (DRAM), and the like (not shown), which are coupled in common to the external bus 100.
  • a refresh control signal 23 is generated by the refresh control circuit 19 and transferred to the outside dynamic memory through the bus 100. Instead the refresh control signal 23 may be transferred to the bus 100 via the bus interface circuit 15 or may be transferred to the memory by using another bus (not shown) separate from the bus 100.
  • the instruction prefetch circuit 14 is used to read an instruction from the external program memory (ROM) and stores the read-out instruction in a queue register therein.
  • the queue register can store, several instructions at a time. In case there is still a space for storage, it will produce the second bus access request signal 17 to start the access to the ROM for storing an instruction to be executed by the CPU 11.
  • the CPU 11 executes the instruction which has been stored in the prefetch circuit 14. As the instruction is processed, it will produce the first bus access request signal 16 if access to the outside dynamic memory, input/output unit or the like is required.
  • the timing control circuit 13 On receiving the bus access request signal 16 or 17 from the CPU 11 or the instruction prefetch circuit 14, the timing control circuit 13 operates to control the bus interface circuit 15 to couple the CPU or the circuit .14 to the external bus 100.
  • the memory refresh operation will subsequently be described.
  • the bus arbiter 22 is used to detect that the access to the external bus has not been gained to implement the memory refresh operation.
  • Fig. 3 shows the refresh control circuit 19 comprising a refresh timer 24 receiving a clock pulse 25, a refresh interval set register 26, a refresh counter 27 generating refresh address 28, and a refresh timing control circuit 29 generating the refresh request signal 20, receiving the refresh grant signal 21 and generating the refresh control command 23.
  • the refresh timer 24 receiving the clock pulse 25 as an input clock generates a timing signal 32 and sends it to the refresh timing control circuit 29 at constant time intervals.
  • the time interval of the refresh timer 24 is given by the refresh interval set register 26.
  • the refresh counter 27 produces the refresh address 28 and increments the contents thereof to "1" or "2" each time it executes the refresh operation in response to a control signal 33.
  • the refresh timing control circuit 29 When the refresh timing control circuit 29 receives the timing signal 32 from the refresh timer 24, it produces the refresh request signal 20. On receiving the refresh grant signal 23, it produces the refresh control command 23 to designate a refresh timing to a dynamic memory to be refreshed. The circuit 29 further produces the control signal 33 for incrementing the counter 27.
  • Figs. 4 and 5 show the bus arbiter 22 receiving the first bus access request signal 16, the second bus access request signal 17, a first status signal 16', a second status signal 17', the refresh request signal 20 and a bus access termination signal 31 and generating the refresh grant signal 21, a bus access start signal 30.
  • the first bus access request signal 16 and the second bus access request signal 17 are sent out respectively whenever the bus access must be executed in the CPU 11 and the instruction prefetch circuit 14. These signals are effective when the bus access termination signal 31 is applied from the timing control circuit, or when the external bus 100 is in an idle status.
  • the bus arbiter 22 will hold the refresh request signal 20 and send the bus access start signal 30 to the timing control circuit to effect the bus access operation of the CPU and the prefetch circuit.
  • the bus arbiter 22 will accept the refresh request signal 20 and send the refresh grant signal 21 to the refresh control circuit 19 to implement the refresh operation.
  • the bus arbiter 22 may be constructed by a random logic circuit, a decoding circuit (e.g. programmable logic array (PLA)), or the like, which determines an output status according to the combination of the inputted signals... ,
  • PLA programmable logic array
  • the refresh operation can be performed without.exerting harmful influence on the C P U operation and the prefetch operation. Further, the refresh operation can be performed even if the CPU 11 is in a waiting condition or a hold condition. Furthermore, the instruction prefetch circuit 14 can be integrated in the semiconductor chip 10 with the CPU 11. The C PU 11 can also execute an instruction read out of the prefetch circuit 14 without taking account of the refresh operation.
  • the bus arbiter 22 While the refresh operation is being executed, the bus arbiter 22 has to hold the bus access request signals from the CPU 11 and the prefetch circuit 14. Namely, a latch circuit is required in the bus arbiter 22.
  • Fig. 5 shows another embodiment of the bus arbiter in which the latch circuit can be omitted from the bus arbiter.
  • the difference from the bus arbiter of Fig. 4 lies in the conditions under which the refresh operation is permitted. This point only wi-l be described.
  • a first status signal 16' and a second status signal 17' are respectively applied to the bus arbiter .22. They become effective when the CPU and the prefetch circuit do not generate the bus access signals during a period . from the present over several clocks (time enough to execute the refresh operation).-
  • the bus arbiter 22 will accept the refresh request in case both the first bus -access request signal 16 and the second bus access request signal 17 are absent and both the status signals 16' and 17' are present.
  • the first status signal 16' can be produced by decoding an instruction which is sent to the CPU. That is, if the instruction to be executed needs to access the external bus, the first status signal 16' is not generated, while the first status signal 16' is generated when the CPU 11 executes an instruction which requires external bus access.
  • This first status signal 16' can be produced by implementing a first detecting circuit 40 as shown in Fig. 2 detecting the instruction which indludes no external bus access.
  • the second status signal 17' is produced by a second detecting circuit 41 which is to be provided in the prefetch circuit 14 as shown in Fig. 2.
  • the second detecting circuit 41 detects that the prefetch circuit 14 is storing full instructions or that the circuit 14-is storing instructions more than a predetermined number and generates the. second status signal 17'.
  • the microprocessor of the present invention can smoothly perform the refresh operation.
  • the refresh operation can be performed in parallel with the CPU operation with no bus access.
  • a microprocessor 10' comprises a C PU 11, a timing control circuit 13, an instruction prefetch circuit 14, a bus interface circuit 15 generating an access signal 18 to an outside dynamic memory, outside input/output unit or the like coupled to an external bus 100, a refresh control circuit 19' generating a refresh request signal 20, a specific refresh request signal 50 and a refresh control signal 23, and a bus arbiter 22' receiving a first bus access request signal 16 and a second bus access request signal 17.
  • Fig. 6 there are two kinds of the refresh request signals; namely, the normal refresh request signal 20 and the specific refresh request signal 50 produced from the refresh control circuit 19'.
  • the refresh operation according to the normal request signal 20 will be explained first:
  • the refresh operation is executed by detecting that the microprocessor is not operating to gain access to the external bus 100, it is possible to provide the memory refresh operation by minimizing reduction in the processing capability of the microprocessor.
  • the memory refresh operation is allowed by using the specific refresh request signal 50.
  • the memory refresh operation by means of the specific refresh request signal 50 is as follows:
  • the refresh operation by means of the specific refresh request signal 50 is carried out by interrupting into the CPU operation and the prefetch operation.
  • the priority order on the bus access will be the specific refresh request signal 50 (highest), the bus access request signals .16 and 17 (second highest), and the normal refresh request signal 20 (lowest).
  • the refresh control circuit 19' and the bus arbiter 22' will be described in detail.
  • Fig. 7 shows the refresh control circuit 19' comprising a refresh timer 70, receiving a clock signal 75, a refresh interval set register 71, a refresh counter 74 generating a refresh address 28, a refresh timing control circuit 73 receiving the refresh grant signal 21 and generating the refresh control signal 23, and a refresh request control circuit 72 generating the normal refresh request signal 20 and the specific refresh request signal 50.
  • the refresh timer 70 is a timer counting the clock signal 75 and senda'a refresh timing signal 76 to the refresh request control circuit 72 at constant time intervals (the time is determined by the value set at the refresh interval set register 71).
  • the refresh request control circuit 72 contains an up/ down counter, which is counted up by the refresh timing signal 76 from the refresh timer 70 and counted down in response to a signal 77 generated each time the refresh operation is executed.
  • the refresh request signals are produced from the refresh request control circuit 72. That is, the normal refresh request signal 20 is produced when the content of the counter indicates "1", whereas the specific refresh request signal 50 is produced when the contents of the counter in the refresh request control circuit 72 indicates "8".
  • the refresh counter 74 stores a refresh address and the content thereof is incremented each time the refresh operation is executed once.
  • the refresh timing control circuit 73 is used to control the execution of the refresh operation and, on receiving the refresh operation grant signal 21, execute the refresh operation as many times as required depending on the conditions of the refresh request signal. In other words, when the normal refresh request signal 20 only is effective, it executes the refresh operation once and when the specific refresh request signal 50 is effective, the required number of times (for instance 8 times).
  • the refresh operation timing control circuit 73 instructs the refresh counter 74 to output the refresh address 28 during the refresh operation and also applies the refresh control signal 23 to the external memory.
  • the refresh timing control circuit 73 increments the content of the refresh counter 74 and decrements the counter of the refresh request control circuit 72 at the end of one refresh operation.
  • Fig. 8 shows the bus arbiter 22 1 having a detection circuit 80 which receives the first bus access request signal 16, the second bus access request signal 17, the normal refresh request signal 20, the specific refresh request signal 50 and generates the acknowledgement signal 51 to the CPU, the acknowledgement signal 52 to the prefetch circuit and the refresh grant signal 21.
  • the detection circuit 80 further generates the bus access start signal 30 and receives the bus access termination signal 31.
  • bus arbiter The following four kinds of bus access request signals are applied to the bus arbiter:
  • the refresh operation is performed in response to the normal refresh request signal 20 when frequency in the external bus access of the CPU 11 and the instruction prefetch circuit 14 is low. While if the program with high frequency in the external bus access is performed by the microprocessor, the refresh operation can be performed with certainty by the specific refresh request signal 50..Therefore, the microprocessor can perform the program processing without reducing the processing capability thereof and can also perform the refresh operation independent on the program processing.
  • the present invention can be adapted to a microprocessor having no instruction prefetch circuit. In this case the second bus access request signal is not required.
  • the microprocessor can be also adapted to a dynamic memory having a refresh address generator. In this case the refresh control circuit does not need the refresh address counter and may generate a refresh timing control signal only, according to the control of the bus arbiter.
  • the present invention is useful in a microprocessor in which operations of a CPU and an instruction prefetch circuit are performed asynchronously with each other.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
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EP85107211A 1984-06-11 1985-06-11 Microprocesseur avec circuit de rafraíchissement pour mémoire dynamique Withdrawn EP0164735A3 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP59119593A JPS60263395A (ja) 1984-06-11 1984-06-11 マイクロ・プロセツサ
JP119593/84 1984-06-11
JP241002/84 1984-11-15
JP59241002A JPS61120396A (ja) 1984-11-15 1984-11-15 マイクロ・プロセッサ

Publications (2)

Publication Number Publication Date
EP0164735A2 true EP0164735A2 (fr) 1985-12-18
EP0164735A3 EP0164735A3 (fr) 1988-11-09

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EP85107211A Withdrawn EP0164735A3 (fr) 1984-06-11 1985-06-11 Microprocesseur avec circuit de rafraíchissement pour mémoire dynamique

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EP (1) EP0164735A3 (fr)

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EP0338528A3 (fr) * 1988-04-19 1991-11-13 Kabushiki Kaisha Toshiba Mémoire à semi-conducteurs
EP0352768B1 (fr) * 1988-07-26 1994-09-14 Kabushiki Kaisha Toshiba Mémoire à semi-conducteurs

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EP0338528A3 (fr) * 1988-04-19 1991-11-13 Kabushiki Kaisha Toshiba Mémoire à semi-conducteurs
EP0352768B1 (fr) * 1988-07-26 1994-09-14 Kabushiki Kaisha Toshiba Mémoire à semi-conducteurs

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US4924381A (en) 1990-05-08
US4965722A (en) 1990-10-23
EP0164735A3 (fr) 1988-11-09

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