EP0165108A1 - Ultraschneller zeitnumerischer Umformer - Google Patents

Ultraschneller zeitnumerischer Umformer Download PDF

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Publication number
EP0165108A1
EP0165108A1 EP85400870A EP85400870A EP0165108A1 EP 0165108 A1 EP0165108 A1 EP 0165108A1 EP 85400870 A EP85400870 A EP 85400870A EP 85400870 A EP85400870 A EP 85400870A EP 0165108 A1 EP0165108 A1 EP 0165108A1
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EP
European Patent Office
Prior art keywords
chain
doors
door
signal
stop signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85400870A
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English (en)
French (fr)
Other versions
EP0165108B1 (de
Inventor
Jean-François Genat
François Rossel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Original Assignee
Centre National de la Recherche Scientifique CNRS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Centre National de la Recherche Scientifique CNRS filed Critical Centre National de la Recherche Scientifique CNRS
Priority to AT85400870T priority Critical patent/ATE41713T1/de
Publication of EP0165108A1 publication Critical patent/EP0165108A1/de
Application granted granted Critical
Publication of EP0165108B1 publication Critical patent/EP0165108B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/005—Time-to-digital converters [TDC]

Definitions

  • the present invention relates to a time-to-digital converter, that is to say a device intended to supply a digital value representing the time elapsed between the reception of a start signal and the reception of a stop signal.
  • the field of application of the invention is notably, but not exclusively, that of very short time measurement in high-energy physical nuclear electronics, nuclear physics, or nuclear medicine.
  • the converter according to the invention is particularly suitable for measuring the collection time intervals at the ends of particle detectors.
  • time-to-digital converters are essentially of two types.
  • the former use a capacitor which is charged at constant current for the duration to be measured, the charge level then being digitized; these converters are generally precise, but of a complex structure.
  • the second are based on the use of reference clocks; they are also of complex structure and their precision is linked to that of the clock.
  • the present invention aims to provide a time-to-digital converter having a simple structure allowing it to be produced in the form of an integrated circuit.
  • the present invention also aims to provide an ultra-fast time-digital converter, that is to say having a very short response time.
  • the present invention is based on the use, as a time reference, of the propagation times of logic signals in an integrated circuit.
  • the new integrated circuit technologies in the present case the manufacture of networks of prediffused doors, ensure, within the same sample, dispersions of the order of a few percent on sets of logical doors. several thousand units.
  • the measurement is carried out by inhibiting, following reception of the stop signal, the propagation of the start signal in a chain of doors.
  • This inhibition can be achieved in several ways.
  • the locking circuit comprises a second chain of doors which is formed on the same integrated circuit substrate and at one end of which the stop signal is received, the two chains forming paths parallel with connections between the doors of the first chain and the doors of the second chain so that the state of the doors of at least one of the two chains is locked when the starting signal propagating along the first chain and the stop signal propagating along the second chain met.
  • the configuration of the doors of the first chain, as well as possibly that of the doors of the second chain is representative of the time to be measured.
  • the converter is provided with coding means having inputs connected to the doors of at least one of the chains to provide a digital measurement value depending on the state of these doors.
  • the directions of propagation of the start signal and the stop signal along the two parallel chains can be opposite to each other or identical. In the latter case, the propagation time through the doors of the first chain is greater than the propagation time through the doors of the second chain so that the stop signal can "catch up" with the start signal.
  • the locking circuit comprises a set of paths each formed between a common input receiving the stop signal and a respective gate of the chain of propagation of the start signal.
  • the stop signal is applied almost simultaneously to the different doors so that the state of the chain is frozen upon receipt of the stop signal.
  • Means for reading the state of the gates of the propagation chain of the starting signal are provided to provide a digital value representative of the time to be measured.
  • the converter according to the invention makes it possible to give the result of the measurement of very short times in an ultra-fast manner.
  • An additional advantage is that the converter can be implemented as an integrated circuit.
  • the converter of FIG. 1 comprises two chains of doors 10 and 15 similar, formed parallel to one another but with opposite directions of propagation.
  • the door chains are formed from a network of pre-diffused doors on the same integrated circuit substrate.
  • Each door 11 of the chain 1a has a first input connected to a non-inverting output of the previous door 11 and a second input connected to the inverting output of an associated door 16 of the chain 15.
  • the latter has a first input connected to the non-inverting output of the previous door 16 and a second input connected to the inverting output of the associated door 11.
  • Each door 11 is thus associated with a door 16, and vice versa.
  • the term "gate" is used here to designate a logic circuit through which an incoming signal may or may not be propagated depending on the state of a control signal which may also be received by this circuit.
  • a start signal sd is applied to the input end 12 of the door chain 10 in the form, for example, of a transition from low logic level to high logic level at an instant t1.
  • a stop signal is applied to the input end 17 of the door chain 15 also in the form of a transition from low logic level to high logic level at an instant t2.
  • the inputs 12 and 17 are located at opposite ends of the chains 10 and 15, the signals sd and sa propagating in opposite directions. Each time the signal sd crosses a door 11, the corresponding door 16 is blocked. Likewise, each time the signal sa passes through a door 16, the corresponding door 11 is blocked.
  • the coding circuit can be arranged to directly deliver a binary digital word giving on N bits a value proportional to ⁇ t.
  • the least significant bit of the word supplied by the converter is 2 t pd .
  • the dispersion ⁇ t pd of the propagation times per integrated circuit gate must satisfy:
  • the maximum number N of significant bits that the converter can supply is such that:
  • T being the value of the full scale of the converter.
  • the value of the least significant bit is here equal to 2 td. A reduction in this value in order to improve the precision or the fineness of the measurement requires a reduction in the propagation time per gate.
  • FIG. 2 illustrates another embodiment of a converter according to the invention with which the least significant bit has a value which can be less than the propagation time per gate.
  • the start signal sd is applied to the input end 22 of a first chain 20 of doors 21 similar to the chain 10 of the converter of FIG. 1.
  • the stop signal sa is applied to the end of input 27 of a second chain 25 of transmission doors 26.
  • Each door 26 is arranged to systematically transmit the signal which is present on its signal input, the latter being connected to its control input.
  • Each input of a door 26 is connected to an input of a door 23 whose inverting output is connected to an input of an associated door 21.
  • the other input of this door 21 is connected to the non-inverting output of the previous door 21 while the other input of the door 23 is connected to the inverting output of the associated door 21.
  • a door 26 is associated with each pair of doors 21 - 23.
  • the starting signal sd is applied to the input 22 at time t1 and propagates along the chain 20. It will be noted that the crossing of each door 21 by the signal sd is accompanied by. blocking of the associated door 23.
  • the stop signal sa is applied to the input 27 at time t2 and propagates along the chain 25. The propagation along this chain is faster than that along the chain 20 so that the signal sa can catch up with the starting signal. As soon as the signal meets door 23 not blocked, it passes through it in order to be able to block the corresponding door 21, thus blocking the propagation of the starting signal.
  • the signal sa continues to be propagated along the chain 25, successively blocking the doors of the chain 20 not crossed by the start signal.
  • the coding circuit 29 can be arranged to supply the number m in the form of a binary digital word.
  • the least significant bit of the word supplied by the converter is t1 pd - t2 pd ; it can therefore take a value less than t1 pd and t2p d .
  • condition (1) Regarding the dispersions ot1 pd and ⁇ t2 pd on the propagation times, we find condition (1) with: also finds the relation (2) giving the number of bits N.
  • the pre-broadcast networks currently available have propagation times per gate less than a nanosecond and dispersions of less than a few tens of picoseconds.
  • the converter of FIG. 2 allows under these conditions a coding on 5 bits with a low weight equal to 500 ps and a full scale of 16 ns.
  • this is a common advantage to all of the embodiments of the invention, the result is available very quickly.
  • FIG. 2 also shows means for adjusting the converter.
  • each chain 20, 25 is connected a series of transmission doors, respectively 20a, 25a.
  • the starting signal is applied to an input terminal 22a which is connected to the input of a switching circuit 24, the outputs of which are connected to respective inputs of the doors 21a of the suite 20a.
  • the stop signal is applied to an input terminal 27a which is connected to the input of a switching circuit 28, the outputs of which are connected to respective inputs of the doors 26a of the sequence 25a.
  • Each switching circuit has a control input for selecting one of the outputs.
  • the zero adjustment is carried out by positioning the routing circuits so that the response of the converter is equal to zero when the signals sd and sa are applied simultaneously to the terminals 22a and 27a.
  • a decoding circuit 20b is arranged at the end of the chain 20 opposite to that of the input, this decoding circuit 20b having inputs connected to the non-inverting outputs of several doors 21.
  • the converter operating on N bits the chain 20 comprises at least 2N gates 21.
  • the number of gates 21 is chosen a little greater than 2N, for example equal to 2N + k and the decoding circuit 20b receives the outputs of the 2k + 1 last doors in the chain.
  • the propagation time per gate, here t1 pd is a function of the supply voltage of the integrated circuit.
  • the decoding circuit 20b is it used to supply a control quantity for adjusting the supply voltage, so that full scale is just reached when two reference signals sd and sa are applied with a time interval equal to full scale, the coding circuit 29 being connected to the first 2N doors of chain 21.
  • FIG. 3 illustrates another embodiment of a converter according to the invention in which the propagation of the starting signal in a chain of doors is stopped by the parallel blocking of the doors of the chain in response to the reception of the signal d 'stop.
  • the start signal sd is received at the input end 32 of a chain 30 of doors 31 while the stop signal sa is applied to a terminal 37 in parallel on the first door inputs 33 each associated with a respective door 31.
  • the connections of the gates 31 and 33 are identical to those of the gates 21 and 23 of the converter of FIG. 2, the gates 31 and 33 being formed on the same integrated circuit substrate from a network of prediffused gates.
  • each door 31 by the signal sd is accompanied by the blocking of the associated door 33.
  • the stop signal passes through the doors 33 not yet blocked to block the associated doors 31 and thus stop the propagation of the signal sd.
  • the state of the doors of the chain 30 is a linear function of the time interval At separating the instants t1 and t2 of reception of the signals sd and sa. This state is read directly from the non-inverting outputs of the gates 31 and converted into the form of a digital word by means of a coding circuit 39.
  • the least significant bit 6t of the word supplied by the converter is equal to t pd , that is to say the propagation time per gate of the chain 30.
  • t pd the propagation time per gate of the chain 30.
  • condition (1) is weaker by a factor 2 1/2 than condition (1), because there is only one propagation in a single chain. However, an additional dispersion is introduced because the locking of the doors 31 of the chain 30 cannot be exactly simultaneous.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Gripping On Spindles (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
EP85400870A 1984-05-11 1985-05-06 Ultraschneller zeitnumerischer Umformer Expired EP0165108B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT85400870T ATE41713T1 (de) 1984-05-11 1985-05-06 Ultraschneller zeitnumerischer umformer.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8407344A FR2564216B1 (fr) 1984-05-11 1984-05-11 Convertisseur temps-numerique ultrarapide
FR8407344 1984-05-11

Publications (2)

Publication Number Publication Date
EP0165108A1 true EP0165108A1 (de) 1985-12-18
EP0165108B1 EP0165108B1 (de) 1989-03-22

Family

ID=9303902

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85400870A Expired EP0165108B1 (de) 1984-05-11 1985-05-06 Ultraschneller zeitnumerischer Umformer

Country Status (6)

Country Link
US (1) US4719608A (de)
EP (1) EP0165108B1 (de)
JP (1) JPS60253994A (de)
AT (1) ATE41713T1 (de)
DE (1) DE3569049D1 (de)
FR (1) FR2564216B1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0508232A3 (en) * 1991-04-09 1994-05-25 Msc Microcomputers Systems Com Electronic circuit for measuring short time-intervals

Families Citing this family (17)

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Publication number Priority date Publication date Assignee Title
JPS63163296A (ja) * 1986-12-26 1988-07-06 Hitachi Ltd 時間差測定回路
US5384713A (en) * 1991-10-23 1995-01-24 Lecroy Corp Apparatus and method for acquiring and detecting stale data
US6081147A (en) 1994-09-29 2000-06-27 Fujitsu Limited Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
US6324125B1 (en) * 1999-03-30 2001-11-27 Infineon Technologies Ag Pulse width detection
US6239591B1 (en) 1999-04-29 2001-05-29 International Business Machines Corporation Method and apparatus for monitoring SOI hysterises effects
US6777708B1 (en) 2003-01-15 2004-08-17 Advanced Micro Devices, Inc. Apparatus and methods for determining floating body effects in SOI devices
US6774395B1 (en) 2003-01-15 2004-08-10 Advanced Micro Devices, Inc. Apparatus and methods for characterizing floating body effects in SOI devices
US20050222789A1 (en) * 2004-03-31 2005-10-06 West Burnell G Automatic test system
US20060129350A1 (en) * 2004-12-14 2006-06-15 West Burnell G Biphase vernier time code generator
US7761751B1 (en) 2006-05-12 2010-07-20 Credence Systems Corporation Test and diagnosis of semiconductors
WO2008033979A2 (en) * 2006-09-15 2008-03-20 Massachusetts Institute Of Technology Gated ring oscillator for a time-to-digital converter with shaped quantization noise
US8228763B2 (en) * 2008-04-11 2012-07-24 Infineon Technologies Ag Method and device for measuring time intervals
US8243555B2 (en) * 2008-08-07 2012-08-14 Infineon Technologies Ag Apparatus and system with a time delay path and method for propagating a timing event
US8065102B2 (en) * 2008-08-28 2011-11-22 Advantest Corporation Pulse width measurement circuit
US7996168B2 (en) * 2009-03-06 2011-08-09 Advantest Corporation Method and apparatus for time vernier calibration
US8098085B2 (en) 2009-03-30 2012-01-17 Qualcomm Incorporated Time-to-digital converter (TDC) with improved resolution
US8324952B2 (en) 2011-05-04 2012-12-04 Phase Matrix, Inc. Time interpolator circuit

Citations (6)

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Publication number Priority date Publication date Assignee Title
US3423676A (en) * 1965-07-02 1969-01-21 Rosenberry W K Multi-state digital interpolating apparatus for time interval measurements
FR2088363A1 (de) * 1970-05-06 1972-01-07 Ibm
US3638047A (en) * 1970-07-07 1972-01-25 Gen Instrument Corp Delay and controlled pulse-generating circuit
US4164666A (en) * 1976-06-08 1979-08-14 Toyko Shibaura Electric Co., Ltd. Electronic apparatus using complementary MOS transistor dynamic clocked logic circuits
US4433919A (en) * 1982-09-07 1984-02-28 Motorola Inc. Differential time interpolator
US4439046A (en) * 1982-09-07 1984-03-27 Motorola Inc. Time interpolator

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Publication number Priority date Publication date Assignee Title
GB729931A (en) * 1952-07-17 1955-05-11 Cinema Television Ltd Improvements in or relating to electrical timing arrangements
SU402853A1 (ru) * 1971-07-26 1973-10-19 Пензенский Политехнический Институт Цифровой измеритель интервалов времени
FR2165758B1 (de) * 1971-12-29 1974-06-07 Commissariat Energie Atomique

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3423676A (en) * 1965-07-02 1969-01-21 Rosenberry W K Multi-state digital interpolating apparatus for time interval measurements
FR2088363A1 (de) * 1970-05-06 1972-01-07 Ibm
US3638047A (en) * 1970-07-07 1972-01-25 Gen Instrument Corp Delay and controlled pulse-generating circuit
US4164666A (en) * 1976-06-08 1979-08-14 Toyko Shibaura Electric Co., Ltd. Electronic apparatus using complementary MOS transistor dynamic clocked logic circuits
US4433919A (en) * 1982-09-07 1984-02-28 Motorola Inc. Differential time interpolator
US4439046A (en) * 1982-09-07 1984-03-27 Motorola Inc. Time interpolator

Non-Patent Citations (1)

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Title
IRE TRANSACTIONS ON NUCLEAR SCIENCE, vol. NS-6, no. 1, mars 1959, pages 31-34, New York, US; R.H. RAGSDALE et al.: "A chronotron for relativistic neutron time-of-flight measurements" *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0508232A3 (en) * 1991-04-09 1994-05-25 Msc Microcomputers Systems Com Electronic circuit for measuring short time-intervals

Also Published As

Publication number Publication date
FR2564216B1 (fr) 1986-10-24
ATE41713T1 (de) 1989-04-15
US4719608A (en) 1988-01-12
EP0165108B1 (de) 1989-03-22
DE3569049D1 (en) 1989-04-27
JPS60253994A (ja) 1985-12-14
FR2564216A1 (fr) 1985-11-15

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