EP0182988A2 - Circuit d'adaptation d'un ordinateur à un moniteur couleur - Google Patents

Circuit d'adaptation d'un ordinateur à un moniteur couleur Download PDF

Info

Publication number
EP0182988A2
EP0182988A2 EP85111552A EP85111552A EP0182988A2 EP 0182988 A2 EP0182988 A2 EP 0182988A2 EP 85111552 A EP85111552 A EP 85111552A EP 85111552 A EP85111552 A EP 85111552A EP 0182988 A2 EP0182988 A2 EP 0182988A2
Authority
EP
European Patent Office
Prior art keywords
circuit
signals
digital
circuit arrangement
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP85111552A
Other languages
German (de)
English (en)
Other versions
EP0182988B1 (fr
EP0182988A3 (en
Inventor
Gerald Dipl.-Ing Gronau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Blaupunkt Werke GmbH
Original Assignee
Blaupunkt Werke GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Blaupunkt Werke GmbH filed Critical Blaupunkt Werke GmbH
Priority to AT85111552T priority Critical patent/ATE59110T1/de
Publication of EP0182988A2 publication Critical patent/EP0182988A2/fr
Publication of EP0182988A3 publication Critical patent/EP0182988A3/de
Application granted granted Critical
Publication of EP0182988B1 publication Critical patent/EP0182988B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/28—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using colour tubes
    • G09G1/285—Interfacing with colour displays, e.g. TV receiver

Definitions

  • the invention is based on a circuit according to the type of the main claim.
  • Computers have outputs for the color signals for connection to color monitors. At these outputs there are digital signals for the colors red, green and blue, that is to say signals which can only assume two values. Each of these signals therefore only indicates whether the corresponding color should light up on the screen or not. By combining these three basic colors, a total of eight colors including black and white are possible.
  • a further development is an additional computer output for a fourth digital signal representing the intensity. This makes it possible to display a total of 16 colors on the monitor.
  • the object of the present invention is to provide a circuit which obtains three analog color value signals required for controlling the monitor from the four digital signals at the output of a computer.
  • the circuit arrangement according to the invention with the characterizing features of the main claim has the advantage that the adaptation of the digital outputs of a computer to the analog inputs of a color monitor takes place with very little circuit complexity. Another advantage is that the energy consumption of this circuit is also very low. Finally, the color rendering is largely independent of level fluctuations in the digital signals.
  • the inputs 1, 2, 3 and 4 of the circuit arrangement according to FIG. 1 are supplied by the computer with the digital signals R d ' G d , B d and I d (red, green, blue and intensity). These signals are output signals from TTL circuits and should therefore be 0 or 5 V depending on the logic value. In some computers, however, the TTL circuits are followed by driver stages, which have either a larger signal amplitude and / or a negative DC voltage value. 1, protective circuits 5, 6, 7 and 8 are therefore provided in order to protect the subsequent circuits from excessive or negative voltages. An embodiment of such a protective circuit is explained in more detail in FIG. 2.
  • the signals R d , G d , B d and I d now limited in their level range arrive at a first inverting switchable limiter amplifier 9, 10, 11 and 12.
  • These switchable limiter amplifiers - called tri-state buffers in English - are in the Digital signal processing frequently used elements, which are usually intended to forward digital signals that come from a source of higher impedance to other devices (circuits, lines) with low impedance.
  • the switchable limiter amplifiers have a switch input with which the signal flow can be interrupted. If an H level is applied to this switching input, the output becomes high-resistance, so that the output assumes the level which is supplied, for example, via a resistor.
  • Switchable limiter amplifiers of this type which additionally invert the signals, are now inserted in the feed lines of the color signals and the intensity signal.
  • a suitable pulse for example the sandcastle pulse already present in a color monitor, is supplied via an input 13.
  • the pulse is fed to the switching inputs of the inverting switchable limiter amplifiers 9 to 12, with the result that no digital color signals are forwarded during the duration of the Sandcastle pulse.
  • the following circuit has the effect that in this case there is a level at the outputs 23, 24 and 25 which corresponds to the value black.
  • the output signals of the amplifiers 9 to 12 are fed to further inverting switchable limiter amplifiers 15, 16, 17 and 18. No signal is fed to them via the switching input, so that they constantly forward the signals at the input in inverted form.
  • the limiting amplifiers 15, 16 and 17 are each followed by a resistance matrix 19, 20 and 21. Each resistance matrix also becomes the output signal of the Limiter amplifier 18 supplied. Depending on the present digital level of the intensity signal, the amplitude output by the respective limiter amplifier 15, 16, 17 is influenced.
  • An embodiment for a resistance matrix will be explained in connection with FIG. 2.
  • the exemplary embodiment according to FIG. 1 has a further special feature.
  • a "par logic" circuit 22 is therefore used to determine whether this combination of the input signals is present. If applicable, a corresponding signal is fed to the resistance matrix 20.
  • the color logic 22 is supplied with the signals R d and G d in non-inverted form, the signals B d and I d in inverted form.
  • This can be achieved very easily in the circuit according to the invention in that the inputs of the color logic 22 are connected to the outputs of the first or second inverting limiter amplifiers present in a respective color channel.
  • the analog color value signals are then available for the usual further processing in a color monitor up to the supply to the control electrodes of the picture tube.
  • Fig. 2 shows a more detailed representation of the circuit of Fig. 1.
  • the protective circuits' 5, 6, 7, 8 (Fig. 1) each consist of two Schottky diodes 31 and 32 and a resistor connected in series with the respective input 33. While one of the Schottky diodes is connected to ground, the other is connected to a positive operating voltage. If the voltage falls below 0 V or if the positive operating voltage of 5 V is exceeded, which is fed to the circuit at 35, one diode becomes conductive and thus limits the input voltage. Finally, a resistor 34 is provided in each protection circuit in order to achieve a defined input potential when the input is open.
  • the protective circuits 5, 6, 7, 8 are identical to one another. Your elements are therefore provided with the same reference numerals.
  • the switching inputs of the inverting switchable limiter amplifiers 9, 10, 11, 12, the function of which has already been described in connection with FIG. 1, are controlled via a switching transistor 36 and a NAND circuit 37 operated as an inverting circuit.
  • the switching transistor 36 is supplied with the so-called Sandcastle pulse via an input 38 and a parallel connection of a resistor 39 and a capacitor 40 which serves for pulse shaping.
  • a resistor 41 serves the switching transistor 36 as a load resistor.
  • the resistors 51 reach a positive potential at the inputs of the following amplifiers 15, 16, 17, 18, at the outputs of which the potential for black is present.
  • a switching function is not required for the second inverting limiter amplifiers 15, 16, 17, 18.
  • those with switching functions were used, since all 8 required limiter amplifiers are inexpensively available on one chip.
  • the switching inputs of the respective second limiter amplifiers 15, 16, 17, 18 are therefore connected to ground potential and are therefore ineffective.
  • the outputs of the limiter amplifiers for the signals R, G and B are each fed to a resistor 42 each of a matrix circuit. Another resistor 43 of this matrix circuit, the output signal of the second limiter-amplifier for the signal I. fed. Depending on the logical value of the signal I d , the signals R, G and B have different amplitudes at the connection points of the resistors 42 and 43. These signals are then supplied to the outputs 23, 24 and 25 via a resistor network 44, 45, 46 and 47 and via a coupling capacitor 48.
  • the potentiometers 46 contained in the network are used to adjust the output levels, the resistors 47 serving to limit the setting range.
  • a color logic 22 serves to reduce the amplitude of the G signal when the color brown is to be displayed.
  • the color logic is represented by a NAND circuit 22, which the digital signals R d and G d by the limiter amplifier 15, 16 and the digital signals B d and I d after the inversion by the inverting switchable limiter amplifier 11, 12 are supplied.
  • the output of the NAND circuit 22 is then connected to a switching transistor 49, which connects the resistor 50 to ground potential.
  • the voltage divider ratios in the resistance matrix for the G signal are thus changed in the sense of a reduction in the amplitude.

Landscapes

  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Processing Of Color Television Signals (AREA)
  • Spectrometry And Color Measurement (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
EP85111552A 1984-11-29 1985-09-12 Circuit d'adaptation d'un ordinateur à un moniteur couleur Expired - Lifetime EP0182988B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT85111552T ATE59110T1 (de) 1984-11-29 1985-09-12 Schaltungsanordnung zur anpassung eines computers an einen farbmonitor.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19843443469 DE3443469A1 (de) 1984-11-29 1984-11-29 Schaltungsanordnung zur anpassung eines computers an einen farbmonitor
DE3443469 1984-11-29

Publications (3)

Publication Number Publication Date
EP0182988A2 true EP0182988A2 (fr) 1986-06-04
EP0182988A3 EP0182988A3 (en) 1987-10-28
EP0182988B1 EP0182988B1 (fr) 1990-12-12

Family

ID=6251426

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85111552A Expired - Lifetime EP0182988B1 (fr) 1984-11-29 1985-09-12 Circuit d'adaptation d'un ordinateur à un moniteur couleur

Country Status (3)

Country Link
EP (1) EP0182988B1 (fr)
AT (1) ATE59110T1 (fr)
DE (2) DE3443469A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
PL272919A1 (en) * 1988-06-08 1990-01-22 Zaklady Kineskopowe Unitra Pol Input circuit of colour crt display unit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5829514B2 (ja) * 1978-06-13 1983-06-23 松下電器産業株式会社 Ｃｒｔディスプレイ用映像増幅回路
US4388639A (en) * 1981-05-18 1983-06-14 Zenith Radio Corporation Color control circuit for teletext-type decoder

Also Published As

Publication number Publication date
DE3443469A1 (de) 1986-05-28
ATE59110T1 (de) 1990-12-15
EP0182988B1 (fr) 1990-12-12
EP0182988A3 (en) 1987-10-28
DE3580903D1 (de) 1991-01-24

Similar Documents

Publication Publication Date Title
EP0758514B1 (fr) Procede de transformation des couleurs et systeme video en couleurs
DE3119923C2 (de) Schaltungsanordnung für einen Bereichskomparator
DE2903327C2 (de) Schaltungsanordnung zur Übertragung von Gleichstromsignalen zwischen galvanisch getrennten Signalleitungen
DE3043641A1 (de) Regelbare multiplizierschaltung mit ersten und zweiten emittergekoppelten transistoren
DE3828546A1 (de) Hochgeschwindigkeits-stromverstaerker-schaltung
EP0182988B1 (fr) Circuit d'adaptation d'un ordinateur à un moniteur couleur
DE1087181B (de) Mehrfach-Gegentaktmodulatorschaltung
DE3430338C2 (de) Sendeschaltung für Signalübertragungssysteme
DE69624542T2 (de) Horizontalablenkschaltung mit über einen Thyristor eingeschaltetem S-Kondensator
DE3438907A1 (de) Schaltgeraet fuer videosignale
DE68918750T2 (de) Niederspannungsgesteuerte elektronische Schaltung in Bereitschaftsstellung mit verzögertem Abschalten.
DE69020631T2 (de) Klarblau-Schaltung für Einsatz mit Computermonitoren und analogen Geräten.
DE3032970C2 (de) Schaltungsanordnung zur Symmetrierung der Arbeitspunkte bei elektronisch gleichstromgespeisten Anschlußleitungen in Fernmelde-, insbesondere Fernsprechvermittlungsanlagen
DE1956515C3 (de) Signalübertragungseinrichtung
DE3918775C2 (fr)
DE1083350B (de) Schaltungsanordnung zur Auswertung von Mehrfrequenzenkodezeichen
DE2013000C3 (de) Schaltungsanordnung zum Umsetzen eines Gleichstromzeichens in ein trägerfrequentes, ein begrenztes Frequenzband belegendes Wechselstromzeichen
DE2428366C3 (de) Schaltungsanordnung zum Schutz eines Schaltverstärkers gegen Fremdspannungen
DE3842425C1 (en) Method and device for the temperature compensation of an attenuator
DE102023110928A1 (de) Anordnung aufweisend eine LED-Pixel-Matrix mit antiparallel geschalteten LEDs und eine Treiberschaltung zum Steuern der LED-Pixel
DE2933847B1 (de) Schaltungsanordnung zum Empfang von Gleichstromzeichen in Fernschreib- und Datenuebertragungsanlagen
DE1180972B (de) Logische UND-Schaltungsanordnung
DE2441033C3 (de) Schaltungsanordnung zur Unterdrückung von Fremd- oder Störimpulsen
DE3540752A1 (de) Schaltungsanordnung mit steuerbarem verstaerkungsfaktor
DE1142189B (de) Einrichtung zur Umwandlung bipolarer in unipolare Impulse

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT CH DE FR GB IT LI SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT CH DE FR GB IT LI SE

17P Request for examination filed

Effective date: 19880428

17Q First examination report despatched

Effective date: 19900607

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT CH DE FR GB IT LI SE

REF Corresponds to:

Ref document number: 59110

Country of ref document: AT

Date of ref document: 19901215

Kind code of ref document: T

ET Fr: translation filed
GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)
REF Corresponds to:

Ref document number: 3580903

Country of ref document: DE

Date of ref document: 19910124

ITF It: translation for a ep patent filed
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Effective date: 19910912

Ref country code: AT

Effective date: 19910912

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19910913

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Effective date: 19910930

Ref country code: CH

Effective date: 19910930

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
GBPC Gb: european patent ceased through non-payment of renewal fee
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Effective date: 19920529

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19920602

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

EUG Se: european patent has lapsed

Ref document number: 85111552.7

Effective date: 19920408