EP0187146A1 - Circuit d'invalidation d'antememoire pour un processeur de donnees - Google Patents

Circuit d'invalidation d'antememoire pour un processeur de donnees

Info

Publication number
EP0187146A1
EP0187146A1 EP19850902273 EP85902273A EP0187146A1 EP 0187146 A1 EP0187146 A1 EP 0187146A1 EP 19850902273 EP19850902273 EP 19850902273 EP 85902273 A EP85902273 A EP 85902273A EP 0187146 A1 EP0187146 A1 EP 0187146A1
Authority
EP
European Patent Office
Prior art keywords
information
cache
item
data processor
operating information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19850902273
Other languages
German (de)
English (en)
Inventor
David Scott Mothersole
Jay Alan Hartvigsen
John Zolnowsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of EP0187146A1 publication Critical patent/EP0187146A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Definitions

  • the present invention relates to data processors which have a cache memory, and more particularly, to data processors which can disable such a cache memory.
  • the cache memory is typically used to provide very quick access to instructions which are the ones being most frequently used.
  • the cache memory is typically in close proximity to a processing unit of the data processing system and has a relatively fast access time.
  • the instructions which are being frequently used are advantageously stored there to improve overall system speed.
  • These same instructions stored in the cache memory are also available elsewhere in the system and accessible via a common bus.
  • the common bus is typically available to a user.
  • An object of the present invention is to provide a data processor with an improved cache memory disable.
  • Another object of the invention is to provide a data processor with improved cache disable flexibility.
  • Yet another object of the invention is to provide a data processor with a cache memory which is disabled via a single external signal line.
  • the data processor has an information processing circuit, a memory access circuit, a cache storage circuit, a cache control circuit, and a disable circuit.
  • the information processing circuit performs operations in accordance with items of operating information provided thereto, at least one of said operations including providing an information request signal requesting one of said items of operating information.
  • the memory access circuit in response to said information request signal, retrieves said one item of said operating information from said memory, and then provides said one item of said operating information to said information processing circuit.
  • the cache storage circuit stores a selected number of all of said items of said operating information provided by said memory access circuit to said information processing circuit. If said one item of said operating information is stored in said cache storage circuit when said one item of operating information is requested by said information processing circuit, the cache storage circuit provides said one item of said operating information to said information storage circuit in response to said information request signal.
  • the cache control circuit in response to said cache storage means providing said one item of said operating information to said information processing means, prevents said memory access means from responding to said information request signal.
  • the cache disable circuit in response to a cache disable signal originating external to said data processor, prevents said cache storage means from providing said one item of information to said information processing means in response to said information request signal.
  • FIG. 1 is a block diagram of a data processing system for implementing the invention
  • FIG. 2 is a block diagram of the data processor of FIG. 1;
  • FIG. 3 is a block diagram of a data processing system with a cache according to a preferred embodiment of the invention
  • FIG. 4 is a combination logic and circuit diagram of a portion of the data processing system of FIG. 3 useful for implementing the invention.
  • FIG. 1 Shown in Figure 1 is a data processing system 10 wherein logical addresses (LADDR) issued by a data processor (DP) 12 are mapped by a memory management unit (MMU) 14 to a corresponding physical address (PADDR) for output on a physical bus (PBUS) 16. Simultaneously, the various logical access control signals (LCNTL) provided by DP 12 to control the access are converted to appropriately timed physical access control signals (PCNTL) by a modifier unit 18 under the control of MMU 14.
  • DP 12 is an example of a data processor which is capable of implementing the present invention relating to a cache memory and the disabling thereof.
  • memory 20 In response to a particular range of physical addresses (PADDR) , memory 20 will cooperate with an error detection and correction circuit (EDAC) 22 to exchange data (DATA) with DP 12 in synchronization with the physical access control signals (PCNTL) on PBUS 16. Upon detecting an error in the data, EDAC 22 will either signal a bus error (BERR) or request DP 12 to retry (RETRY) the exchange, depending upon the type of error.
  • EDAC error detection and correction circuit
  • mass storage interface 24 In response to a different physical address, mass storage interface 24 will cooperate with DP 12 to transfer data to or from mass storage 26. If an error occurs during the transfer, interface 24 may signal a bus error (BERR) or, if appropriate, request a retry (RETRY) .
  • BERR bus error
  • RETRY request a retry
  • a watchdog timer 28 may be provided to signal a bus error (BERR) if no physical device has responded to a physical address (PADDR) within a suitable time period relative to the physical access control signals (PCNTL).
  • OR gates 30 and 32 will respectively activate the BERR and HALT inputs of DP 12.
  • DP 12 will abort the current bus cycle and, upon the termination of the RETRY signal, retry the cycle.
  • operation of DP 12 may be externally controlled by judicious use of a HALT signal.
  • DP 12 In response to the activation of only the HALT input thereof via OR gate 32, DP 12 will halt at the end of the current bus cycle, and will resume operation only upon the termination of the HALT signal.
  • DP 12 In response to the activation of only the BERR input thereof during a processor-controlled bus cycle, DP 12 will abort the current bus cycle, internally save the contents of the status register, enter the supervisor state, turn off the ' trace state if on, and generate a bus error vector number. DP 12 will then stack into a supervisor stack area in memory 20 a block of information which reflects the current internal context of the processor, and then use the vector number to branch to an error handling portion of the supervisor program.
  • DP 12 differs from the MC68000 in the amount of information which is stacked in response to the assertion of BERR.
  • the information stacked by the MC68000 consists of: the saved status register, the current contents of the program counter, the contents of the instruction register which is usually the first word of the currently executing instruction, the logical address which was being accessed by the aborted bus cycle, and the characteristics of the aborted bus cycle, i.e. read/write. instruction/data and function code.
  • DP 12 is constructed to stack much more information about the internal machine state.
  • the last instruction thereof will return control of DP 12 to the aborted program.
  • the additional stacked information is retrieved and loaded into the appropriate portions of DP 12 to restore the state which existed at the time the bus error occurred.
  • DP 12 The preferred operation of DP 12 will be described with reference to Figure 2 which illustrates the internal organization of a microprogrammable embodiment of DP 12. Since the illustrated form of DP 12 is very similar to the Motorola MC68000 microprocessor described in detail in the several U.S. Patents cited hereafter, the common operation aspects will be described rather broadly. Once a general understanding of the internal architecture of DP 12 is established, the discussion will focus on the unique cache disable feature of the present invention.
  • the DP 12 is a pipelined, microprogrammed data processor.
  • each instruction is typically fetched during the execution of the preceding instruction, and the interpretation of the fetched instruction usually begins before the end of the preceding instruction.
  • each instruction is typically fetched during the execution of the preceding instruction, and the interpretation of the fetched instruction usually begins before the end of the preceding instruction.
  • each instruction is executed as a sequence of microinstructions which perform small pieces of the operation defined by the instruction. If desired, user instructions may be thought of as macroinstructions to avoid confusion with the microinstructions.
  • each microinstruction comprises a microword which controls microinstruction sequencing and function code generation, and a corresponding nanoword which controls the actual routing of information between functional units and the actuation of special function units within DP 12.
  • a prefetch microinstruction will be executed.
  • the microword portion thereof will, upon being loaded from micro ROM 34 into micro ROM output latch 36, enable function code buffers 38 to output a function code (FC) portion of the logical address (LADDR) indicating an instruction cycle.
  • FC function code
  • LADDR logical address
  • the corresponding nanoword requests bus controller 44 to perform an instruction fetch bus cycle, and instructs execution unit 46 to provide the logical address of the first word of the next instruction to address buffers 48.
  • bus controller 44 Upon obtaining control of the PBUS 16, bus controller 44 will enable address buffers 48 to output the address portion of the logical address (LADDR).
  • bus controller 44 will provide appropriate data strobes (some of the LCNTL signals) to activate memory 20.
  • bus controller 44 enables instruction register capture (IRC) 50 to input the first word of the next instruction from PBUS 16.
  • IRC instruction register capture
  • another microinstruction will be executed to transfer the first word of the next instruction from IRC 50 into * instruction register (IR) 52, and to load the next word from memory 20 into IRC 50.
  • the word in IRC 50 may be immediate data, the address of an operand, or the first word of a subsequent instruction. Details of the instruction set and the microinstruction sequences thereof are set forth fully in U.S. Patent No. 4,325,121 entitled "Two Level Control Store for Microprogrammed Data Processor” issued 13 April 1982 to Gunter et al, and which is hereby incorporated by reference.
  • address 1 decoder 54 begins decoding certain control fields in the instruction to determine the micro address of the first microinstruction in the initial microsequence of the particular instruction in IR 52.
  • illegal instruction decoder 56 will begin examining the format of the instruction in IR 52. If the format is determined to be incorrect, illegal instruction decoder 56 will provide the micro address of the first microinstruction of an illegal instruction microsequence. In response to the format error, exception logic 58 will force multiplexor 60 to substitute the micro address provided by illegal instruction decoder 56 for the micro address provide by address 1 decoder 54.
  • the microword portion thereof may enable multiplexor 60 to provide an appropriate micro address to micro address latch 62, while the nanoword portion thereof enables instruction register decoder (IRD) 64 to load the first word of the next instruction from IR 52.
  • instruction register decoder ILD
  • micro ROM 34 Upon the selected micro address being loaded into micro address latch 62, micro ROM 34 will output a respective microword to micro ROM output latch 36 and nano ROM 40 will output a corresponding nanoword to nano ROM output latch 42.
  • micro ROM output latch 36 specifies the micro address of the next microinstruction to be executed, while another portion determines which of the alternative micro addresses will be selected by multiplexor 60 for input to micro address latch 62.
  • more than one microsequence must be executed to accomplish the specified operation. These tasks, such as indirect address resolution, are generally specified using additional control fields within the instruction.
  • the micro addresses of the first microinstructions for these additional microsequences are developed by address 2/3 decoder 66 using control information in IR 52.
  • the first microsequence will typically perform some preparatory task and then enable multiplexor 60 to select the micro address of the microsequence which will perform the actual operation as developed by the address 3 portion of address 2/3 decoder 66.
  • the first microsequence will perform the first preparatory task and then will enable multiplexor 60 to select the micro address of the next preparatory microsequence as developed by the address 2 portion of address 2/3 decoder 66.
  • the second microsequence Upon performing this additional preparatory task, the second microsequence then enables multiplexor 60 to select the micro address of the microsequence which will perform the actual operation as developed by the address 3 portion of address 2/3 decoder 66.- In any event, the last microinstruction in the last microsequence of each instruction will enable multiplexor 60 to select the micro address of the first microinstruction of the next instruction as developed by address 1 decoder 54. In this manner, execution of each instruction will process through an appropriate sequence of microinstructions. A more thorough explanation of the micro address sequence selection mechanism is given in U.S. Patent No. 4,342, 078 entitled "Instruction Register Sequence Decoder for Microprogrammed Data Processor" issued 27 July 1982 to Tredennick et al, and which is hereby incorporated by reference.
  • the nanowords which are loaded into nano ROM output latch 42 indirectly control the routing of operands into and, if necessary, between the several registers in the execution unit 46 by exercising control over register control (high) 68 and register control (low and data) 70.
  • the nanoword enables field translation unit 72 to extract particular bit fields from the instruction in IRD 64 for input to the execution unit 46.
  • the nanowords also indirectly control effective address calculations and actual operand calculations within the execution unit 46 by exercising control over AU control 74 and ALU control 76.
  • the nanowords enable ALU control 76 to store into status register (SR) 78 the condition codes which result from each operand calculation by execution unit 46.
  • ALU control 76 is given in U.S. Patent No. 4,312,034 entitled "ALU and Condition Code Control Unit for Data Processor" issued 19 January 1982 to Gunter, et al, and which is hereby incorporated by reference.
  • FIG. 3 Shown in FIG. 3 is an integrated circuit data processor system 300 with a cache function enclosed in dotted lines comprised of DP 12, a cache 301, a compare circuit 302, a cache control circuit 303.
  • An external pin 304 for receiving a cache disable signal *CDIS is also shown in FIG. 3.
  • Pin 304 is shown outside the dotted lines to show that signal *CDIS is generated externally from data processor system 300.
  • An asterisk (*) indicates the signal function is active when the signal is a logic low. In this case when signal *CDIS is a logic low, the cache function is disabled.
  • Pin 304 is directly connected to cache control circuit 303 of integrated circuit data processor 300 which receives signal *CDIS.
  • a memory 305 is also external to integrated circuit data processor system 300 and is coupled thereto by a communication bus 306. Of course many other external pins (not shown) are connected to integrated circuit data processor 300.
  • Cache control circuit 303 provides a hit signal HIT at a logic high when DP 12 can utilize cache 301.
  • Data processor system 300 uses cache 301 to store frequently used items of operating information normally called instructions. Each instruction has a memory location defined by an address. This address acts as a request signal for the particular instruction.
  • a portion of cache 301 stores these addresses of the instructions which are stored in cache 301.
  • the address storage portion of a cache, such as cache 301, is frequently called TAG cache and the addresses stored therein are called TAGs.
  • DP 12 generates an address for an instruction which compare circuit 12 compares to addresses (or TAGs) stored in cache 301. This comparison will be valid only if cache control circuit 303 generates a compare signal ⁇ COMPARE at a logic low. If compare circuit 302 does not detect that the addresses are different (a miss) , then an addresses compare signal ADCOMP is generated at a logic high. Cache 301 will generate a TAG valid signal TAGV if the compared address is valid. It is possible for the address generated by DP 12 to match an address in cache 301 which was placed in cache 301 at a start-up operation and not incidental to writing an instruction into cache 301. Consequently, it is necessary to verify that the compared address has in fact a valid corresponding instruction in cache 301.
  • a signal TAGSACLK is a clock signal for synchronizing the comparison of the TAGs and the address of the instruction.
  • Signal *COMPARE cannot be generated until signal TAGSACLK switches to a logic high.
  • Another signal, valid instruction holding state signal *VIH0LDS also can prevent signal *COMPARE from being generated.
  • DP 12 generates signal *VIHOLDS at a logic high during an access. Because such access may be to cache 301, it is desirable to prevent cache 301 from being disabled by signal *CDIS when signal *VIH0LDS is a logic high. Consequently, cache control 303 prevents both signal *C0MPARE and signal HIT from responding to signal *CDIS when signal *VIHOLDS is a logic high.
  • DP 12 itself may or may not be in a mode where cache 301 is to be utilized. This information is communicated by a load cache register signal LDCACR, a state of cache register signal STCACR, and a least significant bit *BC0 from an information bus (not shown except bit * BCO) . DP 12 also provides a reset signal RESET which brings cache control circuit 303 to an initialized state. In the initialized state cache 301 is not to be utilized. The cache utilization state is communicated to cache control circuit 303 by DP 12 by providing signal LDCACR at a logic high and selecting bit *BCO to be the logic state which corresponds to the cache utilization state of DP 12.
  • a logic high corresponds to not being in the cache utilization state, whereas a logic low corresponds to being in the cache utilization state.
  • Cache control circuit 303 will store this information until DP 12 changes it.
  • DP 12 can read the state of stored bit *BCO by providing signal STCACR at a logic high which will cause control circuit 303 to output bit *BCO at the stored state thereof.
  • Bit *BCO at a logic low means that the cache utilization state is present whereas bit *BCO at a logic high means that the cache utilization state is not present and cache 301 is not to be utilized.
  • An occurrence of signal RESET at a logic high indicates that DP 12 is being initialized and is therefore not to be in the cache utilization state.
  • Cache control circuit 303 consequently responds to signal RESET at a logic high by forcing stored bit *BCO to a logic high.
  • signal HIT is provided by cache control circuit 303 at a logic low.
  • the effect of signal HIT being a logic low is that the addressed instruction must be accessed externally from data processing system 300 to memory 305 via communication bus 306. If signal HIT is a logic high, then cache 301 provides the requested instruction, and memory 305 does not receive the address for the requested instruction. Consequently, cache control circuit 303 has the effect of preventing communication bus 306 from carrying the address for the requested instruction when cache 301 provides the requested instruction.
  • An external access to memory 305 is required under any of the following five conditions; when system 300 is reset by signal RESET at a logic high, when DP 12 has set stored bit *BCO to a logic high, when the cache address and the address of the instruction do not match as indicated by signal ADCOMP being a logic low, when the TAG does not have a properly corresponding instruction in cache 301 as indicated by TAGV being a logic low, or when externally provided signal *CDIS is a logic low.
  • a user of system 300 can prevent DP 12 from accessing cache 301 while maintaining normal operation by either software or hardware means, and thereby offering flexibility not previously seen in the art.
  • the user can cause DP 12 to store bit *BCO at a logic high, in cache control 303 or can externally provide signal *CDIS at a logic low at pin 304. Either of these conditions will cause signal HIT to be a logic low,thereby causing DP 12 to make an instruction access which is external to system 300, and thereby making such instruction access readable by a user of system 300.
  • FIG.s 4A and 4B Shown in FIG.s 4A and 4B is a combination logic and circuit diagram of a circuit which can be used for implementing cache control 303.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un processeur de données (300) est exploité avec une mémoire (305) contenant une pluralité d'éléments d'information d'exploitation pour le processeur de données (300). De plus, une antémémoire (301) enregistre un nombre sélectionné d'éléments d'information d'exploitation parmi leur totalité. Lorsque l'antémémoire (301) fournit un élément d'information d'exploitation, la mémoire (305) n'est pas appelée à fournir l'élément, de sorte qu'un utilisateur du processeur de données (300) ne peut pas détecter la demande de l'élément. Un circuit d'invalidation est créé afin d'empêcher l'antémémoire (301) de fournir l'élément lorsqu'un signal extérieur au processeur de données (300) est fourni. Par conséquent, un utilisateur peut, à l'aide du signal extérieur, faire en sorte que le processeur de données (300) adresse toutes ses demandes d'éléments d'information d'exploitation à la mémoire (305), où ces demandes peuvent être détectées.
EP19850902273 1984-06-26 1985-04-12 Circuit d'invalidation d'antememoire pour un processeur de donnees Withdrawn EP0187146A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62534284A 1984-06-26 1984-06-26
US625342 1990-12-11

Publications (1)

Publication Number Publication Date
EP0187146A1 true EP0187146A1 (fr) 1986-07-16

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP19850902273 Withdrawn EP0187146A1 (fr) 1984-06-26 1985-04-12 Circuit d'invalidation d'antememoire pour un processeur de donnees

Country Status (3)

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EP (1) EP0187146A1 (fr)
CA (1) CA1233271A (fr)
WO (1) WO1986000440A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0239255A (ja) * 1988-07-28 1990-02-08 Toshiba Corp キャッシュメモリ
US5241681A (en) * 1989-11-03 1993-08-31 Compaq Computer Corporation Computer system having an internal cach microprocessor slowdown circuit providing an external address signal
US6355921B1 (en) 1999-05-17 2002-03-12 Agilent Technologies, Inc. Large dynamic range light detection

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4075686A (en) * 1976-12-30 1978-02-21 Honeywell Information Systems Inc. Input/output cache system including bypass capability
US4357656A (en) * 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
JPS54128634A (en) * 1978-03-30 1979-10-05 Toshiba Corp Cash memory control system
US4264953A (en) * 1979-03-30 1981-04-28 Honeywell Inc. Virtual cache
US4464717A (en) * 1982-03-31 1984-08-07 Honeywell Information Systems Inc. Multilevel cache system with graceful degradation capability

Non-Patent Citations (1)

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Title
See references of WO8600440A1 *

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Publication number Publication date
WO1986000440A1 (fr) 1986-01-16
CA1233271A (fr) 1988-02-23

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