EP0201267A2 - Zeilenprozessor für eine bitkartierte Anzeige - Google Patents

Zeilenprozessor für eine bitkartierte Anzeige Download PDF

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Publication number
EP0201267A2
EP0201267A2 EP86303243A EP86303243A EP0201267A2 EP 0201267 A2 EP0201267 A2 EP 0201267A2 EP 86303243 A EP86303243 A EP 86303243A EP 86303243 A EP86303243 A EP 86303243A EP 0201267 A2 EP0201267 A2 EP 0201267A2
Authority
EP
European Patent Office
Prior art keywords
frame buffer
row
bit
display
scan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86303243A
Other languages
English (en)
French (fr)
Other versions
EP0201267A3 (de
Inventor
Joseph H. Hubert
Donald J. Eckardt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of EP0201267A2 publication Critical patent/EP0201267A2/de
Publication of EP0201267A3 publication Critical patent/EP0201267A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/08—Cursor circuits

Definitions

  • the present invention relates to frame buffers for raster scan displays, and more particularly to a row processor for a bit-map display which performs per-scan-line display and copy functions.
  • a frame buffer In raster scan displays a frame buffer is used to store a digital representation of an ,image to be displayed.
  • the frame buffer is divided into one or more planes, each plane having a plurality of words, each word representing a plurality of picture elements, or pixels.
  • each display For a display of 640 pixels across by 480 rows with 16-bit (pixel) frame buffer words, each display is composed of 40 words per row, 19,200 words in all.
  • a display cycle consists of a plurality of horizontal display cycles for each scan line with a plurality of horizontal blanking cycles after each horizontal scan line during the horizontal retrace period of the display. Each cycle consists of a refresh portion during which a word is read from the frame buffer, and an update portion during which data can be written into the frame buffer or data in the frame buffer can be modified.
  • bit block transfer To move a portion, or block, of the image from one position to another within the display, an operation referred to as bit block transfer (BITBLT) is performed.
  • BITBLT bit block transfer
  • attempts to scroll an image via BITBLT result in tearing, flickering or inchworming distortion of the image. What is desired is a smooth scrolling of an image without such distortion.
  • the present invention provides a row processor unit for a bit-map, raster scan display which performs per-scan-line frame buffer management functions.
  • a portion of the frame buffer memory which is not used for display contains load/decode parameters. These parameters are accessed by the row processor unit during the horizontal blanking interval and used for display and data movement operations during the refreshing of the following scan line.
  • a pattern memory provides pixel masks for scrolling as well as providing cursor patterns.
  • a frame buffer 10 having a frame buffer memory 12 with one or more planes (A, B, C, D).
  • the frame buffer memory 12 has a 640x480 pixel display bit-map and a row processor unit field 16 which is 112x512 pixels on the A-plane.
  • the remainder of the 1024x512 pixel frame buffer memory 12 may be used for other purposes.
  • Fig. 2 is illustrative of one frame buffer geometry where each frame buffer word is 16-bits, or 2-bytes, long.
  • a CRT (cathode ray tube) controller 18 provides row and column addresses for the frame buffer memory 12 during refresh display cycles.
  • a frame buffer addressing circuit 20 is situated between the CRT controller 18 and the frame buffer memory 12 for row address selection.
  • a color map 22 receives the pixel display data from the display bit-map 14 as accessed by the CRT controller 18 and outputs a video signal to a display device which includes color information.
  • a row processor unit 24 received the data contained in the row processor field 16 and decodes such data to perform several functions.
  • a pattern memory 26 contains cursor patterns and scroll masks.
  • the row processor unit 24 selects either a cursor pattern or a scroll mask from the pattern memory 26 by row as the CRT controller 18 clocks through the columns.
  • the column addresses from the CRT controller 18 also are input to the row processor unit 24.
  • the row processor unit 24 accesses the frame buffer addressing circuit 20 as does a display processor, or central processing unit (CPU).
  • the row processor unit 24 also accesses the color map 22 to effect palette color changes or cursor color.
  • a frame buffer state machine 28 acts as a traffic controller and provides the timing signals for the frame buffer 10.
  • the cursor from the pattern memory 26 selected by the row processor unit 24 is input to the color map 22 for output as video data to the display unit.
  • the row processor unit 24 and pattern memory 26 are shown in greater detail in Figs. 3-5.
  • the A-plane data (APD) from the frame buffer memory 12 is input to a data latch 30 and clocked out for each column clockpulse (CCLK), i.e., once for each frame buffer word.
  • the output from the data latch 30 forms a row processor data (RPD) bus.
  • a decoder 32 receives as inputs bits 0,1 and 15 of each RPD word, the column count (CC) and most significant bit of the row count (CR9) from the CRT controller 18, a row block transfer enable (ROWBLTEN) signal from the display processor and a row processor strobe (RPSTB) signal from the state machine 28.
  • Bit 15 of each row processor word (words 40-46 for each scan line) is a load bit.
  • the decoder 32 is inhibited.
  • CR9 is set, equivalent to row 512 and above, which is outside the extent of the frame buffer memory 12, the decoder 32 also is inhibited.
  • bit 15 for each word is checked to see if it is set. If bit 15 is set, the decoder 32 outputs a command for a row function to be performed on the next scan line.
  • an interrupt signal (INTO and/or INT1) is output from the decoder 32 if bit 15 and bit 0 and/or bit 1 is set in word 40.
  • INTO/1 are used to synchronize the row processing unit 24 with the CPU.
  • a cursor load (CURSORLD) signal is output.
  • a palette load (PALD) signal is output if bit 15 is set, each word referencing one of the bit-planes.
  • ROWBLTRQ row block transfer request
  • RBMASKLD row block transfer mask load
  • word 46 provides a row processor counter enable (RPCNTEN) signal when bit 15 is set as well as a row counter load (RCNTLD) signal.
  • RPCNTEN row processor counter enable
  • the parameters in that word are either executed immediately or loaded into registers.
  • the function executed may be for a single scan line, such as the interrupt pulses, INTO, INT1, or may be performed on successive lines using the same parameters until new values are loaded or-the function disabled, such as cursor and scrolling operations.
  • a cursor word (41) is decoded by the decoder 32
  • the CURSORLD signal clocks the parameter value in bits 0-4 into a cursor register 34.
  • the value in the cursor register 34 is a row address (PROW) for the pattern RAM 26.
  • the pattern at that row is transferred, when the output of the cursor register is enabled by a video enable (VIDEN) signal, to a cursor shift register 36 upon receipt of a shift register load (SRLD) signal from the frame buffer controller (FBC) 28 and the cursor enable (CURSEN) from the cursor register.
  • SRLD shift register load
  • the dot clock pulses (DCLK) then clock out the cursor to the video display circuit via the color map circuit 22 for display.
  • the RBMASKLD signal from the decoder 32 clocks the mask pattern value and the plane mask value into a mask register 38.
  • the plane mask value provides an enable signal (APEN, BPEN, CPEN, DPEN) from the mask register 38 to the respective planes, and the mask pattern provides a row address to the pattern RAM 26 when the mask register output is enabled by a row block transfer write (ROWBLTWR) signal from the frame buffer controller 28.
  • a row destination counter 40 is enabled by the RPCNTEN signal and the address destination for the data on the following scan line is loaded into the register by the RCNTLD signal.
  • the ROWBLTWR signal also outputs a frame buffer row address (FR) into which the data of that scan line is rewritten for the pixels in each column specified by the mask pattern.
  • FR frame buffer row address
  • the RPSTB signal which occurs during every word access, increments the row destination counter 40 during the scroll/fill operation when enabled by RPCNTEN.
  • Figs. 6 and 7 illustrate the operation of the frame buffer 10.
  • each frame buffer word is readout during the refresh time, including the cursor from the pattern RAM 26.
  • the frame buffer 10 may be accessed by the CPU.
  • the video data readout from the frame buffer memory 12 is latched and held until the update cycle.
  • the video data is rewritten into the frame buffer memory 10 at the location specified by the row destination counter 40 for the pixels indicated by the mask pattern.
  • the CRT controller 18 continues to increment through the frame buffer memory 10.
  • the words from the RPU field 16 are readout and decoded, and the parameters contained therein are loaded into appropriate registers for execution during the next scan line. Again as in normal display the CPU has access to the frame buffer memory 10 during the update portion of the blanking cycle. At the completion of horizontal retrace the column count is reset to zero and the CRT controller increments the row address to display the next scan line.
  • the present invention provides a row processor for a bit-map, raster scan display which uses an unused portion of a frame buffer memory for each scan line to store instructions and parameters which are executed on subsequent scan lines to eliminate image distortion during scroll/fill operations.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Digital Computer Display Output (AREA)
EP86303243A 1985-05-02 1986-04-29 Zeilenprozessor für eine bitkartierte Anzeige Withdrawn EP0201267A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73000385A 1985-05-02 1985-05-02
US730003 1985-05-02

Publications (2)

Publication Number Publication Date
EP0201267A2 true EP0201267A2 (de) 1986-11-12
EP0201267A3 EP0201267A3 (de) 1990-04-04

Family

ID=24933514

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86303243A Withdrawn EP0201267A3 (de) 1985-05-02 1986-04-29 Zeilenprozessor für eine bitkartierte Anzeige

Country Status (2)

Country Link
EP (1) EP0201267A3 (de)
JP (1) JPS61254984A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989006030A1 (en) * 1987-12-24 1989-06-29 Ncr Corporation Apparatus for generating a cursor pattern on a display

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4435776A (en) * 1981-01-27 1984-03-06 Syntrex Incorporated Word processing system
FR2544898B1 (fr) * 1983-04-25 1985-07-19 Texas Instruments France Dispositif d'affichage video sur ecran d'affichage par balayage d'une trame ligne par ligne et point par point

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1989006030A1 (en) * 1987-12-24 1989-06-29 Ncr Corporation Apparatus for generating a cursor pattern on a display
US4987551A (en) * 1987-12-24 1991-01-22 Ncr Corporation Apparatus for creating a cursor pattern by strips related to individual scan lines
AU611521B2 (en) * 1987-12-24 1991-06-13 Ncr Corporation Apparatus for generating a cursor pattern on a display

Also Published As

Publication number Publication date
EP0201267A3 (de) 1990-04-04
JPS61254984A (ja) 1986-11-12

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Inventor name: ECKARDT, DONALD J.