Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/02—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes by tracing or scanning a light beam on a screen

Definitions

• Known computer control laser display systems comprise a pair of mirrors mounted on precision galvanometers which deflect the beam in an x-y plane, in response to X, Y co-ordinates provided by the computer.
• the laser beam can be made to trace a desired pattern on a screen. If the pattern is swept by the beam at a sufficiently high rate, the traced pattern will appear to be continuously illuminated to the human eye.
• the laser can then be used in applications such as advertising, light shows and the production of special effects.
• the co-ordinates of the points of the image must first be calculated by the computer, converted to analogue voltages and fed to respective precision galvanometer/mirror assemblies. Moreover, the co-ordinate values must be fed to the galvanometer/mirrors at least at a sufficiently high rate.
• Known systems cannot achieve real time creation and alteration of laser display patterns since the computers used cannot calculate display co-ordinates from input instructions at a high enough rate to allow the supply of co-ordinate data to the mirrors in real-time.
• the presently available laser display systems require the co-ordinates of the desired image to be first calculated, then stored in memory from which they are read out at a predetermined rate.
• the known systems are generally inflexible and allow little interaction by the operator. Further, the large amounts of memory required to store co-ordinates of even simple images increases the costs and complexity of the laser display system.
• interrupts are communicated to the computer to cause the computer to switch between two programmes running in the computer, an application programme 43 typically written is BASIC (a language in which many programmers are fluent) , and a computation programme 42 written in machine language and used to calculate the data for the FIFO memory.
• interrupt 34 causes the computer to switch to the application programme 43, for example to receive keyboard instructions from the operator or to accept preprogrammed instructions.
• computer interrupt 34 causes the computer to switch to the computation programme to calculate more co-ordinate data for the laser control device.
• the computation programme is written in machine language for rapid execution.
• the use of the "full" interrupt 35 allows the machine language routine to execute without the normal practice of continually testing an interface to determine if it can accept data, a time consuming requirement of known laser display systems.
• the machine language programme 42 performs some computations, adding offsets to various parts of images and performing the interpolations between images. It is relatively simple to add new computational functions to this programme.
• the machine language programme is driven by tables held in memory and by images referenced by the tables.
• FIG. 2 a more detailed schematic illustration of one half of the data buffer of the preferred embodiment is shown.
• the X buffer 11 of Figure 1 is realised using a pair of FIFO buffers 31 and 32 connected in series, each of the FIFO buffers having a status output which indicates when the buffer is full.
• FIG. 3 one half of a second embodiment of the FIFO buffer is illustrated schematically.
• the computer output data is fed to one of a pair of buffers 52 and 53 via a demultiplexing device 51 while at the same time data from the other of the pair of buffers 52 and 53 is being fed from the buffer to the digital to analogue converter 13 via a multiplexer 54.
• the data transfer to and from the buffers 52 and 53 is under the control of a buffer control circuit 55.
• the buffers 52 and 53 could be simple shift registers, as one buffer will
• Addresses FF74 to FF77 are used in controlling and setting up the PIA (IC2) as shown in Table 1.
• the PIA (IC2) data direction registers A and B are set so that both peripheral interface ports A (PAO-7) and B (PBO-7) are used as output ports.
• the control registers are set such that interrupt line CAl detects (with IC14 a and b) when the FIFO buffer (IC3, 4, 5 and 6) is full and interrupt CBl detects when the FIFO buffer (IC3, 4, 5 and 6) is "nearly empty". The nearly empty state is indicated in this embodiment when the buffer is less than half empty,
• CB2 is set as a control signal and strobes the data when available into FIFO's IC3 and 5.
• CA2 is set to control the *D' type flip-flop IC15 which via the FIFO data bit D8 controls: a) the FIFO output clock (IC3 and 4) , and b) the operation of a shutter (not shown) to control the laser output (IC5 and 6) .
• the timer chip (ICI) is set to produce two frequencies one of which is selected by IC16 to control the output from the FIFO's (IC3, 4, 5 and 6).
• the frequency selected is controlled by FIFO data bit 8 (IC3 and 4) and the 2:1 MUX chip IC16.
• the output from the Timer No 2 output is used to control the FIFO .output when displaying images, with control being changed to the timer No 1 output for character display. Both the timer output frequencies have been selected to be less than the input strobe so that interrupt control can be achieved.
• IC7 and IC8 are 8 bit high speed digital-to-analog convertors. IC7 controls the 'X' axis of the laser image whilst IC8 controls the 'Y' axis.
• the output from the laser card is taken via a 9 pin "D" type connector to the laser unit.
• the interface is designed for operation with a Hitachi Peach computer, with disk drives and digitiser.
• the interface circuit can be repackaged to suit an Hitachi Si computer (a compatible upgrade of the MB 6890 computer) , or the interface circuit can be implemented by "black box" units containing their own micro processors, but co-ordinated by a central computer.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• General Physics & Mathematics (AREA)
• Theoretical Computer Science (AREA)
• Controls And Circuits For Display Device (AREA)

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Citations (5)

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• 1986
  • 1986-05-29 WO PCT/AU1986/000152 patent/WO1986007164A1/fr not_active Ceased
  • 1986-05-29 EP EP19860903149 patent/EP0227702A4/fr not_active Withdrawn

Patent Citations (5)

Non-Patent Citations (2)

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