EP0228207A2 - Dispositif de circuit avec test incorporé pour logique combinatoire - Google Patents

Dispositif de circuit avec test incorporé pour logique combinatoire Download PDF

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Publication number
EP0228207A2
EP0228207A2 EP86309560A EP86309560A EP0228207A2 EP 0228207 A2 EP0228207 A2 EP 0228207A2 EP 86309560 A EP86309560 A EP 86309560A EP 86309560 A EP86309560 A EP 86309560A EP 0228207 A2 EP0228207 A2 EP 0228207A2
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EP
European Patent Office
Prior art keywords
data output
logic circuit
function block
blocks
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86309560A
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German (de)
English (en)
Other versions
EP0228207A3 (fr
Inventor
Robert Perlman
Alan Corry
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP0228207A2 publication Critical patent/EP0228207A2/fr
Publication of EP0228207A3 publication Critical patent/EP0228207A3/fr
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Definitions

  • the present invention relates to fault detection and isolation circuits in general and to fault detection and isolation circuits for detecting and isolating faults in a large multi-level combinatorial logic circuit in particular.
  • Many digital logic circuits comprise essentially two types of logic circuits. One type is called a combinatorial logic circuit. The other type is called a sequential logic circuit.
  • An example of a combinatorial logic circuit is an AND gate comprising a plurality of inputs and an output in which the output is strictly a function of the inputs.
  • Such circuits in general, are not bistable and consequently do not store data or contain state information.
  • An example of a sequential logic circuit is a flip-flop comprising a plurality of inputs and a plurality of outputs.
  • the outputs of a sequential logic circuit are a function of its inputs and its previous state. For example, if a flip-flop is initially set to a logical 1 state, a set 1 input signal will not change the state of the flip-flop. However, if the flip-flop is initially in a logical 0 state, a set 1 input signal will change the flip-flop from its logical 0 state to its logical 1 state. Moreover, the outputs of the flip-flop, regardless of the state to which it has been set or reset, will remain after the inputs are removed.
  • the combinatorial logic is sandwiched between a first and a second sequential logic circuit, e.g. a pair of shift registers.
  • a first test pattern is shifted into the first shift register.
  • the test pattern is operated on by the combinatorial logic circuit and the results thereof transferred into the second shift register.
  • the results transferred into the second shift register are then compared with a second test pattern. If there is a predetermined correspondence between the results and the second test pattern, the tested circuits are assumed to be operational. If not, the tested circuits are repaired or replaced.
  • This shift register technique is not suitable for testing more complex digital circuits comprising many levels of combinatorial logic. This technique is unsuitable because it is often difficult to feed an appropriate test pattern from the input or inputs of a large multi-level combinatorial logic circuit to a section of logic buried deep in the circuit.
  • One of the reasons for this difficulty is that logic sections upstream from the section of logic under test often manipulate a test pattern applied to the inputs of the circuit during the normal operation thereof in an unpredictable manner or in such a manner that a desired test pattern simply cannot be generated at the inputs of the section of logic under test. Another reason is that the upstream logic itself may be defective. This problem is one of controllability.
  • the logic sections downstream from a logic section under test can so manipulate the output of the logic section under test or can themselves be defective such that the results of the test are indeterminate. This problem is one of observability.
  • proposals for isolating and detecting faults in deeply buried sections of logic in complex combinatorial logic circuits have generally comprised the use of a 2-to-1 multiplexer coupled to the input and a pass gate coupled to the output of selected logic sections, a test pattern input bus and a test results output bus.
  • the input of a selected logic section was isolated from the output of the preceding upstream logic sections by the multiplexer.
  • a test pattern was applied to the input of the section via the test pattern input bus and the multiplexer. The results of the test were passed to the output bus via the pass gate coupled thereto.
  • a principal disadvantage of the above described prior known method and apparatus for isolating and detecting faults in deeply buried sections of complex combinatorial logic circuits is that a considerable amount of space on the chip is required for the multiplexers, the pass gates and the two test pattern and test result busses.
  • a combinatorial shifter comprising a plurality of rows of multiplexers is normally capable of shifting data a selected number of bits as a function of control signals applied to normally available control signal inputs.
  • One of the normally available control signal inputs is a zero shift control signal input which when active causes data applied to the input to be passed to the output of the shifter without modification, i.e. without having been shifted.
  • the shifter can be made to appear "transparent" to data applied to its input with no additional hardware required.
  • combinatorial adders and subtracters and other types of logic circuits can be made to appear transparent with very little additional hardware required by simply providing enough hardware such that during a test a test pattern or test results from another circuit applied to the input of the circuit is provided at the output of the circuit without modification.
  • a multi- level complex combinatorial logic circuit to be tested is first partitioned into function blocks (e.g. adders, shifters, multipliers) and control blocks.
  • the control blocks may comprise, for example, RAM, ROM, PROM, PLA, or a combination thereof.
  • Each function block is then modified, if and as required, to pass data transparently when given an appropriate control command from a control block.
  • this "pass" function requires, as indicated above, that the function block be modified by a small amount of additional hardware.
  • no additional hardware is needed since, as mentioned above, a shifter can be made to pass data by supplying it a shift count of zero.
  • control blocks are modified to respond to a special set of controls, or a test instruction set, that command all function blocks except the one under test to pass data transparently. In this fashion, data can be fed from input pins of the logic circuit to the function block under test without modification. Similarly, test results from the block under test can be fed to the output pins of the logic circuit without modification.
  • the transparent paths to and from the function block under test provide controllability and observability. Moreover, the necessary changes to the control blocks are made by adding product terms requiring little or no hardware expense.
  • the present arrangement also provides fault isolation with a minor addition of hardware to otherwise conventional combinatorial logic circuits.
  • a test result output bus By passing a test result output bus through all function blocks, and by adding 3-state drivers from the output of each block to the bus, the test result from any function block can be observed directly, i.e. without passing through any other function block. Therefore, by testing function blocks in a predetermined sequence a fault can be detected and isolated to a particular function block. For example, if the first function block in the sequence is found to be without a fault, that block is rendered transparent to pass a test pattern applied to its inputs which is appropriate for testing the next function block in the sequence to the input of the next function block in the sequence without modification.
  • next function block in the sequence is found to be free of faults it and the previously tested function block are rendered transparent to a test pattern appropriate to the following function block and so on until all blocks have been tested. In this manner, the space for multiplexers and a test pattern input bus as required in prior known apparatus is saved for other purposes.
  • data is injected into the function blocks by 2:1 multiplexers.
  • the blocks are tested and rendered transparent in a reverse sequence to effect fault detection and isolation with the test results observed on the outputs of the first block test after each test. For example, after each function block is tested and found to be free of faults, beginning with the last function block in a predetermined sequence, all function blocks downstream of the function block under test are rendered transparent to the test results from the function block under test. In this manner, the space for a test results bus as required in prior known apparatus is saved for other purposes.
  • a large multilevel combinatorial logic circuit designated generally as 1.
  • the circuit 1 is shown divided into a plurality of function blocks 2 and a plurality of control blocks 3.
  • the function blocks 2 there is illustrated a multiplier 4, a shifter 5, an adder 6, a shifter 7, an adder 8, and a shifter 9.
  • the control blocks 3 comprise a plurality of control blocks 10-15.
  • the control blocks 10-15 are coupled to the function blocks 4-9 by means of a plurality of control signal buses 20-25. Normal instructions and test instructions are provided to the control blocks 10-15 on an instruction bus 26.
  • a plurality of data buses which are represented by a plurality of single unbroken arrows 30-36.
  • the unbroken arrows 30-36 in addition to representing data buses, more importantly represent the flow of data through the circuits 4-9 as the data is processed therein in a conventional manner in response to normal arithmetic and logic instructions under the control of the control blocks 10-15.
  • a pair of operands on the data buses represented by the unbroken arrow 30 is processed in the multiplier 4 and the resulting operand is then placed on the data bus represented by the arrow 31 for processing in the shifter 5.
  • the data is processed in the shifter 5, it is placed on the data bus 32 for processing in the adder 6.
  • the body of the broken arrow 40 is shown passing through the circuits 4 and 5 and having a head terminating at the data input of the adder 6.
  • the body of the broken arrow 41 is shown commencing at the data output of the adder 6 and passing through the circuits 7, 8 and 9.
  • the purpose of the broken arrow 40 is to show that during testing of the adder 6, when only adder 6 is being operated in a conventional manner under the control of the control block 12, the circuits 4 and 5 upstream of the adder 6 are rendered transparent to a test pattern applied to the data buses represented by the arrow 30 under the control of the control blocks 10 and 11.
  • the purpose of the broken arrow 41 is to show that during testing of the adder 6, the circuits 7-9 downstream of the adder 6 are rendered transparent to the test results resulting from the testing of the adder 6 which are applied to the data bus represented by the arrow 33 under the control of the control blocks 13-15.
  • control blocks 10-15 there is provided, in addition to conventional instruction decoding circuitry which is used for causing a circuit controlled thereby to operate in a conventional manner, simple test instruction decoding circuitry for generating a control signal PASS A to cause the circuit to operate in either a conventional manner or to pass data transparently.
  • an N-bit combinatorial binary multiplier 40 having a plurality of inputs A N-1 -Aand B N-1 -B o for receiving a pair of N-bit operands A and B on the bus 30, and a plurality of data outputs F 2N - 1 -F o for providing an output operand F on the bus 31. Coupled in series with each of the inputs B N - 1 -B o there is provided a pair of pass gates 41 and 42.
  • Each of the pass gates 41 is provided with an input for receiving one of the bits of the operand B, a first control signal input coupled through an inverter 43 to the control signal bus 20 and a second inverted control signal input coupled directly to the control signal bus 20.
  • Each of the pass gates 42 except for the pass gate coupled to input B a , is provided with an input for receiving a logical 0.
  • the pass gate 42 coupled to the input B o is provided with an input for receiving a logical 1.
  • Each of the pass gates 42 is provided with a first control signal input which is coupled directly to the control signal bus 20 and a second inverted control signal input which is coupled through the inverter 43 to the control signal bus 20.
  • the control block 10 when the multipler 4 is to be tested, the control block 10 generates a PASS A control signal on the bus 20 in response to a test instruction.
  • the PASS A control signal causes the pass gates 41 to pass the bits BN., -B o of the operand B to the multiplier 40 so that the operands A and B are processed in the multipler 40 in a conventional manner.
  • the control block 10 During the testing of other circuits in the circuit 1 in response to another test instruction, the control block 10 generates a PASS A control signal on the bus 20 in response to the latter instruction.
  • the control signal PASS A causes the pass gates 42 to pass logical 0's to the inputs B N . 1 -B, and a logical 1 to input B o .
  • the operand A is multiplied by the operand B which now has a value of unity, thus, in effect rendering the multiplier 40 transparent to the operand A. That is, the operand A, which will comprise a test pattern for a downstream circuit, will be transferred from the input data bus 30 to the output data bus 31 without modification.
  • an N-bit combinatorial binary adder 50 having a plurality of inputs A N-1 -A o and B N-1 -B o for receiving a pair of N-bit operands A and B on the bus 32, a carry-in input C, N , a carry-out output C OUT , and a plurality of data outputs F N-1 , -F o for providing an output operand F on the bus 33. Coupled in series with each of the inputs B N-1 , -B o and C IN there is provided a pair of pass gates 51 and 52.
  • Each of the pass gates 51 is provided with an input for receiving one of the bits of the operand B, a first control signal input coupled through an inverter 53 to the control bus 22 and a second inverted control signal input coupled directly to the control signal bus 22.
  • Each of the pass gates 52 is provided with an input for receiving a logical 0, a first control signal input which is coupled directly to the control signal bus 22 and a second inverted control signal input coupled to the control signal bus 22 through the inverter 53.
  • control block 12 In operation, when the adder 50 is to be tested, the control block 12 generates a PASS A control signal on the bus 22 in response to a test instruction.
  • the control signal PASS A causes the pass gates 51 to pass the bits B N-1 , -B o of the operand B and C IN to the adder 50 so that the operands A and B are processed in the adder 50 in a conventional manner.
  • the control block 12 During the testing of the other circuits in the circuit 1 in response to another test instruction, the control block 12 generates a PASS A control signal on the bus 22 in response to the latter test instruction.
  • the control signal PASS A causes the pass gates 52 to pass logical 0's to the inputs B N - 1 -B. and C,N. Thereafter, the logical 0's are added to operand A in a conventional manner, thus in effect, rendering the adder 50 transparent to the operand A. That is, the operand A, which will comprise a test pattern for a downstream circuit or the test results from an upstream circuit, will be transferred from the input data bus 32 to the output data bus 33 without modification.
  • an N-bit, multilevel shifter 60 having a plurality of inputs A, -A. for receiving an 8-bit operand A on the data input bus 31 and a plurality of outputs coupled to the output bus 32.
  • This shifter 60 is described as being 8 bits wide for ease of illustration, but the discussion that follows applies equally well to shifters of arbitrary width.
  • the shifter 60 there is provided a plurality of 2:1 multiplexers 161-184.
  • the multiplexers 161-184 are arranged in three rows designated levels 1, 2 and 3.
  • a plurality of control signal buses 80-82 are coupled to each of the multiplexers in the levels 1, 2 and 3, respectively, for selectively coupling one of the two inputs of each multiplexer and its output.
  • the inputs of each of the multiplexers 161-184 are designated with a logical 1 and 0.
  • a conventional shifter control circuit 90 In the control block 11, there is provided a conventional shifter control circuit 90, a conventional test instruction decoding circuit 91 and a plurality of AND gates 92, 93 and 94.
  • the inputs of the circuits 90 and 91 are coupled to the instruction bus 26.
  • the outputs of the circuit 90 are coupled to a first input of the AND gates 92-94.
  • the outputs of the circuit 91 are coupled to an inverting input of the AND gates 92-94.
  • the outputs of the AND gates are coupled to the control signal buses 80-82, respectively.
  • the circuit 91 in the control block 11 When the shifter 60 is to be tested, the circuit 91 in the control block 11 generates a PASS A control signal which enables the AND gates 92-94 and the circuit 90 outputs a shift control signal in response to a test instruction. If the shift control signal calls for shifting the input 7 places to the right, a logical 1 will be placed on the control buses 80-82 by the circuit 90 causing the input 1 of all of the multiplexers 161-184 to be coupled to their output. Under these conditions, an input of A, 0, 1, 0, 0, 0, 0, 0 on the bus 31 will appear on the bus 32 as OOOOOOOA, as shown in Fig. 6.
  • circuit 91 During the testing of the other circuits in the circuit 1 in response to another test instruction, circuit 91 outputs a PASS A control signal which disables the AND gates 92-94.
  • the resulting logical 0 on the control signal buses 80-82 couples the input 0 of the multiplexers to their output rendering the shifter 60 transparent and causing the operand A 7 -A o on the bus 31, which may be a test pattern for a downstream circuit or test results from an upstream circuit, to appear on the bus 32 without modification.
  • shifters 7 and 9 of Fig. 1 it should be noted that the apparatus described above for selectively rendering the shifter 5 transparent is also used for selectively rendering the shifters 7 and 9 transparent. Of course, appropriate modifications should be made if the number of levels in shifters 7 and 9 are more or less than three.
  • the function blocks 4-9 are tested in sequence using a test pattern specially designed for that purpose beginning with the multiplier 4. As each of the function blocks is checked and found to be free of faults, it is rendered transparent to a test pattern specially designed for testing the next and succeeding function blocks in the sequence.
  • circuit 1 of Fig. 1 and the apparatus of Figs. 2-5 are useful for detecting faults in deeply buried logic circuits. It should be noted, however, that because the circuits downstream of a circuit under test may be faulty and thereby affect the test results from an upstream circuit even though control signals are generated for rendering these circuits transparent, it is not possible to reliably isolate a fault which has been detected in the circuit 1.
  • Figs. 7-10 there are shown two modifications of the apparatus of Fig. 1 which may be used for isolating a fault to a specific function block regardless of how deeply buried the function block is in the logic circuit.
  • Figs. 7-10 there are shown two modifications of the apparatus of Fig. 1 which may be used for isolating a fault to a specific function block regardless of how deeply buried the function block is in the logic circuit.
  • all circuits which are the same or substantially the same as the circuits of Fig. 1 will be identified in Figs. 7-10 using the same numerical designators.
  • a plurality of control blocks 10A-15A a plurality of function blocks 4-9 which are identical to function blocks 4-9 of Fig. 1, and a plurality of pass gates 100-105.
  • control block 10A-15A there is provided a control circuit, a test instruction decoder and a plurality of gates for controlling the operation of the function blocks 4-9 as described above with respect to Figs. 1-6 and the pass gates 100-105.
  • control block 11 A there is provided a control shifter circuit 90, and a plurality of AND gates 92-94 which are identical to and function in the same manner as the circuit 90 and gates 92-94 of Fig. 4, a test instruction decoder 91 A and an AND gate 95.
  • the decoder 91A is identical to the circuit 91 of Fig. 4 except that an additional output is provided for providing a test control signal TEST.
  • the control signal PASS A is coupled to an inverted input and the control signal TEST is coupled to a non-inverted input of the AND gate 95.
  • the output of the AND gate 95 is coupled to the control signal line 21 A for controlling the pass gate 101.
  • the AND gate 95 of Fig. 8 is replaced by an OR gate 96 having a pair of inverted inputs for receiving the control signals PASS A and TEST.
  • the output of OR gate 96 is coupled to control signal line 25A for controlling pass gate 105.
  • control blocks for the multiplier 4, and adders 6 and 8 will comprise an arrangement of gates consistent with the required control signals as described above with respect to Figs. 2 and 3.
  • the inputs of the pass gates 100-105 are coupled to data buses 31-36, respectively.
  • the ouputs of the pass gates 100-105 are coupled to a results bus 106.
  • the control signal inputs of the pass gates 100-105 are coupled to the control signal buses 20-25, respectively.
  • the pass gates 100-104 are enabled by a control signal corresponding to PASS A * TEST and pass gate 105 are enabled by a control signal corresponding to TEST + PSS A
  • each of the function blocks of the apparatus of Fig. 7 is preferably tested in sequence beginning with the multiplier 4 and that the results of each test are transmitted to a test evaluation circuit (not shown) via the results bus 106.
  • the function block tested Upon completion of a test, the function block tested is rendered transparent and the next function block in the sequence is tested. Since the results of each test bypass the untested downstream function blocks, faults in the downstream function blocks will not affect the results of the test. Consequently, faults in the apparatus of Fig. 7 are readily and reliably isolated.
  • a plurality of control blocks 10B-15B a plurality of function blocks 4-9, which are identical to function blocks 4-9 of Fig. 1, and a plurality of 2:1 multiplexers 110-114.
  • Each of the multiplexers 110-114 have a first input coupled to the output of the function block upstream therefrom, a second input coupled to a test pattern input bus 115, an output coupled to the input of the function block downstream therefrom, and a control signal input coupled to the control signal bus of the downstream function block.
  • the circuit used for generating the control signal PASS A * TEST described above with respect to the apparatus of Fig. 8 is also used for generating the control signals for selecting the inputs 21 B-25B of the multiplexers 110-114.
  • the multiplexer immediately upstream therefrom in the embodiment of Fig. 10 couples its second input from the test pattern bus 115 to its output.
  • the control signal PASS A * TEST is inactive, the first input of the multiplexer coupled to the upstream function block is coupled to its output.
  • the circuit 1 of Fig. 8 is operable in a normal mode and in a test mode.
  • the control blocks 10-15 in response to a normal instruction, enable the first input of the multiplexers 110-114 to allow the function blocks 5-9 to operate on data applied to their inputs in a normal manner under the control of the normal instruction.
  • test block 9 In the test mode, the function blocks described above with respect to the circuits of Figs. 1 and 7 are tested in a reverse order. That is, to begin a test of the circuit 1, a test pattern is provided by means of the test pattern input bus 115 and the second input of the multiplexer 114 to the last function block in the sequence, i.e. shifter 9. After the function block 9 has been tested and found free of defaults another test instruction is applied to the control blocks 10-15. This test instruction enables an appropriate test pattern to be passed by means of the test pattern input bus 115 through the second input of the multiplexer 113 to the inputs of the adder 8. This causes the adder 8 to operate on the test pattern in a normal manner and at the same renders the downstream function block 9 transparent to the results of the test such that the test results are transferred through the function block 9 without modification.
  • Each of the function blocks in the sequence are tested in the above described manner such that all function blocks downstream from the function block being tested are rendered transparent while the function block being tested is caused to operate on a test pattern applied to its inputs by means of the test pattern input bus 115 and the 2:1 multiplexer coupled thereto in a normal manner.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
EP86309560A 1985-12-17 1986-12-09 Dispositif de circuit avec test incorporé pour logique combinatoire Withdrawn EP0228207A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US81112885A 1985-12-17 1985-12-17
US811128 1985-12-17

Publications (2)

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EP0228207A2 true EP0228207A2 (fr) 1987-07-08
EP0228207A3 EP0228207A3 (fr) 1989-03-22

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JP (1) JPS62162982A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2668011A1 (fr) * 1990-10-11 1992-04-17 Telecommunications Sa Systeme adaptatif de traitement d'image, avec epreuve de bon fonctionnement en temps reel.

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58207152A (ja) * 1982-05-28 1983-12-02 Nec Corp パイプライン演算装置テスト方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2668011A1 (fr) * 1990-10-11 1992-04-17 Telecommunications Sa Systeme adaptatif de traitement d'image, avec epreuve de bon fonctionnement en temps reel.

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EP0228207A3 (fr) 1989-03-22
JPS62162982A (ja) 1987-07-18

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