Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
  • H04L27/08—Amplitude regulation arrangements
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
  • H04L25/067—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability

Definitions

• the present invention relates to an automatic drift control circuit which automatically corrects the drift of multi-level demodulated signals.
• the demodulated signal is amplified up to the spe­cified level by an amplifier, then input to an A/D converter through an adder and then converted to a digital signal consisting of a plurality of bits.
• the data of 4-bit structure can be obtained since the I and Q channels respectively become the data of 16-level.
• the one bit lower than such data namely the 5th bit from the most significant bit (MSB) indicates whether or not the input signal is higher or lower than the decided level among the specified 16 levels. Therefore, it is used as the error signal and it is then applied to an integrator for integration.
• the integrated output therefrom is applied to said adder and thereby the drift of demodulated signal is corrected.
• the error signals of signals in each decision level are integrated and then added to the demodulated signal.
• the integrated output used by selecting the error signal of the signal in the specified range including at least the signals higher than the most significant bit or lower than the least significant bit is added to the demodulated signal.
• Fig. 1 is a basic block diagram of the present invention.
• a multi-level signal obtained, for example, by demodulating the QAM signal is input to the analog-to-digital (A/D) converter 2 through an adder 1.
• the A/D converter 2 converts the multi-level signal input into the digital signal corresponding to the level thereof and outputs it as the data and simultaneously outputs the specified bits including the bits lower than the data to an error signal selecting circuit 3 and a monitoring circuit 4.
• the error signal selecting circuit 3 always outputs error signal, only in the normal condition, corresponding to the decision condition signal obtained from the monitoring circuit 4 or error signal, in the false condition, only when the specified level is decided by the A/D converter 2.
• the error signal selecting circuit 3 selects and outputs the error signal which seems to be correct under the false condition.
• the integrator 5 integrates error signals from the error signal selecting circuit 3 and outputs it to the adder 1 as the drift control signal.
• the adder 1 adds the integrated signal to multi-level signal so that drift of multi-level signal may be corrected.
• Fig. 2 is a block diagram of an embodiment which may be used to any of the 16-level signals of I and Q channels obtained by demodulating the 256-level QAMaa signal.
• the 16-level signal is input to the A/D converter 2 through the adder 1.
• Fig. 3 and Fig. 4 indicate decisions of the A/D converter 2.
• the A/D con­verter 2 outputs the data D1-D4 of 4 bits which indicate to which level among 16 levels indicated by X in Fig. 3 the input signal corresponds and also outputs, as shown in Fig. 4, D5, D6 of 2 bits which is lower than the data which decides further detail the range (a, b, c....) decided to each level into four ranges.
• the horizontal line indicates the threshold level of each bit.
• the bit D5 as the error signal becomes 1, allowing the judgement that positive drift is generat­ed.
• the bit D5 becomes 0, and erroneous error signal which indicates that negative drift is generated as output.
• the signal is within the range A higher than the highest level among 16 levels and in the range D lower than the lowest level, there should be no signal at the outside of such levels. Accordingly, correct error signal can be obtained. Thereby even when the decision condition is not good, the correct drift control can be realized by executing the drift control through the selection of the error signal obtained when the input signal to the A/D converter 2 is within such range.
• the error signal is selected not only in the ranges A and D but also in the center ranges B and C.
• Result of decision condition can be judged as follows.
• the range where the bits D5 and D6 take the same value, namely the exclusive NOR of D5 and D6 becomes 1 is far from the correct level. Therefore, result of decision condition can be judged from the fact that the rate of the input signal to enter such range is higher or lower than a certain reference value.
• the logic circuit 31 consisting of an AND circuit 311, a NOR circuit 312, an OR circuit 313 and an AND circuit 314 outputs the pulse synchronized with the clock to the A/D converter when the input signal enters the range of A-D of Fig. 3.
• the flip-flop 32 holds the error signal D5 when such pulse is generated.
• the logic circuit consisting of the AND circuits 33, 34, inverter 35 and OR circuit 36 selects and outputs the error signal D5 without passing the flip-flop 32 and the error signal having been held by the flip-flop 32, in accordance with the decision condition signal from the monitoring circuit 4.
• the circuits 31-36 correspond to the error signal selecting circuit 3 of Fig. 1.
• the exlusive NOR 41 outputs the signal indicated by D5 D6 in Fig. 4 as the pseudo error signal and the integrator 42 integrates such pseudo error signal and outputs pseudo error rate.
• This pseudo error rate is compared with the reference value V ref in the comparator 43. If it is lower than such reference value, decision condition is judged good but if it is higher than the reference value, decision condition is judged bad. The decision condition signal is then output to the error signal selecting circuit.
• the circuits 41- 43 correspond to the monitoring circuit 4 of Fig. 1.
• the auto­matic gain control is also known in addition to the automatic drift control.
• the gain of anmplfier in the preceding stage of the A/D converter can be judged as too large and in case polarity of input signal is different from that of error signal, such gain is judged as too small. Therefore, the gain of amplifier can be controlled in accordance with an integrated value by integrating the exclusive OR of the first bit (D1) which indicates the polarity among the outputs of A/D converter and error signal (D5 in the case of 16-level signal) as the gain error signal.
• D1 exclusive OR of the first bit
• D5 error signal
• the gain error signal is selected and can be conrolled when the decision condition becomes bad as in the case of the drift control.
• Fig. 5 is a block diagram of the second embodiment of the present invention.
• the adder 1, A/D converter 2, error signal selecting circuit 3, monitor­ing circuit 4 and integrator 5 are similar to those of Fig. 2.
• a variable gain amplifier 6 is provided at the preceding stage of the adder 1 and the output level is controlled to the constant value by the gain control signal described later.
• D1 and D5 among the outputs of A/D converter 2 are input to a gain error signal selecting circuit 7.
• the exclusive OR circuit 71 generates the gain error signal from the exclusive OR of D1 and D5.
• the logic circuit consisting of the flip-flop 72, AND circuits 73, 74, inverter 75 and OR circuit 76 selects and outputs the gain error signal to the integrator with the operations similar to that of the circuits 32, 36 in the error signal selecting circuit 3 on the basis of the output of logic circuit 31 in the error signal selecting circuit 3 and the decision condition signal from the monitoring circuit 4.
• the integrator 8 integrates the gain error signal and outputs it to the variable gain amplifier as the gain control signal. Thereby, gain control can be executed in accordance with the decision condition.

Landscapes

• Engineering & Computer Science (AREA)
• Computer Networks & Wireless Communication (AREA)
• Signal Processing (AREA)
• Power Engineering (AREA)
• Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
• Analogue/Digital Conversion (AREA)
• Dc Digital Transmission (AREA)

Applications Claiming Priority (2)

Publications (3)

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• 1986
  • 1986-06-27 JP JP61149616A patent/JPS637024A/ja active Granted
• 1987
  • 1987-06-26 EP EP87109203A patent/EP0254877B1/de not_active Expired - Lifetime
  • 1987-06-26 DE DE87109203T patent/DE3787231T2/de not_active Expired - Fee Related
  • 1987-06-26 CA CA000540666A patent/CA1271989A/en not_active Expired
  • 1987-06-29 US US07/066,960 patent/US4860010A/en not_active Expired - Fee Related

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