Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2851—Testing of integrated circuits [IC]
  • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
  • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's

Definitions

• the present invention concerns the manufacture of integrated circuits and in particular is addressed to the problem of testing circuits for conformity to a defined inherent performance (i.e. speed) specification.
• each replica circuit produced on a semiconductor wafer will differ with the location of that circuit relative *to the wafer and will vary also in a stochastic manner from wafer to wafer. It is thus necessary to provide test techniques capable of measuring inherent performance and to use the same to enable the selection of those replica circuits that are in conformity to specification. Further, the measured inherent performance can be correlated with the model derived in CAD (computer aided design) work and to parameters of the process used to fabricate the circuits enabling changes to be made to the model and/or the process, to exercise tighter control of the manufacturing specification.
• CAD computer aided design
• FIG. 1 This depicts a section of a semiconductor wafer 1 on which a large number of replica circuits 3 have been produced.
• the array of replica circuits 3 includes a small number of test-dedicated circuits 5 substituted at selected array sites.
• the number of test-dedicated circuits 5 is usually small, typically five or so per wafer. Probes are then applied to these test circuits 5 and the inherent performance at the substitution sample sites measured. The inherent performance of the surrounding replica circuits 3 is then deduced on the basis of statistical analysis and the chips selected accordingly.
• test-dedicated circuits 5 r "drop-ins" 5a_ have been positioned not at substitute sites but at intermediate positions, lying thus in the scribe lane areas of the wafer 1 (See Figure 2).
• the present invention is intended as a remedy to the problem aforesaid.
• each replica includes, in addition to a device function circuit, a test-dedicated sub-circuit, this sub-circuit being capable of generating a test measurable that is dependent upon inherent performance.
• test-dedicated sub-circuits as aforesaid, wafer probe tests may be applied and chips selected accordingly.
• the circuit design may provide that in subsequent packaging the sub-circuit is connected to device pins, and performance and function testing (and eventual selection) carried out thereafter.
• the test measurable may be analogue or may be digital and may be chosen thus to suit the test technique adopted. Examples of the measurable include a delay time or a frequency (both analogue), or a .TRUE./.FALSE, logic variable.
• Figures 1 and 2 illustrate in plan view, wafer sections adapted for known sample performance testing
• Figure 3 is a plan view of a wafer section modified for testing in accordance with this invention. and, inset, an enlarged view of a replica circuit;
• Figures 4 to 6 are block schematic diagrams of test dedicated sub-circuits suitable for inclusion in the wafer construction shown in the preceding Figure.
• Each replica circuit 3a_ includes, as usual, the device function circuit and may include other test-facility, e.g. logic test, sub-circuits.
• a distinguishing feature of the replica circuit 3a_ is the inclusion of a • performance' test-dedicated sub-circuit 5b.
• the design of the sub-circuit 5b_ is not critical provided that it will generate a performance related parameter (i.e. the measurable).
• the form of this sub-circuit 5b thus may be optimised to suit the test strategy of the manufacturer. Possible implementations of this sub-circuit 5b_ are illustrated in Figures 4 to 6 and will now be described.
• a simple delay measurement sub-circuit 5b is illustrated In Figure 4.
• This circuit 5b_ consists of a chain of inverters I ⁇ _, 12' ••• I n each with suitable impedance loading C ⁇ , C2'....C n (The impedance values here are chosen so as to limit the average interconnect loading typical of the device function circuit).
• an interrogation pulse is applied to the sub-circuit 5b input I/P and the propagation delay to output O/P measured.
• a large number n of inverters would be incorporated in the chain. Twenty or more inverters, typically, might be used. Absolute time delay measurement will in general be less than ideal as delays will be inserted by the connected apparatus. Differential measurement techniques would be preferred therefore. More accurate delay measurements thus may be achieved using by-pass or alternative length switching techniques.
• FIG. 5b_ A second of these implementations, a ring oscillator 5b' is illustrated in Figure 5.
• the number n of inverters I would normally be in excess of 10, and odd.
• the output measurable in this case, is a frequency which is, in turn, a function of the individual gate delay.
• the sub-circuit 5b_' may also include frequency division circuitry (not shown) to facilitate measurement.
• An "OR” or an "AND” gate may be substituted at one of the inverter gate positions. This substitution will allow oscillation to be stopped, to prevent circuit noise and to reduce integrated circuit power consumption.
• a frequency meter 5b_ is illustrated in Figure 6.
• This sub-circuit is particularly suited for use in conjunction with a digital tester.
• this sub-circuit 5b" thus includes circuitry to enable interfacing to digital testers.
• the output of the oscillator 5b' is fed to a counter 7 and oscillator stop and counter reset functions are controlled via an inverter 9 connected at sub-circuit input I/P.
• Input signal and counter output are referred to a pulse conincidence detector. Under test, a "Go" signal starts the oscillator and the oscillator cycles are counted.
• the width of the "Go" signal pulse can be varied systematically to allow measurement of ring oscillator frequency or to check that such frequency lies within specified limits.

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• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Tests Of Electronic Circuits (AREA)
• Testing Of Individual Semiconductor Devices (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)

Applications Claiming Priority (2)

Publications (1)

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ID=10601697

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• 1986
  • 1986-07-25 GB GB868618210A patent/GB8618210D0/en active Pending
• 1987
  • 1987-07-25 JP JP62504447A patent/JPH01500927A/ja active Pending
  • 1987-07-25 WO PCT/GB1987/000530 patent/WO1988001060A1/en not_active Ceased
  • 1987-07-25 EP EP19870904906 patent/EP0277167A1/de not_active Withdrawn

Non-Patent Citations (1)

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