EP0280582A2 - Systèmes graphiques à ordinateur - Google Patents

Systèmes graphiques à ordinateur Download PDF

Info

Publication number
EP0280582A2
EP0280582A2 EP88301742A EP88301742A EP0280582A2 EP 0280582 A2 EP0280582 A2 EP 0280582A2 EP 88301742 A EP88301742 A EP 88301742A EP 88301742 A EP88301742 A EP 88301742A EP 0280582 A2 EP0280582 A2 EP 0280582A2
Authority
EP
European Patent Office
Prior art keywords
viewport
memory
display
controller
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88301742A
Other languages
German (de)
English (en)
Other versions
EP0280582B1 (fr
EP0280582A3 (en
Inventor
David John Phillips
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Axiom Innovation Ltd
Original Assignee
Axiom Innovation Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB878704653A external-priority patent/GB8704653D0/en
Priority claimed from GB878727119A external-priority patent/GB8727119D0/en
Priority claimed from GB888801012A external-priority patent/GB8801012D0/en
Application filed by Axiom Innovation Ltd filed Critical Axiom Innovation Ltd
Publication of EP0280582A2 publication Critical patent/EP0280582A2/fr
Publication of EP0280582A3 publication Critical patent/EP0280582A3/en
Application granted granted Critical
Publication of EP0280582B1 publication Critical patent/EP0280582B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/14—Display of multiple viewports

Definitions

  • the present invention generally concerns improvements in or relating to computer graphics systems, and more particularly concerns window management systems and windowing devices for use with computer graphics workstations.
  • images to be displayed on a display screen are drawn into a reserved block of memory, sometimes called a frame buffer, within the system.
  • Memory locations within the frame buffer have a one-to-one correspondence with display locations on the display screen and image data is read out sequentially from the frame buffer via video generation circuitry in accordance with the instantaneous address of the scanning beam on the display screen.
  • This arrangement is adequate so long as there is no requirement to move complex multiple images rapidly around the display screen.
  • the requirements of graphics systems users have become more sophisticated there has been a corresponding increase in demand for complex images to be displayable and quickly relocatable on a screen.
  • the position and size of a displayed image may be controlled by the user, for example by way of a mouse which provides user determined positional and dimensional information.
  • a mouse can be moved swiftly across a table top by the user for repositioning a displayed image
  • the image is commonly unable to keep up with the movement of the mouse. This is because of the one-to-one relationship which exists between the frame buffer and the display screen locations and because of the corresponding requirement that, in order to move an image from one part of the screen to another, it is necessary to copy the entire image data to new locations in memory and to replace the image data at the original memory locations by data corresponding to whatever was visually behind the image on the screen, whether it be a plain background or part of another image.
  • Hardware windowing is a method of moving images around a display screen without the need to rearrange large blocks of image data within the memory. In principle the idea is simple. Image data in the frame buffer is transferred to the video generation circuitry in a controlled sequence such that any given area of memory, hereinafter referred to as a window, can be displayed at any chosen location on the display screen, such location hereinafter being referred to as a viewport.
  • Hardware windowing is distinct from conventional serialised approaches wherein scanning through the display memory is effected sequentially as the display screen is scanned, since in hardware windowing a dedicated circuit is used to extract image data from the memory by jumping from place to place in memory as required. It then becomes easy to move any image instantly from one place to another, simply by specifying where it is to be displayed next.
  • the present invention resides both in the concept of providing a multi-planar display memory wherein each plane of the memory has its own viewport controller for flexibly mapping windows from that memory plane to viewports of the display, and in the novel means hereinafter described for realising such a viewport controller which offers considerable advantages over the prior art.
  • each plane of the memory has its own viewport controller for flexibly mapping windows from that memory plane to viewports of the display, and in the novel means hereinafter described for realising such a viewport controller which offers considerable advantages over the prior art.
  • the present invention overcomes all of the above-mentioned problems of prior art computer graphics systems, and uniquely provides a number of hitherto unachievable benefits to the art of window management.
  • the exemplary windowing device in accordance with the present invention which is described hereinafter is configured as a single VLSI component designed for use with planar display memory and to take advantage of the special capabilities of modern VRAM memory chips. It is modular and cascadable and can be used with almost any planar VRAM raster scan graphics system. It provides a means by which multiple windows can be displayed in viewports at high resolution with each viewport and window sized and located with perfect, single-pixel resolution. It handles overlapping viewports automatically and allows them to appear transparent or opaque relative to one another as required.
  • a single windowing device as hereinafter described comprises a pluraity of viewport controllers each capable of mapping a plurality of 1-bit windows from a respective plane of a multi-planar memory to viewports on the screen.
  • each windowing device comprises four viewport controllers, each of which controls the manipulation of up to four windows on a single image plane.
  • a plurality of such windowing devices can be cascaded to address any number of memory planes and enable any number of windows to be displayed in an arrangement which will hereinafter be referred to as a windowing device array.
  • This highly modular architecture allows price and performance to be tailored precisely to the user's needs, in systems ranging from PCs to top-end graphics workstations.
  • the windowing device treats the display memory as a collection of superimposed bit planes.
  • a 1-bit window is any rectangular array of bits on one plane
  • an n-bit window is a block of image data composed of n superimposed 1-bit windows of equal size and each drawn from a dlfferent plane.
  • Each 1-bit window may be taken from any arbitrary location in its memory plane and displayed in any viewport location, and any combination of n planes is allowed.
  • the conventional concept of a window corresponds in the system of the present invention to the restricted case of an n-bit window in which all the 1-bit components are at the same planar address (vertically aligned) and n is equal to the number of planes in the system.
  • each 1-bit window is assigned a priority by the user, the same priority being assigned to all n planar components of an n-bit window.
  • a higher priority window is arranged to obscure a lower priority window. This obscuring is a visual effect only and does not involve the manipulation of the image data in memory, and the obscured area re-appears automatically and instantaneously when the overlapping viewport is moved or when the priorities are suitably altered.
  • Equal priority windows from different planes are advantageously arranged to overlap transparently, and colour mixing effects within the overlap area can be determined at the choice of the user by appropriate setting up of a user programmable colour look-up table.
  • a viewport of any shape can readily be created by using a 1-bit window as a mask. Double- (or multiple-) buffering of animated images is easily achieved by mapping windows to viewports sequentially; only the areas of the display memory which actually contain the buffered images are affected.
  • window-viewport assignments which are a set of absolute and relative co-ordinates on the display and in the memory.
  • This simple method of defining windows and viewports makes programming of a graphics system in accordance with the present invention very straightforward, and abolishes the cumbersome software operations such as strip decomposition and Boolean computation of transparency effects which hinder other systems.
  • the invention thus provides an extremely versatile, powerful system which enables complex visual effects to be produced effortlessly while making very efficient use of memory. All window boundary clipping and transparency effects are carried out automatically, in real time, with no user intervention.
  • the windowing device is effectively invisible to the drawing processor (or whatever other device is being used to create bit maps in memory) and in general drawing proceeds at close to full speed under most circumstances even while the images being drawn are being moved all over the screen.
  • the bus bandwidth required to create, relocate or remove a window is so small that the system overhead that this represents is in general negligible.
  • windowing device array there is no theoretical limit to the number of windowing devices and therefore viewport controllers that a windowing device array can contain. It follows that there is no theoretical limit to the number of planes, windows and viewports which can be controlled by such an array.
  • means can be provided for linking as many of the devices together in parallel as may be required in order to achieve the desired number of displayable viewports.
  • a conventional raster graphics system might comprise a host computer 1 which provides overall management of the system, a display memory 2 for storing image data, a raster scan display screen 3 for displaying viewports, and a serialiser 4 which steps in strict progression through the display memory in raster fashion and reads data serially out from the memory as the display spot scans the display screen.
  • the resulting display is a one-to-one mapping of the image data onto the display screen so that images appear on the screen in the same relative positions as they are stored in memory.
  • the hardware windowing system of Figure 1B allows selected areas of memory to be displayed instantly at any desired display position.
  • the hardware circuit 5 Under control of the host computer, the hardware circuit 5 performs the function of selectively extracting portions of image data from any location in the display memory 2 and transferring it for display at any desired location on the display screen 3 so that any given area of memory can be displayed at any chosen location on the screen.
  • the host computer 1 can be arranged to draw image data directly into the display memory, or it can be used to control a separate drawing processor, not shown, which provides this function.
  • the display memory can contain information relating to a number of different images, shown in the Figures exemplarily as a solid chevron 6, a bounded-W 7, and a chequered ball 8.
  • the data representative of these images can be stored in different areas of a single memory plane, or can be stored in different memory planes, or with some of the image data in one plane and other image data in one or more other planes.
  • the windowing device 5 of the present invention under supervisory control of the host computer 1 which provides to the windowing device 5 window-viewport mapping assignments including information representative of the locations In memory where image data is stored in a window of the memory and the viewport locations whereat such Image data is desired to be displayed and representative also of the priority to be accorded to the respective viewports for enabling overlapping viewports to be readily handled, extracts from the display memory 2 only image data appropriate to the required display and passes it to the display screen 3 for display as the information is required.
  • the relative locations of the three images 6, 7 and 8 on the display screen 3 need bear no direct correspondence with the relative locations of the corresponding image data in the display memory 2 and can be varied as desired.
  • image data of the three images has in the example of Figure 1 B been read from the memory and displayed in a manner which causes portions of them to overlap on the display screen, the chevron 6 opaquely overlapping a portion of the chequered ball 8 and the bounded-W 7 and chequered ball 8 transparently sharing a common area of overlap.
  • the windowing device 18 of the present invention provides the logic and other functions required to ensure that only the required image data is read from the display memory and transferred to the display screen for display and that, in a case where images overlap transparently, overlapping data from the images is combined before being displayed on the display screen.
  • Figure 2 shows further examples of how the present invention enables image data stored in the display memory to be selectively extracted from memory and flexibly displayed on the display screen.
  • overlapping viewports are handled by storing image data in multiple memory planes and assigning priorities to window-viewport mapping Instructions so that data is automatically read from memory in accordance with the priority assignments and when displayed automatically provides the desired overlapping display effect.
  • the display 9 shown in Figure 2 is the same as that described with reference to Figure 1B and shows the features of opaque and transparent overlapping previously mentioned herein, the chevron 6 opaquely overlapping the chequered ball 8 which in turn transparently overlaps the bounded-W 7, such a display being obtainable in accordance with the teachings of the present invention by storing the bounded-W and the chevron in one display memory plane and the ball in another and setting the priority of the chevron at a high value and the priorities of the bounded-W and the ball at the same lower priority.
  • equal priority images read from different memory planes overlap transparently in the system of the invention.
  • the box 7a is overlapped and partially obscured by the chequered ball 8 and the W 7b overlies and partially obscures both the box 7a and the chequered ball 8, whilst the chevron 6 opaquely overlaps both the box 7a and the ball 8.
  • the display 10 of Figure 2 might for example be obtained by storing image data representative of the chevron, the W, the ball and the box in different planes of a multi-planar memory and providing that the box has the lowest priority, the ball has a higher priority than the box but a lower priority than the W, and the chevron has a higher priority than either the box or the ball.
  • display effects additional to those obtained by allocation of display images to selected planes of the display memory and by allocation of viewport priorities can be obtained by suitably programming a colour look-up table to which the video signals extracted from memory are applied before they are displayed.
  • the windowing device 5 advantageously comprises four viewport controllers which share common areas of control and can each control up to four Independent viewports and four associated image windows held In a single memory plane.
  • a single windowing device 5 can thus control up to sixteen 1-bit windows held in four 1-bit deep memory planes to produce displays in up to sixteen viewports on a display screen.
  • Multi-bit windows consisting of superimposed bits In the four bit planes can likewise be managed.
  • the windowing device is adapted to be cascaded to form a windowing device array as aforementioned comprising a plurality of windowing devices arranged in parallel, and such an array can control the display of data from a large number of memory planes independently and can display up to four independent image windows from each plane of memory.
  • the invention Is not restricted to configuring the windowing device as comprising four viewport controllers, but by virtue of the use of VLSI technology a particularly advantageous chip configuration can be obtained with four viewport controllers on each chip without placing undue demands on the pin count and die size of the VLSI circuitry:
  • FIG. 3 there is shown therein a typical graphics system according to the present invention which incorporates a windowing device 5 comprising four Independently operable viewport controllers.
  • the windowing device 5 is adapted to be controlled by a host computer, not shown, via a host computer bus 11, and there is also provided a drawing processor 12 which draws or creates bit-maps In a planar video RAM 13 which is treated by the windowing device 5 as four superimposed bit planes each of which is individually associated with a specific one of the four viewport controllers within the windowing device.
  • the drawing processor may optionally be excluded from the system in which case the host computer may be linked directly to the video RAM 13 so that it can draw directly into the memory.
  • the planar video RAM or VRAM, is shown as comprising four independent memory planes 13a-13d, and each memory plane can contain image data drawn into it by the drawing processor 12 and is arranged to be accessed independently by a specific one of the four viewport controllers within the windowing device.
  • the viewport controllers operate to extract image data from the VRAM under control of the host computer and to transmit the extracted data to a user programmable colour look-up table and digital to analog converter (CLUT & DAC) 14 which control the display screen 3.
  • CLUT & DAC digital to analog converter
  • the components shown in Figure 3 are obtainable as standard off-the-shelf components from a wide range of suppliers.
  • the drawing processor 12 may be almost any processing device or system capable of creating image data in the form of bit-maps to be stored in the planar VRAM 13.
  • a particularly effective planar drawing processor in this respect is the QPDM manufactured by Advanced Micro Devices (UK) Limited.
  • the choice of VRAM 13 and of CLUT & DAC 14 is not limited to specific makes or models.
  • Figure 4 shows a functional block diagram of a windowing device 5 according to the invention, the device comprising four viewport controllers 15 only one of which is shown for the sake of clarity, together with functional blocks which are shared by all four viewport controllers within the windowing device, namely a counter 16 for synchronising the windowing device operation with the drawing processor and the raster display, a VRAM controller 17 responsive to the viewport controllers 15 for determining the extraction of image data from the VRAM 13, and global priority control logic 18 for controlling the overlapping display of viewports originating from memory planes controlled by different windowing devices of a windowing device array.
  • a counter 16 for synchronising the windowing device operation with the drawing processor and the raster display
  • VRAM controller 17 responsive to the viewport controllers 15 for determining the extraction of image data from the VRAM 13
  • global priority control logic 18 for controlling the overlapping display of viewports originating from memory planes controlled by different windowing devices of a windowing device array.
  • the viewport controller 15 is shown in Figure 4 decomposed into its major subunits, namely a register file 19, a VRAM setup list (VSL) 20, merge logic and video data buffer 21, video control logic 22 and planar priority control logic 23, and the functions and the detailed construction of these subunits will be described in the following, it being remembered at all times that the windowing device of Figure 4 does in fact comprise four such viewport controllers 15.
  • VSL VRAM setup list
  • each viewport controller In operation of each viewport controller, information identifying the locations in the VRAM display memory of the image windows and the viewport locations where the image windows are required to be displayed together with viewport priority information is downloaded into the register file 19 from the host computer via the host interface 24, it being recalled that each viewport controller 15 can control the display of up to four viewports.
  • the information downloaded into the register file 19 is used to create a VRAM setup list which describes the actions to be performed by the VRAM controller 17 in extracting image data from the VRAM for display.
  • the data output from the VRAM serial port is input a byte at a time to merge logic and video data buffer 21 which, under the control of information stored in the register file 19, shifts and merges the bytes of data which would each correspond to displays at a plurality of display pixels to achieve the required single pixel display accuracy before passing them to the video controller 22.
  • the video controller 22 accepts the merged data and outputs it under control of the priority controller 23 for display.
  • Video data is loaded from the VRAM into each of the four viewport controllers eight pixels at a time and is output to the display four pixels at a time, and the video controller takes care of this 8:4 multiplex operation; by virtue of this arrangement the maximum on-chip clock rate required is reduced to one quarter of the pixel rate, making the bandwidth required for high-resolution displays readily achievable using conventional CMOS fabrication.
  • the viewport priority information that is loaded into the register file 19 is utilized by the planar priority controller 23 to determine the display in overlapping viewports of image data extracted from that memory plane of the VRAM display memory which is associated with the respective viewport controller.
  • the global priority controller 18 co-operates with the four planar priority controllers 23 within the windowing device in order to determine which viewport data originating from the four memory planes controlled by the windowing device should be passed to the display for a given display location.
  • the global priority controller 18 also includes a priority bus interface which enables it to communicate over a priority bus 25 with other global priority controllers in similar windowing devices when several such windowing devices are connected in parallel to form a windowing device array as described hereinbefore.
  • the global priority controller thus has the capability to determine the display of overlapping viewports corresponding to image data derived from different viewport controllers whether or not these are contained within the same windowing device.
  • a handshake interface is provided between the VRAM controller 17 and the drawing processor 12 which requires the transmission between the VRAM controller and the drawing processor of video bus request ( VBR) and video bus grant ( VBG) control signals.
  • VBR video bus request
  • VBG video bus grant
  • Each viewport controller contains three first in first out (FIFO) buffers, namely a VRAM setup list FIFO (VSL FIFO) 26 which together with test logic and VRAM setup list (VSL) compiler 27 and offset adder 28 the functions whereof will be explained hereinafter makes up the VRAM setup list 20 of Figure 4, a data FIFO 29 corresponding to the buffer between the merge logic 21 and the video controller 22, and a priority FIFO 30 which buffers priority information from the register file 19 to the planar priority controller 23.
  • the three FIFO's taken together amount to less than 700 bits of buffering per viewport controller which is approximately one quarter of the storage that would be required with a serial line buffer approach.
  • the four viewport controllers in the windowing device operate independently and only interact at their output stages where their outputs are synchronised so that identically defined viewports in separate controllers overlap precisely on the display.
  • each of the four available window-viewport assignments is defined by data downloaded from the host computer and held in registers within the register file 19.
  • the window-viewport co-ordinate definition comprises:
  • the viewport Xi, Yi and X 2 , Y 2 co-ordinates define the screen locations of opposite corners of the viewport.
  • the offset co-ordinates X o , Y o are added to the viewport X 1 , Y i co-ordinates to provide the window start address in memory.
  • the viewport priorities are defined by a 3-bit priority word which enables priority levels from 0 to 7 to be achieved, though it will be appreciated that this is exemplary and that greater or lesser numbers of priority levels can be provided for as desired.
  • Figures 7A and 7B show respectively a possible arrangement of three 1-bit deep viewports V1, V2, V3 from a single memory plane where viewport V2 has been assigned a higher priority than viewport V1, and a scanline A-A of the display.
  • VSL compiler 27 determines the viewport priority hierarchy for the memory plane in question.
  • the VSL compiler makes no reference to the priorities of viewports on other planes.
  • Information loaded into the VSL FIFO 26 consists of an ordered sequence of entries, each entry being in the form (X e , V#, S, P) where X e is the X address at which the next visible viewport boundary occurs, V # is the number of the active viewport (1-4) at that boundary, S is a setup bit which signals whether or not a VRAM setup is required, that is to say whether the boundary in question is followed by window data (i.e. marks the start of a window) or by background (i.e. marks the end of a window), and P is a parity bit which signals whether VCOUNT is odd or even for the line in question.
  • the sequence of entries from the VSL compiler into the VSL FIFO would be as follows: where each X;(n) is the relevant X-co-ordinate obtained from the register file 42.
  • the scan line has effectively been divided into a number of data fields.
  • the first data field from the leftmost side of the display to X 1 (1), is formed of background or default data since there is no viewport in this section of display.
  • the second data field between X 1 (1) and X i (2), is formed of viewport V1 pixel data.
  • the third data field, from X i (2) to X 2 (2), can be broken down into two parts.
  • the first part from Xi (2) to X2(1) is common to both viewport V1 and viewport V2 but. since viewport V2 has a higher priority than viewport V1, the information associated with this part of the third field is exclusively viewport V2 pixel data.
  • the hardware assembles this list of entries from the VSL compiler into the VSL FIFO for the scan line A-A of Figure 7B by working through the X edges defined in the register file 42 in order from left to right across the scan line in a series of logical passes. On the first pass, the logic tests each viewport to determine whether Y 1 (n) ⁇ Y A-A ⁇ Y2(n)
  • viewport n is relevant to scanline A-A and identifies the relevant viewport which has the smallest value of X 1 (n), namely the viewport V1.
  • a flag-bit is set noting the fact that the left (Xl) edge of this viewport has been passed. If the viewport has the highest priority of all viewports active at the boundary location tested, and it is not already the current display viewport, then the four fields of data X e , V#, S and P above are loaded into the VSL FIFO 26.
  • the X 2 address of the viewport in question will be examined instead of the Xi address during future passes so that the right edge, as seen on the screen, rather than the left edge will next be tested.
  • a second flag-bit is set which prevents that viewport from being subject to any testing in subsequent passes. Further similar passes are now made, examining Xi or X 2 for each viewport or ignoring the viewport altogether as dictated by the set flag-bits. This continues until all viewports have been logically eliminated. In practice it is possible to accomplish the entire process of detecting viewports for a given scan line well within the time of a single scan line.
  • the contents of the VSL FIFO 26 is combined with offset data from the register file 19 and the result is used by the VRAM controller 17 to perform the correct sequence of VRAM setups for the scan line in question.
  • this process begins during the flyback period preceding scan line A-A.
  • the VRAM controller 17 is a finite state machine and only one such VRAM controller is provided in the windowing device 5. In a windowing device array. all the VRAM controllers run synchronously. During the line flyback time before line A-A, any entry in the VRAM setup list in VSL FIFO 26 will cause the VRAM controller 17 to request control of the VRAM address bus from the drawing processor by asserting the not-VBR (Video Bus Request) signal.
  • VBR Video Bus Request
  • VBG Video Bus Grant
  • the VRAM controller 17 sets up the VRAM serial ports on each memory plane to access data for the first viewport to appear from that memory plane. Once set up, each VRAM serial port is clocked until a number of words equal to the difference between successive values of X e have been output. The next setup operation is then performed.
  • the VRAM controller can simultaneously supply four setup addresses (one per memory plane). It determines which planes are set up on a particular cycle by controlling the not-RAS (Row Address Strobe) signal for each plane.
  • Image data is extracted from the VRAM in eight bit words and loaded into the merge logic 21.
  • the VRAM is organised in 16-bit words and a 16:8 multiplexing operation is performed by alternately output-enabling the VRAM making up the high and low bytes.
  • Data bytes output sequentially from the VRAM enter the merge logic 21 which, as is explained more fully below, shifts, masks and merges the data to single pixel resolution as specified by the values of the four bit quantities start-bit, stop-bit and offset-bit. These correspond to the least significant 4-bits of X i (n), X 2 (n) and X o (n) respectively, and define viewport boundaries and image offsets down to single pixel accuracy.
  • a viewport starts at bit 2 of display byte D1, and the user has decreed that bit 6 of memory pyte M1 should appear at this location.
  • These bit locations are defined by the bottom three bits of X e and X o . These are 2 and 4 respectively.
  • the merge logic must fetch image bytes and generate display bytes, masking off those bits which fall outside of the viewport boundary. Referring to Figure 8A, in this exemplary situation the merge logic operates as follows.
  • Memory byte M1 is loaded into input register 31 and is barrel shifted in barrel shifter 32 as defined by the bit offset, which is 4 in the case under consideration. Since the viewport starts in background, register 33 will be clear.
  • the appropriate mask is applied to multiplexer 34 to select the low order two bits from register 33 and the high order six bits from the barrel shifter 32.
  • the result is stored in register 33 by setting the control bit of multiplexer 35 appropriately, selecting the feedback path.
  • register 33 As register 33 is loaded, register 31 receives memory byte M2 which is therefore also shifted.
  • the mask applied to multiplexer 34 is now changed to select the most significant four bits from the barrel shifter 32 and the least significant four bits from the register 33.-, Multiplexer 35 control bit also changes to select the shifter output. This results in the first disply byte D1.
  • the whole sequence is shown in Figure 8C for the exemplary situation of Figure 8B.
  • the merged data from the merge logic 21 is loaded into data FIFO 29 to achieve the necessary output synchronisation.
  • the FIFO 29 is 8-bits wide by 32-bits deep and is equipped with a "FULL" output which halts the data coming in from the VRAM when necessary.
  • the presence of the data FIFO 29 allows the viewport controller to start accessing the VRAM during the line flyback time, and buffers sufficient pixel data to enable a steady output of pixels to be passed to the display. It is important that this feature Is included since the data stream from the VRAM into the merge logic is fragmented whenever the VRAM controller resets the VRAM serial port between windows.
  • the data On exit from the data FIFO, the data enters the video control logic 22 which multiplexes the 8-bit words into 4-bit subwords, controls the synchronisation of the data FIFO 29, and injects zero "background" data during intervals when no viewport is active so that the data FIFO 29 only has to buffer active pixel data.
  • viewport edge Information X e emerging from the VSL FIFO 26 is selectively loaded into the priority FIFO 30 together with appropriate priority data from the register file 19.
  • This loading process is arranged so that priority values corresponding to the 4-bit video subword which contains a given viewport edge are merged into the row of the priority FIFO 30 corresponding to that edge. More particularly, as each VRAM set-up list entry is presented by the VSL FIFO 26, the value X e is compared with the previous value of X e at the top of the priority FIFO 30, and if it falls In a different subword the priority FIFO 30 is loaded.
  • each X e entry Associated with each X e entry are four priority entries, one for each of the bits within the subword, which are loaded from the register file 19 at the same time as X e .
  • the priority FIFO 30 When two or more successive values of X e fall within a common subword, the priority FIFO 30 is not shifted, but the "overlapped" priority values are updated. The result is a set of four priorities which will correspond precisely to the four display data bits at the video output.
  • the output from the priority FIFO 30 is synchronised with the output from the video control logic 22 so that the correct four priority values are presented for each four-bit subword.
  • the value of HCOUNT is continuously compared with the X address at the top of the priority FIFO 30.
  • the priorities of the bits in a 4-bit subword are output to the planar priority control logic 23. This determines the highest priority at each of the four pixel locations so that bits from a viewport which does not have the highest priority at that instant can be masked as they are output from the video control logic 22.
  • the priority FIFO 30 is shifted by one location at each match In order to present the next subword address for comparison. If, at a given 4-bit subword location, there is no match between HCOUNT and the X e output of the priority FIFO 30, implying that there is no active boundary In that subword, the active priority will be that of the rightmost pixel of the last matching subword. In other words, the active priority during an active viewport transit remains what it was at the left edge of the viewport. Since the data FIFO 29 and the priority FIFO 30 are both loaded and read during a single scan line, only one of each is required.
  • the four priority values output from the priority FIFO 30 are passed via the planar priority controller 23 where they are compared with synchronised priority information from the other three viewport controllers within the windowing device. These are obtained from the global priority control logic 18 which can also incorporate priority information passed from other windowing devices in a multiple windowing device system via the priority bus.
  • the priority control logic 23 gates each bit of the 4-bit subword emerging from the video control logic 22, enabling it only if its priority is the highest (or equal highest) offered at that pixel. The resultant four bits are now ready for output as the contribution of this plane to the four-pixel-wide video output bus.
  • the priority values are converted from their binary representation to thermometer code and a bitwise-OR is performed on the results. This operation is carried out in parallel for the four pixels which are output by each viewport controller in every cycle and yields a thermometer code value corresponding to the highest of the priorities being compared.
  • the global priority controller performs a bitwise OR on the thermometer code values between planes and supplies each planar priority controller with the result.
  • the planar organisation of the windowing device architecture makes it very straightforward to cascade several such devices as a windowing device array, each device controlling up to four memory planes in a multi-planar system.
  • a windowing device array When more than one windowing device is used, it is necessary to determine the highest global priority overall at each pixel so that only the highest priority viewports are displayed. This is accomplished by way of a 28-bit priority bus compring seven bits for each of the four pixels. Connections to the priority bus are made via open-drain input/output pins, so that no external logic is required to perform the OR operation. In order for the bus to operate at the required speeds a pre-charge circuit is incorporated into each of the open drain outputs.
  • each chip "sees" four priority words on the bus corresponding to the highest global priority at each of the four pixels.
  • the priority bus runs at one quarter of the pixel rate, e.g. at 27.5MHz for 1280 x 1024 resolution at 60Hz refresh rate. It is the only linkage (apart from the standard timing signals) required in a multiple windowing device array.
  • each window is managed automatically in hardware and may be positioned, repositioned or removed instantaneously with no modification of data in memory.
  • a user can create, reposition and remove large numbers of viewports on a display screen, each viewport displaying any chosen window from the frame buffer.
  • Each viewport may be any size and each window may be any number of bits deep depending upon the number of memory planes in the system.
  • Viewports are completely independent and can overlap either transparently or opaquely. All boundary clipping and transparency effects are performed on the fly, and overlapping areas are automatically obscured, revealed or intermixed as required with no user intervention and no software or processing overhead.
  • Each of the windowing devices as hereinbefore described has the capability to control up to four planes of memory and up to four independent windows per memory plane. These may be stacked in any configuration ranging from sixteen 1-bit deep windows to four 4-bit deep windows or any combination in between. Multiple windowing devices may be cascaded to provide any number of windows, each any number of bits deep. For example, a sixteen plane system may be controlled by means of four of the described windowing devices to provide up to 641-bit text windows, or one 16-bit deep window with up to 48 1-bit text windows, or up to eight 8-bit deep windows, and so on. Window configuration is dynamically allocated and re-allocated as required.
  • the modularity and high performance of the described windowing device makes it a cost effective solution to image manipulation tasks in systems ranging from PC graphics cards to top-end workstations. It is compatible with most implementations of graphics standards such as GKS, CGI and DEGIS, and may be integrated with windowing protocols such as X windows and NeWS.
  • Major applications of the invention include CAD, particularly for architecture, IC design and PCB layout, business graphics, drafting, medical imaging, cartography, and electronic publishing.
  • the described windowing device comprises four viewport controllers each capable of processing four window-viewport assignments in a respective memory plane; the invention extends to a single such viewport controller and also extends to a viewport controller operating on the same principles but not adapted for the control of four viewports, the choice of four viewport controller per windowing device and four viewports controlled by each viewport controller being a judicious selection having regard to all of the operating requirements and constraints but otherwise being exemplary.
  • VRAM for the display memory is advantageous in view of the inherent suitability of VRAM for graphics applications, but the invention is not to be regarded as limited to the use of VRAM and an alternative embodiment could be constructed with DRAM (dynamic RAM) memory; such an alternative embodiment is in fact described in the Ph.D.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Processing Or Creating Images (AREA)
EP88301742A 1987-02-27 1988-02-29 Systèmes graphiques à ordinateur Expired - Lifetime EP0280582B1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
GB8704653 1987-02-27
GB878704653A GB8704653D0 (en) 1987-02-27 1987-02-27 Computer graphics
GB878727119A GB8727119D0 (en) 1987-11-19 1987-11-19 Computer graphics hardware
GB8727119 1987-11-19
GB8801012 1988-01-18
GB888801012A GB8801012D0 (en) 1988-01-18 1988-01-18 Improvements in computer graphics systems

Publications (3)

Publication Number Publication Date
EP0280582A2 true EP0280582A2 (fr) 1988-08-31
EP0280582A3 EP0280582A3 (en) 1990-07-04
EP0280582B1 EP0280582B1 (fr) 1995-07-19

Family

ID=27263330

Family Applications (1)

Application Number Title Priority Date Filing Date
EP88301742A Expired - Lifetime EP0280582B1 (fr) 1987-02-27 1988-02-29 Systèmes graphiques à ordinateur

Country Status (5)

Country Link
EP (1) EP0280582B1 (fr)
JP (1) JPS6414678A (fr)
AT (1) ATE125379T1 (fr)
DE (1) DE3854165D1 (fr)
GB (1) GB2202115B (fr)

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0344082A3 (en) * 1988-05-23 1990-08-01 International Business Machines Corporation Method for accessing visually obscured data in a multi-tasking system
EP0439873A1 (fr) * 1990-01-29 1991-08-07 International Business Machines Corporation Système de traitement de données
EP0483576A3 (en) * 1990-10-31 1993-06-16 International Business Machines Corporation Application independent services enabling the incorporation of hypermedia
EP0459711A3 (en) * 1990-05-31 1993-08-04 Matsushita Electric Industrial Co., Ltd Method and apparatus for processing image data
EP0605945A1 (fr) * 1992-12-15 1994-07-13 Firstperson, Inc. Présentation d'informations dans un système d'affichage à fenêtres transparentes
US5463728A (en) * 1993-03-10 1995-10-31 At&T Corp. Electronic circuits for the graphical display of overlapping windows with transparency
GB2296641A (en) * 1994-12-27 1996-07-03 Fujitsu Ltd Window display processing method and apparatus
EP0757833A1 (fr) * 1994-04-29 1997-02-12 Cirrus Logic Format et profondeur de pixel variables pour fenetres video
WO1997014133A3 (fr) * 1995-09-27 1997-08-28 Cirrus Logic Inc Circuits, systemes et procedes pour topographie memoire, et systems de commande d'affichage les utilisant
EP0798690A3 (fr) * 1996-03-25 1997-12-29 Siemens Aktiengesellschaft Circuit d'insertion d'image dans l'image
EP0840276A3 (fr) * 1996-11-01 1999-06-23 Texas Instruments Incorporated Traitement des fenêtres dans un système d'affichage sur écran
EP0840277A3 (fr) * 1996-11-01 1999-06-23 Texas Instruments Incorporated Traitement des fenêtres dans un système d'affichage sur écran
EP0883292A3 (fr) * 1989-04-24 1999-12-15 Motorola, Inc. Récepteur de télévision OSD avec lissaye des fenêtres et amélioration de bord
US6310657B1 (en) 1996-11-01 2001-10-30 Texas Instruments Incorporated Real time window address calculation for on-screen display
EP1271409A1 (fr) * 2001-06-28 2003-01-02 Sun Microsystems, Inc. Procédé et système permettant de générer une image numérique comprenant un objet transparent
USRE41922E1 (en) * 1993-05-10 2010-11-09 Apple Inc. Method and apparatus for providing translucent images on a computer display
US8724029B2 (en) * 2011-05-26 2014-05-13 Adobe Systems Incorporated Accelerating video from an arbitrary graphical layer
US9092128B2 (en) 2010-05-21 2015-07-28 Apple Inc. Method and apparatus for managing visual information

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5274755A (en) * 1989-02-08 1993-12-28 Sun Microsystems, Inc. Hardware implementation for providing raster offsets in a graphics subsystem with windowing
JPH0567185A (ja) * 1991-09-09 1993-03-19 Victor Co Of Japan Ltd 画像表示処理装置
GB2273025B (en) * 1992-11-12 1997-03-26 Rockwell International Corp Automatic call distributor with a programmable data window display system and method
US5918039A (en) * 1995-12-29 1999-06-29 Wyse Technology, Inc. Method and apparatus for display of windowing application programs on a terminal
US7720672B1 (en) 1995-12-29 2010-05-18 Wyse Technology Inc. Method and apparatus for display of windowing application programs on a terminal

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4209832A (en) * 1978-06-13 1980-06-24 Chrysler Corporation Computer-generated display for a fire control combat simulator
EP0121015B1 (fr) * 1983-03-31 1990-03-07 International Business Machines Corporation Gestion de l'espace de présentation et visualisation dans une partie déterminée de l'écran d'un appareil terminal virtuel à fonctions multiples
US4616220A (en) * 1983-08-22 1986-10-07 Burroughs Corporation Graphics display comparator for multiple bit plane graphics controller
DE3485132D1 (de) * 1983-10-17 1991-11-07 Ibm Anzeigesystem mit vielfachen bildfenstern.
WO1985002049A1 (fr) * 1983-11-03 1985-05-09 Burroughs Corporation Procede pour deplacer electroniquement des parties de plusieurs images differentes sur un ecran a tube a rayons cathodiques
US4663617A (en) * 1984-02-21 1987-05-05 International Business Machines Graphics image relocation for display viewporting and pel scrolling
JPS61296384A (ja) * 1985-06-26 1986-12-27 株式会社日立製作所 画面表示制御装置

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0344082A3 (en) * 1988-05-23 1990-08-01 International Business Machines Corporation Method for accessing visually obscured data in a multi-tasking system
EP0883292A3 (fr) * 1989-04-24 1999-12-15 Motorola, Inc. Récepteur de télévision OSD avec lissaye des fenêtres et amélioration de bord
EP0439873A1 (fr) * 1990-01-29 1991-08-07 International Business Machines Corporation Système de traitement de données
US5293470A (en) * 1990-01-29 1994-03-08 International Business Machines Corporation Data processing system for defining and processing objects in response to system user operations
EP0459711A3 (en) * 1990-05-31 1993-08-04 Matsushita Electric Industrial Co., Ltd Method and apparatus for processing image data
EP0483576A3 (en) * 1990-10-31 1993-06-16 International Business Machines Corporation Application independent services enabling the incorporation of hypermedia
US5999191A (en) * 1992-12-15 1999-12-07 Sun Microsystems, Inc Method and apparatus for presenting information in a display system using transparent windows
EP0605945A1 (fr) * 1992-12-15 1994-07-13 Firstperson, Inc. Présentation d'informations dans un système d'affichage à fenêtres transparentes
US5651107A (en) * 1992-12-15 1997-07-22 Sun Microsystems, Inc. Method and apparatus for presenting information in a display system using transparent windows
US6384840B1 (en) 1992-12-15 2002-05-07 Sun Microsystems, Inc. Method and apparatus for presenting information in a display system using transparent windows
US6694486B2 (en) * 1992-12-15 2004-02-17 Sun Microsystems, Inc. Method and apparatus for presenting information in a display system using transparent windows
US5463728A (en) * 1993-03-10 1995-10-31 At&T Corp. Electronic circuits for the graphical display of overlapping windows with transparency
USRE41922E1 (en) * 1993-05-10 2010-11-09 Apple Inc. Method and apparatus for providing translucent images on a computer display
USRE44241E1 (en) 1993-05-10 2013-05-28 Apple Inc. Method and apparatus for providing translucent images on a computer display
USRE45630E1 (en) 1993-05-10 2015-07-28 Apple Inc. Method and apparatus for providing translucent images on a computer display
EP0757833A1 (fr) * 1994-04-29 1997-02-12 Cirrus Logic Format et profondeur de pixel variables pour fenetres video
GB2296641A (en) * 1994-12-27 1996-07-03 Fujitsu Ltd Window display processing method and apparatus
GB2296641B (en) * 1994-12-27 1999-04-07 Fujitsu Ltd Window display processing method and apparatus
US5854628A (en) * 1994-12-27 1998-12-29 Fujitsu Limited Window display processing method and apparatus
US6025840A (en) * 1995-09-27 2000-02-15 Cirrus Logic, Inc. Circuits, systems and methods for memory mapping and display control systems using the same
US6058464A (en) * 1995-09-27 2000-05-02 Cirrus Logic, Inc. Circuits, systems and method for address mapping
WO1997014133A3 (fr) * 1995-09-27 1997-08-28 Cirrus Logic Inc Circuits, systemes et procedes pour topographie memoire, et systems de commande d'affichage les utilisant
EP0798690A3 (fr) * 1996-03-25 1997-12-29 Siemens Aktiengesellschaft Circuit d'insertion d'image dans l'image
US6310657B1 (en) 1996-11-01 2001-10-30 Texas Instruments Incorporated Real time window address calculation for on-screen display
US6452641B1 (en) 1996-11-01 2002-09-17 Texas Instruments Incorporated Method and apparatus for providing and on-screen display with variable resolution capability
EP0840276A3 (fr) * 1996-11-01 1999-06-23 Texas Instruments Incorporated Traitement des fenêtres dans un système d'affichage sur écran
EP0840277A3 (fr) * 1996-11-01 1999-06-23 Texas Instruments Incorporated Traitement des fenêtres dans un système d'affichage sur écran
EP1271409A1 (fr) * 2001-06-28 2003-01-02 Sun Microsystems, Inc. Procédé et système permettant de générer une image numérique comprenant un objet transparent
US9092128B2 (en) 2010-05-21 2015-07-28 Apple Inc. Method and apparatus for managing visual information
US8724029B2 (en) * 2011-05-26 2014-05-13 Adobe Systems Incorporated Accelerating video from an arbitrary graphical layer

Also Published As

Publication number Publication date
DE3854165D1 (de) 1995-08-24
EP0280582B1 (fr) 1995-07-19
ATE125379T1 (de) 1995-08-15
EP0280582A3 (en) 1990-07-04
JPS6414678A (en) 1989-01-18
GB8804746D0 (en) 1988-03-30
GB2202115A (en) 1988-09-14
GB2202115B (en) 1991-09-25

Similar Documents

Publication Publication Date Title
EP0280582B1 (fr) Systèmes graphiques à ordinateur
US5251298A (en) Method and apparatus for auxiliary pixel color management using monomap addresses which map to color pixel addresses
US5742788A (en) Method and apparatus for providing a configurable display memory for single buffered and double buffered application programs to be run singly or simultaneously
US5218674A (en) Hardware bit block transfer operator in a graphics rendering processor
US5594473A (en) Personal computer apparatus for holding and modifying video output signals
EP0524362A1 (fr) Adapteur d'affichage
US5696540A (en) Display controller
IE60736B1 (en) Video display apparatus
EP0318517A4 (en) Display generator circuitry for personal computer system
US4749990A (en) Image display system and method
US4800380A (en) Multi-plane page mode video memory controller
US4845663A (en) Image processor with free flow pipeline bus
EP0139095A2 (fr) Sélection d'image dans un dispositif d'affichage à balayage à trame
JPH0721758B2 (ja) ラスタ走査ビデオ制御装置において更新プロセスと表示プロセスとの間で表示メモリをプログラム可能に振り分ける装置
CA1270344A (fr) Systeme d'affichage a circuit de traitement de trames a puissance accrue
Read Developing the next generation cockpit display system
EP0182454A2 (fr) Contrôleur de système vidéo avec un circuit de dépassement de l'adresse de ligne
EP0279227A2 (fr) Générateur de tracé de vecteur pour l'affichage vidéo à balayage par trame
EP0658858B1 (fr) Ordinateur graphique
EP0225197A2 (fr) Dispositif de commande d'affichage vidéo
JPS62203285A (ja) ラスタ処理用変換回路
EP0216886B1 (fr) Appareil d'affichage video
EP0264603B1 (fr) Système numérique d'affichage à balayage à trame
EP0201261A2 (fr) Processeur pour l'exécution d'opérations logiques sur des octets de données de points d'image
KR100252648B1 (ko) 그래픽스시스템및그래픽스드로잉방법

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH DE ES FR GB GR IT LI LU NL SE

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH DE ES FR GB GR IT LI LU NL SE

17P Request for examination filed

Effective date: 19910307

17Q First examination report despatched

Effective date: 19930225

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: AXIOM INNOVATION LIMITED

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH DE ES FR GR IT LI LU NL SE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 19950719

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19950719

Ref country code: BE

Effective date: 19950719

Ref country code: ES

Free format text: THE PATENT HAS BEEN ANNULLED BY A DECISION OF A NATIONAL AUTHORITY

Effective date: 19950719

Ref country code: CH

Effective date: 19950719

Ref country code: LI

Effective date: 19950719

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 19950719

Ref country code: FR

Effective date: 19950719

Ref country code: AT

Effective date: 19950719

REF Corresponds to:

Ref document number: 125379

Country of ref document: AT

Date of ref document: 19950815

Kind code of ref document: T

REF Corresponds to:

Ref document number: 3854165

Country of ref document: DE

Date of ref document: 19950824

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Effective date: 19951019

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Effective date: 19951020

EN Fr: translation not filed
NLV1 Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act
PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19960229

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed