EP0322058A1 - Anordnung zur Regelung der Übertragungsgeschwindigkeit für mindestens zwei Komponenten eines digitalen Videosignals - Google Patents

Anordnung zur Regelung der Übertragungsgeschwindigkeit für mindestens zwei Komponenten eines digitalen Videosignals Download PDF

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Publication number
EP0322058A1
EP0322058A1 EP88202938A EP88202938A EP0322058A1 EP 0322058 A1 EP0322058 A1 EP 0322058A1 EP 88202938 A EP88202938 A EP 88202938A EP 88202938 A EP88202938 A EP 88202938A EP 0322058 A1 EP0322058 A1 EP 0322058A1
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EP
European Patent Office
Prior art keywords
circuit
component
output
standard
rap
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP88202938A
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English (en)
French (fr)
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EP0322058B1 (de
Inventor
François Société Civile S.P.I.D. Modarresse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronique Gran Public
Koninklijke Philips NV
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Philips Electronique Gran Public
Philips Gloeilampenfabrieken NV
Koninklijke Philips Electronics NV
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Priority to AT88202938T priority Critical patent/ATE95367T1/de
Publication of EP0322058A1 publication Critical patent/EP0322058A1/de
Application granted granted Critical
Publication of EP0322058B1 publication Critical patent/EP0322058B1/de
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/146—Data rate or code amount at the encoder output
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N11/00—Colour television systems
    • H04N11/04—Colour television systems using pulse code modulation
    • H04N11/042—Codec means
    • H04N11/044—Codec means involving transform coding

Definitions

  • the present invention relates to a device for controlling bit rate combined with at least two components of digital video signals, comprising a correlation reduction circuit which receives said digital signals representative of a certain number of points of a picture divided into blocks, a scanning conversion circuit which transforms the two-dimensional sequence of values of the coefficients F i (u, v) of output from the correlation reduction circuit into a one-dimensional sequence, a normalization circuit, a quantization circuit by conversion into an integer value, a circuit for coding the quantized values, and a flow regulation circuit which receives the coded values according to a variable flow and, on the one hand, returns an average standard value linked to said flow to the normalization circuit, on the other hand delivers values at constant flow rate, on the output of the regulating device, a delay circuit possibly being provided for example between said correlation reduction and sweep conversion circuits.
  • This invention is particularly applicable in the field of transmission of television signals, as well as in that of recording and / or memorizing such signals.
  • the digitization of television signals is an extremely useful solution in the case of links where the disturbing noise is particularly high, satellite links in particular.
  • a television picture contains a very large amount of information, the digital representation of which results in a high bit rate.
  • the direct digitization of the luminance and chrominance components at the frequencies of 13.5 and 6.75 megahertz respectively, imposed by the standards would indeed lead to a bit rate of 216 Meb / s. This speed is completely prohibitive, especially in the case of consumer magnetic recording devices.
  • the use of flow reduction techniques is therefore necessary, and all the more feasible when a relatively large redundancy exists in the image.
  • U.S. Patent No. 4,394,774 describes a rate control device which operates by coding video signals following an orthogonal transformation. Each image is cut into blocks of determined size, then said orthogonal transformation is applied to each block. The coefficients resulting from this transformation are then divided by a normalization factor, then quantified and coded. Such a device does not however take into account the differences in statistical properties of the video signals locally in order to adapt certain coding parameters to these local properties.
  • the object of the invention is to propose a device for regulating the bit rate of digital video signals which overcomes such a drawback.
  • the device firstly comprises a correlation reduction circuit which is for example a circuit for transformation into discrete cosine 10.
  • This circuit 10 receives a series of digital signals representing in the form of a matrix of values the chrominance of a certain number of points or elements of an image divided into blocks, and delivers for each block a two-dimensional series of coefficients F i (u, v).
  • Figure 2a shows such an image, divided into M x N blocks.
  • the transformation into discrete cosine is a known operation, and the expression of these transformation coefficients obtained successively for each block will therefore not be given here. It will simply be recalled that numerous statistical measurements have made it possible to show the very strong correlation between neighboring points of a frame or of an image, and that the object of the transformation is to obtain a set of coefficients more independent than the values. available before transformation.
  • the coefficients F i (u, v) are then supplied, here by means of a delay circuit 20, to a scan conversion circuit 30 intended to convert the two-dimensional series of values F i (u, v) into a one-dimensional suite.
  • the delay circuit 20 is used to store one or more blocks of one of the components when the two components are not available simultaneously.
  • the one-dimensional sequence can for example be a zig-zag sequence like that indicated in FIG.
  • a normalization circuit 40 receives this one-dimensional sequence.
  • the output of circuit 40 normalized, is then quantified in quantization circuit 50 and then coded in coding circuit 60.
  • the output of this coding circuit 60 is connected to the input of a buffer memory 70 which receives according to a variable flow the coded values and restores them on its main output S with a constant flow.
  • This main output constitutes the output of the flow control device according to the invention.
  • the quantization operation makes it possible to convert the normalized value of each coefficient, expressed with a floating point, into an integer value, for example either by simple rounding, or preferably by truncation by taking the integer part of the value before quantification, and these operations can also be optionally combined with a compression or an expansion of the scale of values. Subject to such quantification, a certain number of values between 0 and 1 are replaced by the value 0, which decreases the number of significant coefficients to be transmitted to the coding circuit and therefore goes in the direction of the reduction in bit rate sought.
  • the coding operation is carried out here using tables of values coded according to a code of Huffman, for coding either coefficient values (variable length coding) or range lengths (range coding).
  • the normalization circuit 40 will now be described in more detail. To adapt the bit rate to the local properties of the image, it was necessary to find a function relating the activity of a block to the number of binary elements necessary to ensure the coding of this block (the activity translates the nature of the spectral content of the block and, more precisely, the greater or lesser importance, in this content, of high spatial frequencies and is therefore for example low for a quasi-uniform block, or on the contrary all the higher the more the block contains more contours and that these contours are stiffer).
  • the first coefficient, C1 is not used, because it corresponds to the average amplitude of the block and does not provide any information on the spectral content of the block. Its value is independent of the bit rate, because it is coded in a particular way, with a constant number of bits, eight or nine bits for example, to avoid erroneous interpretations which would lead to changes in colors or gray levels.
  • the rate regulation is carried out after the coding of a certain number of blocks corresponding to the component D R and of a certain number of blocks corresponding to the component D B , in the present case after the coding of a single block D R and in a single block D B , without this choice being limiting.
  • a global standard is calculated according to the filling rate of the buffer memory 70 and the variation of this rate.
  • This circuit 40 first comprises a circuit 401 for calculating rap (acti) at starting from the activities acti (D R ) and acti (D B ) of each of the two components D R and D B , this circuit 401 being provided at the output of the scanning conversion circuit 30.
  • a circuit 402 of computation of rap (norm) then calculates this last quantity using the expression (8) and from the hypothesis retained (in a nonlimiting manner) as for the choice of the function f.
  • This circuit 402 is here followed by a recursive low-pass filtering circuit 403.
  • rap (norm) thus smoothed is supplied to a circuit 404 for calculating specific norms, that is to say norm (D R ) and norm (D B ) according to expressions (12) and (13 ) respectively.
  • a divider 405 finally ensures the division of the output of the scanning conversion circuit 30 by standard (D R ) or by standard (D B ) according to the nature of the component being coded (block D R or block D B , as it has been specified above).
  • the calculation of the specific norms norm (D R ) and norm (D B ) carried out by the circuit 404 implies that this circuit receives, in accordance with expressions (12) and (13), not only the value of rap (norm) but also that of the overall standard.
  • This global standard is provided by a global standard calculation circuit 406 according to the following process.
  • a counter 407 provided at the output of the buffer memory 70 gives the exact number of binary elements present in this memory for the current block being processed, and an auxiliary memory 408 temporarily stores this number of binary elements which, during the processing of the next block become the current block, will of course represent the number of binary elements of the block become the previous block.
  • a subtractor 409 determines, with its sign, the difference between the input and the output of said auxiliary memory 408, that is to say the difference in the number of binary elements between two successive blocks, and supplies this difference to the global standard calculation circuit 406.
  • This circuit 406 also receives, on another input connection, the number of binary elements of the current block, supplied by the counter 407, and delivers as an output, for sending to the calculation circuit of specific standards 404, the modified value, more or less, of the global standard.
  • the latter respectively comprises a first input connection 701 connected to the output of the coding circuit 60 and controlling both the writing in memory and the incrementation of the counter 407, and a second input connection 702, connected to a clock circuit 410 defining a fixed rate (here, for example, 1 Mbit / second but satisfactory tests have also been carried out with higher or lower rates) for ensure constant flow.
  • This clock circuit 410 therefore controls the emptying of the buffer memory 70, as well as the decrementation of the counter 407.
  • the invention could not be limited by the type of path chosen for reading the two-dimensional matrix of the transformation coefficients of each image block. Whatever this route and the more or less marked specific advantage (s) that result, standardization can be carried out according to the principles set out in detail above.
  • the type of route adopted has an influence mainly on the coding, and the nature of the coding obviously depend on the quantity of information which leaves the coding circuit and therefore the bit rate and the global standard, but without this modifying the mode of implementation of the invention nor of it decreases interest.
  • the activity thus defined no longer has such a good correlation with the flow rate, which nevertheless constituted the initial criterion for the definition of a satisfactory expression of the activity. This therefore results in a poorer ratio between the variations in flow and the respective values of the standards and a risk of a certain drift for the filling rate of the buffer memory 70.
  • This drawback can be remedied, as indicated in FIG. 1, by positioning between the output of the circuit 402 for calculating rap (standard) and the corresponding input of circuit 404 for calculating specific standards, of circuit 403 for recursive low-pass filtering of the standard.
  • the inertia thus conferred on the device makes it possible to confine the parameters of the operations in a relatively small interval around their average value and therefore to limit this drift.
  • the invention is not limited to the device for implementation, on emission, of such regulation, but extends to the television image transmission system which includes at least one such device.
  • transmission we always mean here, of course, the actual transmission of the signals, but also their recording or memorization.
  • the invention also extends to any emission stage which, in such a transmission system, comprises the structure described with reference to FIG. 1, as well as to any stage corresponding reception.
  • Such a reception stage comprises, it will be noted, a signal restitution device which is the exact inverse of the regulation device described above.
  • This device comprises, more precisely and as indicated in FIG. 3, a buffer memory 170 receiving input signals at constant rate and delivering them at variable rate, a circuit 160 for decoding this information at variable rate, a circuit 150 for inverse quantization of the decoded signals, a reverse normalization circuit 140, a scan conversion circuit 130, possibly a delay circuit 120, and a correlation restitution circuit 110.
  • the reverse normalization circuit 140 is almost identical to the normalization circuit 40, with the replacement of the references 401 to 410 by the references 501 to 510.
  • the input signals of the rap calculation circuit 501 can be taken either at the input of the scanning conversion circuit 130 (connection in broken lines in FIG. 3) , or at the input of the reverse quantization circuit 150 (in this same FIG. 3, connection in solid line), the latter solution being preferably adopted.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Television Systems (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Color Television Systems (AREA)
  • Communication Control (AREA)
EP88202938A 1987-12-23 1988-12-19 Anordnung zur Regelung der Übertragungsgeschwindigkeit für mindestens zwei Komponenten eines digitalen Videosignals Expired - Lifetime EP0322058B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT88202938T ATE95367T1 (de) 1987-12-23 1988-12-19 Anordnung zur regelung der uebertragungsgeschwindigkeit fuer mindestens zwei komponenten eines digitalen videosignals.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8718046 1987-12-23
FR8718046A FR2625399A1 (fr) 1987-12-23 1987-12-23 Dispositif de regulation de debit conjointe a au moins deux composantes de signaux video numeriques

Publications (2)

Publication Number Publication Date
EP0322058A1 true EP0322058A1 (de) 1989-06-28
EP0322058B1 EP0322058B1 (de) 1993-09-29

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EP88202938A Expired - Lifetime EP0322058B1 (de) 1987-12-23 1988-12-19 Anordnung zur Regelung der Übertragungsgeschwindigkeit für mindestens zwei Komponenten eines digitalen Videosignals

Country Status (7)

Country Link
US (1) US4868641A (de)
EP (1) EP0322058B1 (de)
JP (1) JPH01202082A (de)
KR (1) KR960011976B1 (de)
AT (1) ATE95367T1 (de)
DE (1) DE3884588T2 (de)
FR (1) FR2625399A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993013628A1 (en) * 1991-12-20 1993-07-08 Ampex Systems Corporation Method and apparatus for image data compression using combined luminance/chrominance coding
EP0660619A1 (de) * 1993-12-22 1995-06-28 Laboratoires D'electronique Philips S.A.S. Verfahren zur variablen Längenkodierung von Bildern und Vorrichtung zur Ausführung eines solchen Verfahrens

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051840A (en) * 1988-12-14 1991-09-24 Fuji Photo Film Co., Ltd. Device for coding a picture signal by compression
FR2653953A1 (fr) * 1989-10-27 1991-05-03 Philips Electronique Lab Dispositif de codage comportant un codeur a mots de longueur variable et dispositif de decodage associe.
US5841476A (en) * 1995-03-03 1998-11-24 Kokusai Denshin Denwa Co. Ltd. Coding apparatus for encoding motion picture
JP3250507B2 (ja) * 1997-12-10 2002-01-28 株式会社日立製作所 画像データの符号量制御方法および装置
WO2009040799A1 (en) * 2007-09-24 2009-04-02 Ceragon Networks Ltd. Maintaining a constant delay in point-to-point transmission
WO2009040800A1 (en) * 2007-09-24 2009-04-02 Ceragon Networks Ltd. Errorless and hitless variable data rate communications
US8270291B2 (en) * 2007-09-24 2012-09-18 Ceragon Networks Ltd. Protected variable data rate communication systems

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394774A (en) * 1978-12-15 1983-07-19 Compression Labs, Inc. Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback
EP0189703A1 (de) * 1984-12-21 1986-08-06 Thomson Grand Public Verfahren zur adaptiven Transformationskodierung und Dekodierung einer Bildfolge und Geräte zur Durchführung dieses Verfahrens
EP0248729A1 (de) * 1986-06-06 1987-12-09 Thomson-Csf Rechner für monodimensionelle Kosinus-Transformationen und Bildkodier- und -dekodiergeräte, welche solche Rechner benutzen

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8500735A (nl) * 1985-03-14 1986-10-01 Philips Nv Systeem voor het regelsgewijs in een compressie-inrichting comprimeren van binaire data van een beeldveld, decompressie-inrichting voor gebruik in zo een systeem en afbeeldinrichting voorzien van zo een decompressie-inrichting.
US4802003A (en) * 1986-02-28 1989-01-31 Canon Kabushiki Kaisha Color picture information transmission system
US4774562A (en) * 1987-06-02 1988-09-27 Eastman Kodak Company Image transmission system with preview mode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394774A (en) * 1978-12-15 1983-07-19 Compression Labs, Inc. Digital video compression system and methods utilizing scene adaptive coding with rate buffer feedback
EP0189703A1 (de) * 1984-12-21 1986-08-06 Thomson Grand Public Verfahren zur adaptiven Transformationskodierung und Dekodierung einer Bildfolge und Geräte zur Durchführung dieses Verfahrens
EP0248729A1 (de) * 1986-06-06 1987-12-09 Thomson-Csf Rechner für monodimensionelle Kosinus-Transformationen und Bildkodier- und -dekodiergeräte, welche solche Rechner benutzen

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993013628A1 (en) * 1991-12-20 1993-07-08 Ampex Systems Corporation Method and apparatus for image data compression using combined luminance/chrominance coding
US5434623A (en) * 1991-12-20 1995-07-18 Ampex Corporation Method and apparatus for image data compression using combined luminance/chrominance coding
EP0660619A1 (de) * 1993-12-22 1995-06-28 Laboratoires D'electronique Philips S.A.S. Verfahren zur variablen Längenkodierung von Bildern und Vorrichtung zur Ausführung eines solchen Verfahrens

Also Published As

Publication number Publication date
KR960011976B1 (en) 1996-09-06
EP0322058B1 (de) 1993-09-29
US4868641A (en) 1989-09-19
JPH01202082A (ja) 1989-08-15
KR890010723A (ko) 1989-08-10
DE3884588T2 (de) 1994-04-07
ATE95367T1 (de) 1993-10-15
DE3884588D1 (de) 1993-11-04
FR2625399A1 (fr) 1989-06-30

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