EP0362017A1 - Device such as diode, triode or flat and integrated cathodoluminescent display device, and manufacturing process - Google Patents

Abstract

The microcomponent of the invention comprises an Si substrate of the type, (2) oxidized at the surface (4), at least one cathode with a cesium-shaped cesized surface of n-type monocrystalline Si (7) being formed on this substrate. It is surrounded by monocrystalline p-type Si (6). A layer of Si02 (8) formed on the p-type Si has an opening (9) facing the cathode. This opening is vacuum sealed by the anode material (11).

Description

The present invention relates to a component such as a diode, a triode, or a flat and integrated cathodoluminescent display device, and to a method of manufacturing such a device.

There are a number of publications in the recent literature relating to cathodoluminescent display devices. Apart from the conventional electron gun exciting a phosphor in a vacuum tube of the "television tube" type, new approaches are emerging. Thus, a trend currently observed consists in the use of matrix arrangements of microchannels whose operation is multiplexed using suitable electronics. An exemplary embodiment of such a device is given in an article by R. Meyer et al. entitled "Microtips fluorescent display" and presented during the conference "Japan Display 1986". The microchannels are formed from molybdenum tips, and the electrons are extracted by field effect between the tip and a grid located at the top of the tip. An anode made of the phosphor material is positioned at a distance of approximately 100 μm from the grid plane.

We can consider a similar structure, but using for the realization of the microchannels, no longer a matrix of microtips with field effect, but a matrix of cold microcathodes produced on semiconductor (Si for example). This type of cathode uses a semiconductor surface treated so as to have a negative electronic affinity. With regard to Si, the surface treatment making it possible to obtain this property consists in successively adsorbing on a surface (100) reconstructed by heat treatment, a cesium monolayer and oxygen monolayer. More details on this caesiation technique can be found in the articles by B. Goldstein (Surf. Sci. 47, 1975, p 143) and JD Lévine (Surf. Sci 34, 1973, p 90).

• a) de l'abaissement considérable du niveau du vide,
• b) de la courbure des bandes de conduction à la surface,

les électrons situés au minimum de la bande de conduction en volume ont une énergie supérieure à celle du niveau du vide : on obtient la situation dite d'affinité électronique "négative".Under the conditions for ceasing the p-type Si described above, and because:

• a) considerable lowering of the vacuum level,
• b) the curvature of the conduction bands on the surface,

the electrons located at the minimum of the volume conduction band have an energy higher than that of the vacuum level: we obtain the situation called "negative" electronic affinity.

If the p-type silicon layer thus treated is placed on an n-type substrate, and if the junction thus obtained is directly polarized, electrons are injected which are emitted in a vacuum after crossing the layer of type p.

The making of such a cold cathode has been described by E.S. Kohn (IEEE Transactions on Electron Devices, ED-20, N ° 3, 1973, p 321).

E.S. Kohn used this type of cathode to reproduce on a screen supporting a phosphor and placed 0.5 mm from the cathode plane, characters etched in silicon and treated according to the preceding description in negative electronic affinity.

The disadvantage of all these devices (devices with field effect emission or cold silicon cathode) is that they can only operate under ultra-vacuum. This is particularly true for cesium-coated silicon surfaces, where the slightest adsorption of foreign atoms is likely to raise the energy position of the vacuum level, thus dramatically affecting the emission properties of the surface.

The subject of the present invention is a component such as a diode or a display device of the cold cathode type in p-type semiconductor treated so as to have a negative affinity, not requiring the creation of a vacuum. grown in a relatively large volume which can be produced automatically in series, and at a reasonable cost price.

The present invention also relates to a method of manufacturing such a component.

The component according to the invention comprises at least one microvolume containing a microcathode and autoscealed under vacuum by the anode material.

The process for manufacturing a component in accordance with the invention, a component of the cold cathode type formed on a substrate made of semiconductor material capable of being brought into a state of negative electronic affinity, this process consists, when this semiconductor material is silicon, at :
oxidizing one face of an n-type silicon substrate, this substrate being at least partially monocrystalline,
- etch in the silica of this face at least one opening,
depositing p-type silicon on the silica and on the parts of the substrate exposed so as to have a very flat surface after deposition, this silicon being monocrystalline in the openings and polycrystalline on the silica,
- deposit a layer of dielectric material,
- etch in this last layer openings substantially in the axis of the aforementioned openings until reaching the p-type silicon layer,
- carry out "in situ" cleaning of the surfaces of the p-type silicon layer exposed,
- carry out a treatment bringing the cleaned surfaces, in a state of negative electronic affinity,
- Evaporate under high vacuum and in grazing incidence a layer of anode material, the substrate being driven in a rotational movement about an axis perpendicular to the surface of this substrate, until the sealing of the microcavity thus produced.

• - la figure 1 est une vue schématique en coupe d'un microcomposant conforme à l'invention,
• - les figures 2,3A et 4 à 8 sont des vues schématiques en coupe illustrant les différentes étapes successives d'un premier mode de réalisation de l'invention, et
• - les figures 3B et 9 sont des vues schématiques en coupe montrant des étapes particulières d'un second mode de réalisation de l'invention.

The present invention will be better understood on reading the detailed description of two embodiments, taken as nonlimiting examples and illustrated by the appended drawing, in which:

• FIG. 1 is a schematic sectional view of a microcomponent according to the invention,
• FIGS. 2,3A and 4 to 8 are schematic sectional views illustrating the different successive stages of a first embodiment of the invention, and
• - Figures 3B and 9 are schematic sectional views showing specific steps of a second embodiment of the invention.

The invention is described below with reference to the production of a light micropoint and display panels comprising a very large number of such light micropoints, but it is understood that it is not limited to such a component, and that it can be implemented for the production of other cold cathode components such as diodes or triodes (the triodes being taken in the sense of "components with three electrodes").

FIG. 1 shows a light micropoint 1 according to the invention. This component 1 comprises a substrate 2 which is in this case made of n-type silicon, the underside of which has a coating 3 of material which is a good electrical conductor (ohmic contact), making it possible to connect the substrate 2 constituting the to an output conductor. one of the electrodes of component 1. According to another embodiment, not described in detail here, the substrate is made of AsGa. Those skilled in the art can easily adapt the steps of the method described below to this AsGa material, by referring to French Patent Application 88 04437.

The upper face of the substrate 2 is covered with a layer 4 of silica (Si0₂) or any other dielectric (Si₃N₄, Al₂0₃ ...), with the exception of an opening 5. The substrate 2 must be at least monocrystalline at the opening 5. The layer 4 and the surface of the substrate 2 constituting the opening 5 are covered with a p-type silicon layer 6. In the zone of the opening 5, the layer 6 has, in a volume 7, a monocrystalline structure. This volume 7 has roughly the shape of a micro-fungus, the base of which corresponds to the opening 5. The rest of the layer 6 deposited on the dielectric layer 4 has a polycrystalline structure. The reason for this difference in structure of layer 6 will appear below in the description of the method for manufacturing the light micropoint.

Layer 6 is coated with a layer 8 of silica or another dielectric, with the exception of an opening 9 coaxial with the opening 5 and of the same diameter as the latter. The surface 10 of the layer 6 not covered by the layer 8 is treated so as to have a negative electronic affinity, for example by caesiation. A layer 11 of anode material largely covers the opening 9 by sealing it, a high vacuum (of the order of 10⁻¹⁰ Torr) prevailing in the microvolume determined by the opening 9 sealed at one end by the layer 6 , and to the other by the layer 11. In the case where the component is, as specified above, a light micropoint, the layer 11 is made of a phosphor material, such as zinc oxide. In the case where the component is a diode or a triode, the layer 11 is simply an electrically conductive material. The layers 3, 6 and 11 are connected to suitably polarized voltage sources 12, 13.

Component 1 can operate in the ambient atmosphere since the vacuum is maintained in the microvolume thanks to the sealing effected by the anode material.

We will now describe a process for producing a component according to the invention.

Step 1 (Figure 2)

We start from a wafer 14 of standard n-type semiconductor material. Preferably, this material is for example silicon (100) or (110) or (111), because this material exists in the form of large substrates. The surface of the wafer 14 is oxidized until an insulating layer 15 of silica having for example a thickness of approximately 1000 to 1500 Å. Openings 16 are etched in the silica using an appropriate lithographic technique, for example optical or electronic. In top view, these openings 16 can be of any shape: circular, square, rectangular, oblong ... The dimensions of this shape seen from above are of the order of a micrometer. If the shape seen from above is circular, its diameter will be of the order of a micrometer.

In the case of cathodoluminescent components, one or more such components arranged side by side are used to define a light pixel.

Step 2 (Figures 3A and 3B)

The surfaces of the wafer 14 previously exposed by making the openings 16 in the silica, are covered with p-type monocrystalline silicon (crystal plane 100), by vapor phase epitaxy (in English: "Chemical Vapor Deposition"). It is important that the surface of the silicon deposit is flat. It is this surface which will be brought into the state of negative electronic affinity in a subsequent step (step 5).

To carry out this deposition of silicon, the invention provides two embodiments characterized by different deposition conditions.

The first mode, illustrated by FIG. 3A, consists in cracking the molecules of the SiH₄ + H₂ + B₂H₆ mixture at a temperature of around 900 to 1060 ° C and at atmospheric pressure (method called "APCVD" with AP "atmospheric pressure ", and CVD already explained above). The B₂H₆ gas makes it possible to obtain p-type doping of the silicon deposit. The growth of the deposit 17 on the substrate 14 left free by the openings 16 is monocrystalline, of the same orientation (plane 100) as the substrate 14, therefore making the deposit 17 suitable for being brought into the state of negative electronic affinity. On the other hand, the deposit 17A of silicon is polycrystalline on the silica.

The growth rate of the deposit in one direction perpendicular to the surface plane of the substrate being greater on the monocrystalline areas 16 than on the silica 15, one arrives after a certain time, which depends on the thickness of the starting silica layer 15, at a thickness deposit practically uniform over the entire wafer. The silicon deposit (17 + 17A) can then be described as "planarized".

When forming, as shown in FIG. 3A, several identical or similar components on the same substrate, for example with a view to producing a matrix network, the deposits (17 + 17A) can be given the shape of parallel bands on the 'axis of which the deposits 17 are aligned and, preferably, regularly spaced. These strips can be obtained by etching from layer 17A to layer 15. This etching forms in the layer 17A grooves parallel to the axes 17B on which are deposited columns 17, these grooves being each time equidistant from two consecutive axes of deposition columns 17. These grooves are then filled with silica 17C using a conventional deposition method such as LTO or HTO (LTO: Low Temperature Oxide; HTO; High Temperature Oxide) in combination with a "lift-off" technique "allowing the silica deposit to be easily removed on pads 17 and 17A. Another method consists in depositing a uniform layer of silicon nitride (Si₃N₄), in etching in this layer bands such as 17C and then practicing a localized oxidation of the underlying silicon. The silicon nitride is then removed by selective chemical attack (LOCOS type process).

The second embodiment, illustrated in FIG. 3B, is based on the technique of selective epitaxy, and is carried out at atmospheric pressure (APCVD) or else under reduced pressure (RP CVD, with RP for "reduced pressure") at a temperature between 900 and 1060 ° C. approximately. It uses a gas mixture SiH₄ + HCl + H₂ + B₂H₆ which makes it possible to work near thermodynamic equilibrium.

The selectivity of the deposit is governed by a mechanism of selective nucleation by which the growth of silicon is possible on surfaces with a low nucleation barrier, such as silicon (100), and prohibited on a foreign surface such as silica. For more details, refer to the article by JO BORLAND and CI DROWLEY published in "Solid State Technology" of August 1985, page 141, as well as to the article by L. KARAPIPERIS and collaborators published in "Proceedings of the 18 ^th Conference on Solid State Devices and Materials ", Tokyo 1986, page 713.

The epitaxy is performed on the substrate 14 covered with the layer 15 and comprising the holes 16, as shown in FIG. 2. When the holes 16 are filled with monocrystalline p-type silicon 18, the arrival of the HCl gas is cut off, which removes the selectivity and allows the deposition of silicon also on the layer 15 but polycrystalline, the deposit then being uniform in thickness over the entire surface of the wafer (surfaces 18 and 15). The total thickness of the deposit is of the order of 1 micrometer. The deposit 19 on the surfaces 18 is monocrystalline p silicon, and slightly protrudes from these surfaces, while the deposit 20 on the remaining surfaces 15 is polycrystalline p silicon.

According to a variant, not shown, of the first and of the second embodiment, the thickness of the layers 17, 18 and 19 of monocrystalline silicon p is minimized. Components are obtained which operate more quickly because their response time is mainly a function of the transfer time of the minority carriers in the p-type silicon zone (layers 17, 18 and 19).

The method for producing this variant according to the second embodiment is as follows. The openings made in the silica 15 are selectively filled with n-type monocrystalline silicon, without depositing it on the silica. We therefore place ourselves under the conditions of selective epitaxy, and gas streams comprising for example SiH₄ + HCl + H₂ + PH₃ are used. The PH₃ component is used for doping type n. The deposition of silicon p is then carried out, non-selectively this time, this silicon being monocrystalline on the layer of silicon n and polycrystalline on the layer of silica, using a gaseous mixture SiH₄ + B₆H₆.

The silicon layer p thus obtained can have a thickness of between 1,000 and 5,000 Å approximately. This method also makes it possible to produce, by localized oxidation (for example by using the method known under the name of "LOCOS"), silicon bands p (forming columns of a matrix display device similar to that shown in Figure 9) isolated from each other.

Step 3 (Figure 4)

Is deposited on one or other of the structures of Figures 3A and 3B a dielectric layer 21 of silica (Si0₂) for example (this not being limiting) having a thickness between 2 and 10 micrometers. To simplify the drawing, FIG. 4A shows the structure of FIG. 3A with the substrate 14 and the layers 15, 17 and 17A, but it is understood that the structure of the figure could also have been represented there. 3B with the substrate 14 and the layers 15,18,19 and 20. Figures 5 to 8 described below also include the structure of Figure 3A, only Figure 9 includes the structure of Figure 38. The silica layer (HTO) 21 is preferably carried out by a high temperature process (HTO), for example by pyrolysis of a gaseous mixture SiH₂Cl₂ + N₂0 at a temperature of at least 250 ° C, and advantageously between 850 and 900 ° C approx. The silica layer thus obtained has good mechanical and electrical properties.

Instead of silica, the layer 21 can be formed from dielectric materials such as Si₃N₄, Al₂0₃, Zr0₂, etc., using appropriate deposition techniques.

Step 4 (Figure 5)

It is etched by reactive ion etching or RIE (from the English Reactive Ion Etching) in the dielectric layer 21 openings 22 coaxial with the layers 17 or 19. It will be noted that due to the overflow of the monocrystalline "head" of the "fungus 17" relative to its "base", or of the layer 19 relative to the layer 18, the centering openings 22, made in the layer 21, relative to the monocrystalline studs ("head" of the "fungus" or layer 19) is not critical.

Step 5 (Figure 6)

Is carried out "in situ" a prior cleaning of the surface of the p-type silicon pads exposed during the etching of the openings 22 (step 4). This cleaning essentially consists in the elimination of the native silicon oxide on this surface of the studs, by heating to approximately 1000 ° C. of the wafer in an enclosure under ultra-vacuum (approximately 10⁻¹⁰ Torr), in which then performs the activation of said surface of the pads by caesiation. The caesiation technique can be one of the techniques known per se from the articles cited in the preamble.

Step 6 (Figure 7)

In the same ultra-vacuum enclosure, a layer 23 of phosphor material, for example Zn0, is evaporated in grazing incidence (angle of incidence ϑ less than 15 °), the substrate 14 being rotated around an axis 24 perpendicular to the upper surface of the substrate 14. Evaporation is stopped when the thickness of the layer 23 is sufficient to seal the openings 22. The cathodes (cesized surfaces of layers 17 or 19) are thus trapped in micro-cavities.

Advantageously, the component thus produced can be annealed "in situ" in order to improve the mechanical properties of the layer 23.

Step 7 (Figure 8)

This step is implemented when it is desired to produce a matrix display panel, that is to say a panel comprising a large number of display elements. cathodoluminescent arranged in rows and columns. These elements being of very small dimensions, one can group several of them to form a single luminous point (called "pixel"). In this case, the layers 17A are produced in strips parallel to each other (see also FIG. 3A) to form, for example, the columns of the matrix device. Step 7 then consists in making strips 25 parallel to each other of phosphor material by etching the layer 23 produced during step 6. These strips 25 of phosphor material are perpendicular to the strips 17A and form, for the above example , the rows of the matrix device. Of course, it is also possible to produce a matrix device from the embodiment of FIG. 38 by forming parallel bands between them in the silicon layer p (19,20), then by forming bands in the phosphor material of the same as for the embodiment of FIG. 8. The device shown in FIG. 9 is then obtained.

In the embodiment of FIG. 8, in order to reduce the access resistances of the strips of phosphor material, the upper surface of these strips 25 can be coated with a thin transparent layer 26 made of material which is a good electrical conductor, advantageously of indium tin oxide (ITO).

A light point is obtained by applying on the one hand a voltage between a column and the substrate 14, and on the other hand a voltage between a line and the substrate 14. Of course, as specified above, this light point can be defined by several elementary cathodoluminescent devices: it then suffices that several of these elementary devices are formed over the width of a row and / or of a column. We can thus give any desired shape to this light point.

The matrix display device shown in FIG. 9 is produced, after step 2 (embodiment of FIG. 3B), according to steps 3 to 6 described above for the embodiment of FIG. 3A. These steps result in the formation of the silica layer 27, in which cavities are etched 28. The exposed surfaces of monocrystalline silicon p, cleaned and cesium-coated are referenced 29. The layer of phosphor material is referenced 30. The step 7, for this device of FIG. 9, also consists in forming strips of phosphors. These strips can, as described above, be formed by etching the layer 30 of phosphor material. However, if this phosphor material is sufficiently resistive, the etching of the strips, in order to isolate them from each other, is not necessary. The determination of the lines is then made by depositing a thin and transparent layer, for example of indium tin oxide, in the form of strips 31 parallel to each other (and perpendicular to the columns).

Finally, it is possible to deposit on the device thus produced a layer 32 (covering at least its upper face) of translucent passivating material (for example phosphosilicate glass) so as to isolate this device from external aggressions. This layer 32 has only been shown for the embodiment of FIG. 9, but it is understood that it can also be deposited on the device of FIG. 8.

The component whose manufacturing process has been described above is a display device. The invention is not however limited to such a type of component. If the layer of phosphor material is replaced by a layer of material that is a good electrical conductor, such as molybdenum, and that each individual anode is obtained, microtubes of the triode type are obtained, which can be used to produce integrated circuits, each microtube behaving like a bipolar transistor.

Advantageously, one can deposit a layer of material which will produce a "getter" effect in "sandwich" in the silica layer 21 or 27. The "getter" material can by example be one of the following elements: Ti, Ta, Zr, Ca. The silica layer is then deposited in two steps separated by a step of depositing this "getter" material. This applies to both the visualization components and the microtubes.

Claims (34)

1. Component such as diode, triode or cathodoluminescent display device, flat and integrated, of the cold cathode type formed on a substrate of semiconductor material (14) capable of being brought into a state of negative electronic affinity, characterized by the the fact that it comprises at least one microvolume (22,28) containing a microcathode and autoscealed under vacuum by the anode material (23,25,30). 2. Component according to claim 1, produced as a display device, characterized in that the anode material is a phosphor material. 3. Component according to claim 1 or 2, characterized in that its substrate is made of silicon (14), of n type. 4. Component according to claims 1 or 2, characterized in that its substrate is of n-type gallium arsenide. 5. Component according to one of the preceding claims, characterized in that the surface in a state of negative electronic affinity is the caesiated surface of at least part of the upper face of a layer of substrate at least partially monocrystalline, p-type (17, 19). 6. Component according to claim 5, characterized in that the layer of silicon or gallium arsenide of monocrystalline gall type pa a form of "fungus" (17) whose "foot" in contact with the substrate is surrounded by dielectric (15) on which the rim of the "hat" of this mushroom rests. 7. Component according to claim 5, characterized in that the layer of monocrystalline silicon has a form of pellet (19) whose lower face has a central part in contact with a protuberance (18) of the substrate and a peripheral part in contact with a dielectric layer (15) surrounding said protuberance. 8. Component according to one of claims 6 or 7, characterized in that the layer of p monocrystalline silicon is coplanar with a layer of p polycrystalline silicon (20) laterally surrounding the p monocrystalline silicon. 9. Component according to claim 8, characterized in that a layer of dielectric material (21,27) separates the layer of mono and polycrystalline p silicon from the layer of anode material, the lateral walls of the microvolume being constituted by this dielectric material. 10. Method for manufacturing a flat and integrated component of the cold cathode type formed on a substrate of semiconductor material capable of being brought into a state of negative electronic affinity, used for a silicon substrate, characterized by the fact that it consists of:
- oxidize one face of an n-type silicon substrate, at least partially monocrystalline,
- etch in the silica of this face at least one opening,
depositing p-type silicon on the silica and on the parts of the substrate exposed so as to have a very flat surface after deposition, this silicon being monocrystalline in the openings and polycrystalline on the silica,
- deposit a layer of dielectric material,
- etch in this last layer openings substantially in the axis of the aforementioned openings until reaching the p-type silicon layer,
- carry out "in situ" cleaning of the surfaces of the p-type silicon layer exposed,
- carry out a treatment bringing the cleaned surfaces into a state of negative electronic affinity,
- evaporate under high vacuum and grazing incidence a layer of anode material, the substrate being rotated around an axis perpendicular to the surface of this substrate, until the microcavity thus sealed. 11. Method according to claim 10, characterized in that the p-type silicon layer is deposited by vapor phase epitaxy. 12. Method according to claim 11, characterized in that the deposition is made by cracking molecules of a gaseous mixture SiH₄ + H₂ + B₂H₆ at atmospheric pressure at a temperature of about 900 to 1060 ° C. 13. Method according to claim 11, characterized in that the deposition is made by selective epitaxy using a gaseous mixture SiH₄ + HCl + H₂ + B₂H₆ at atmospheric pressure or at reduced pressure at a temperature between 900 and 1060 ° C about. 14. Method according to claim 13, characterized in that when the openings in the silica are filled, the inlet of the HCl gas is cut off so as to obtain a uniform deposit. 15. The method of claim 14, characterized in that the total thickness of the silicon deposit p is about 1 micrometer. 16. The method of claim 11, characterized in that the openings made in the silica are first filled with n-type monocrystalline silicon, without depositing it on the silica, then the type silicon deposition is carried out. p. 17. The method of claim 16, characterized in that the deposition of n-type monocrystalline silicon is carried out using a gas mixture SiH₄ + HCl + PH₃. 18. The method of claim 16 or 17, characterized in that the deposition of p-type silicon is carried out using a gaseous mixture SiH₄ + B₂H₆. 19. Method according to one of claims 16 to 18, characterized by the fact that the pa type silicon layer has a thickness of between 1000 and 5000 Å approximately. 20. Method according to one of claims 10 to 17, characterized in that the deposition of dielectric material is made at a temperature between about 250 and 900 ° C. 21. The method of claim 20, characterized in that the dielectric material is furrow, the deposition of silica being made by pyrolysis of SiH₂Cl₂ + N₂0 at a temperature between about 850 and 900 ° C. 22. Method according to one of claims 10 to 20, characterized in that the dielectric material is one of the following: Si₃N₄, Al₂0₃, Zr0₂. 23. Method according to one of claims 10 to 22, characterized in that the cleaning of the silicon surfaces exposed during the production of the openings in the dielectric material is carried out in an enclosure under ultra-vacuum at a temperature d 'about 1000 ° C. 24. The method of claim 23, characterized in that the state of negative electronic affinity of the exposed and cleaned surfaces is obtained by cessation under ultra-vacuum. 25. Method according to one of claims 10 to 24, used for a cathodoluminescent component, characterized in that the anode material is made of phosphor material. 26. The method of claim 25, characterized in that the phosphor material is zinc oxide. 27. The method of claim 25 or 26, characterized in that one carries out an "in situ" annealing of the components so as to improve the mechanical properties of the anode. 28. Method according to one of claims 25 to 27, for producing a matrix display device, characterized in that the silicon layer p is formed in strips parallel to each other, and that one etches in the layer of phosphor material of the bands parallel to each other and perpendicular to the bands of silicon p. 29. Method according to one of claims 25 to 27, for producing a matrix display device, characterized in that the layer of silicon p is formed in strips parallel to each other and which is deposited on the layer of material resistive phosphor of the parallel strips between them of a transparent conductive material, these strips being perpendicular to the silicon strips p. 30. The method of claim 28, characterized in that a thin layer of transparent conductive material is deposited on the strips of phosphor material. 31. Method according to one of claims 29 or 30, characterized in that the transparent conductive material is indium tin oxide. 32. Method according to one of claims 10 to 31, characterized in that a translucent passivating material is deposited on the component. 33. Method according to claim 32, characterized in that the translucent passivating material is a phosphosilicate glass. 34. Method according to one of claims 9 to 29, characterized in that the deposition of the dielectric material layer (21,27) is carried out in two deposition steps separated each time by a deposition step a layer of a material that will produce a getter effect.

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