EP0362017A1 - Vorrichtung, wie Diode, Triode oder flache und integrierte kathodolumineszierende Anzeigevorrichtung und Herstellungsverfahren - Google Patents

Vorrichtung, wie Diode, Triode oder flache und integrierte kathodolumineszierende Anzeigevorrichtung und Herstellungsverfahren Download PDF

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Publication number
EP0362017A1
EP0362017A1 EP89402538A EP89402538A EP0362017A1 EP 0362017 A1 EP0362017 A1 EP 0362017A1 EP 89402538 A EP89402538 A EP 89402538A EP 89402538 A EP89402538 A EP 89402538A EP 0362017 A1 EP0362017 A1 EP 0362017A1
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EP
European Patent Office
Prior art keywords
layer
silicon
substrate
type
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89402538A
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English (en)
French (fr)
Inventor
Jean Olivier
Didier Pribat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thomson CSF SA
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Filing date
Publication date
Application filed by Thomson CSF SA filed Critical Thomson CSF SA
Publication of EP0362017A1 publication Critical patent/EP0362017A1/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02—Manufacture of electrodes or electrode systems
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J21/00—Vacuum tubes
    • H01J21/02—Tubes with a single discharge path
    • H01J21/06—Tubes with a single discharge path having electrostatic control means only
    • H01J21/10—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode
    • H01J21/105—Tubes with a single discharge path having electrostatic control means only with one or more immovable internal control electrodes, e.g. triode, pentode, octode with microengineered cathode and control electrodes, e.g. Spindt-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00—Cathode ray tubes; Electron beam tubes
    • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/10—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes
    • H01J31/12—Image or pattern display tubes, i.e. having electrical input and optical output; Flying-spot tubes for scanning purposes with luminescent screen
    • H01J31/123—Flat display tubes
    • H01J31/125—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection
    • H01J31/127—Flat display tubes provided with control means permitting the electron beam to reach selected parts of the screen, e.g. digital selection using large area or array sources, i.e. essentially a source for each pixel group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2201/00—Electrodes common to discharge tubes
    • H01J2201/30—Cold cathodes
    • H01J2201/308—Semiconductor cathodes, e.g. having PN junction layers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking

Definitions

  • the present invention relates to a component such as a diode, a triode, or a flat and integrated cathodoluminescent display device, and to a method of manufacturing such a device.
  • the p-type silicon layer thus treated is placed on an n-type substrate, and if the junction thus obtained is directly polarized, electrons are injected which are emitted in a vacuum after crossing the layer of type p.
  • E.S. Kohn used this type of cathode to reproduce on a screen supporting a phosphor and placed 0.5 mm from the cathode plane, characters etched in silicon and treated according to the preceding description in negative electronic affinity.
  • the subject of the present invention is a component such as a diode or a display device of the cold cathode type in p-type semiconductor treated so as to have a negative affinity, not requiring the creation of a vacuum. grown in a relatively large volume which can be produced automatically in series, and at a reasonable cost price.
  • the present invention also relates to a method of manufacturing such a component.
  • the component according to the invention comprises at least one microvolume containing a microcathode and autoscealed under vacuum by the anode material.
  • the process for manufacturing a component in accordance with the invention, a component of the cold cathode type formed on a substrate made of semiconductor material capable of being brought into a state of negative electronic affinity this process consists, when this semiconductor material is silicon, at : oxidizing one face of an n-type silicon substrate, this substrate being at least partially monocrystalline, - etch in the silica of this face at least one opening, depositing p-type silicon on the silica and on the parts of the substrate exposed so as to have a very flat surface after deposition, this silicon being monocrystalline in the openings and polycrystalline on the silica, - deposit a layer of dielectric material, - etch in this last layer openings substantially in the axis of the aforementioned openings until reaching the p-type silicon layer, - carry out "in situ" cleaning of the surfaces of the p-type silicon layer exposed, - carry out a treatment bringing the cleaned surfaces, in a state of negative electronic affinity, - Evaporate under high vacuum and in grazing incidence
  • the invention is described below with reference to the production of a light micropoint and display panels comprising a very large number of such light micropoints, but it is understood that it is not limited to such a component, and that it can be implemented for the production of other cold cathode components such as diodes or triodes (the triodes being taken in the sense of "components with three electrodes").
  • FIG. 1 shows a light micropoint 1 according to the invention.
  • This component 1 comprises a substrate 2 which is in this case made of n-type silicon, the underside of which has a coating 3 of material which is a good electrical conductor (ohmic contact), making it possible to connect the substrate 2 constituting the to an output conductor.
  • the substrate is made of AsGa.
  • the upper face of the substrate 2 is covered with a layer 4 of silica (Si02) or any other dielectric (Si3N4, Al203 ...), with the exception of an opening 5.
  • the substrate 2 must be at least monocrystalline at the opening 5.
  • the layer 4 and the surface of the substrate 2 constituting the opening 5 are covered with a p-type silicon layer 6.
  • the layer 6 In the zone of the opening 5, the layer 6 has, in a volume 7, a monocrystalline structure. This volume 7 has roughly the shape of a micro-fungus, the base of which corresponds to the opening 5.
  • the rest of the layer 6 deposited on the dielectric layer 4 has a polycrystalline structure. The reason for this difference in structure of layer 6 will appear below in the description of the method for manufacturing the light micropoint.
  • Layer 6 is coated with a layer 8 of silica or another dielectric, with the exception of an opening 9 coaxial with the opening 5 and of the same diameter as the latter.
  • the surface 10 of the layer 6 not covered by the layer 8 is treated so as to have a negative electronic affinity, for example by caesiation.
  • a layer 11 of anode material largely covers the opening 9 by sealing it, a high vacuum (of the order of 10 ⁇ 10 Torr) prevailing in the microvolume determined by the opening 9 sealed at one end by the layer 6 , and to the other by the layer 11.
  • the layer 11 is made of a phosphor material, such as zinc oxide.
  • the layer 11 is simply an electrically conductive material.
  • the layers 3, 6 and 11 are connected to suitably polarized voltage sources 12, 13.
  • Component 1 can operate in the ambient atmosphere since the vacuum is maintained in the microvolume thanks to the sealing effected by the anode material.
  • a wafer 14 of standard n-type semiconductor material Preferably, this material is for example silicon (100) or (110) or (111), because this material exists in the form of large substrates.
  • the surface of the wafer 14 is oxidized until an insulating layer 15 of silica having for example a thickness of approximately 1000 to 1500 ⁇ .
  • Openings 16 are etched in the silica using an appropriate lithographic technique, for example optical or electronic. In top view, these openings 16 can be of any shape: circular, square, rectangular, oblong ... The dimensions of this shape seen from above are of the order of a micrometer. If the shape seen from above is circular, its diameter will be of the order of a micrometer.
  • cathodoluminescent components one or more such components arranged side by side are used to define a light pixel.
  • the surfaces of the wafer 14 previously exposed by making the openings 16 in the silica are covered with p-type monocrystalline silicon (crystal plane 100), by vapor phase epitaxy (in English: “Chemical Vapor Deposition”). It is important that the surface of the silicon deposit is flat. It is this surface which will be brought into the state of negative electronic affinity in a subsequent step (step 5).
  • the invention provides two embodiments characterized by different deposition conditions.
  • the first mode consists in cracking the molecules of the SiH4 + H2 + B2H6 mixture at a temperature of around 900 to 1060 ° C and at atmospheric pressure (method called "APCVD” with AP “atmospheric pressure ", and CVD already explained above).
  • the B2H6 gas makes it possible to obtain p-type doping of the silicon deposit.
  • the growth of the deposit 17 on the substrate 14 left free by the openings 16 is monocrystalline, of the same orientation (plane 100) as the substrate 14, therefore making the deposit 17 suitable for being brought into the state of negative electronic affinity.
  • the deposit 17A of silicon is polycrystalline on the silica.
  • the growth rate of the deposit in one direction perpendicular to the surface plane of the substrate being greater on the monocrystalline areas 16 than on the silica 15, one arrives after a certain time, which depends on the thickness of the starting silica layer 15, at a thickness deposit practically uniform over the entire wafer.
  • the silicon deposit (17 + 17A) can then be described as "planarized".
  • the deposits (17 + 17A) can be given the shape of parallel bands on the 'axis of which the deposits 17 are aligned and, preferably, regularly spaced. These strips can be obtained by etching from layer 17A to layer 15. This etching forms in the layer 17A grooves parallel to the axes 17B on which are deposited columns 17, these grooves being each time equidistant from two consecutive axes of deposition columns 17.
  • These grooves are then filled with silica 17C using a conventional deposition method such as LTO or HTO (LTO: Low Temperature Oxide; HTO; High Temperature Oxide) in combination with a "lift-off” technique "allowing the silica deposit to be easily removed on pads 17 and 17A.
  • LTO Low Temperature Oxide
  • HTO High Temperature Oxide
  • Another method consists in depositing a uniform layer of silicon nitride (Si3N4), in etching in this layer bands such as 17C and then practicing a localized oxidation of the underlying silicon. The silicon nitride is then removed by selective chemical attack (LOCOS type process).
  • the second embodiment, illustrated in FIG. 3B, is based on the technique of selective epitaxy, and is carried out at atmospheric pressure (APCVD) or else under reduced pressure (RP CVD, with RP for "reduced pressure") at a temperature between 900 and 1060 ° C. approximately. It uses a gas mixture SiH4 + HCl + H2 + B2H6 which makes it possible to work near thermodynamic equilibrium.
  • APCVD atmospheric pressure
  • RP CVD reduced pressure
  • the selectivity of the deposit is governed by a mechanism of selective nucleation by which the growth of silicon is possible on surfaces with a low nucleation barrier, such as silicon (100), and prohibited on a foreign surface such as silica.
  • a mechanism of selective nucleation by which the growth of silicon is possible on surfaces with a low nucleation barrier, such as silicon (100), and prohibited on a foreign surface such as silica For more details, refer to the article by JO BORLAND and CI DROWLEY published in "Solid State Technology" of August 1985, page 141, as well as to the article by L. KARAPIPERIS and collaborators published in "Proceedings of the 18 th Conference on Solid State Devices and Materials ", Tokyo 1986, page 713.
  • the epitaxy is performed on the substrate 14 covered with the layer 15 and comprising the holes 16, as shown in FIG. 2.
  • the holes 16 are filled with monocrystalline p-type silicon 18, the arrival of the HCl gas is cut off, which removes the selectivity and allows the deposition of silicon also on the layer 15 but polycrystalline, the deposit then being uniform in thickness over the entire surface of the wafer (surfaces 18 and 15).
  • the total thickness of the deposit is of the order of 1 micrometer.
  • the deposit 19 on the surfaces 18 is monocrystalline p silicon, and slightly protrudes from these surfaces, while the deposit 20 on the remaining surfaces 15 is polycrystalline p silicon.
  • the thickness of the layers 17, 18 and 19 of monocrystalline silicon p is minimized. Components are obtained which operate more quickly because their response time is mainly a function of the transfer time of the minority carriers in the p-type silicon zone (layers 17, 18 and 19).
  • the method for producing this variant according to the second embodiment is as follows.
  • the openings made in the silica 15 are selectively filled with n-type monocrystalline silicon, without depositing it on the silica.
  • gas streams comprising for example SiH4 + HCl + H2 + PH3 are used.
  • the PH3 component is used for doping type n.
  • the deposition of silicon p is then carried out, non-selectively this time, this silicon being monocrystalline on the layer of silicon n and polycrystalline on the layer of silica, using a gaseous mixture SiH4 + B6H6.
  • the silicon layer p thus obtained can have a thickness of between 1,000 and 5,000 ⁇ approximately.
  • This method also makes it possible to produce, by localized oxidation (for example by using the method known under the name of "LOCOS"), silicon bands p (forming columns of a matrix display device similar to that shown in Figure 9) isolated from each other.
  • LOC localized oxidation
  • FIG. 4A shows the structure of FIG. 3A with the substrate 14 and the layers 15, 17 and 17A, but it is understood that the structure of the figure could also have been represented there. 3B with the substrate 14 and the layers 15,18,19 and 20.
  • Figures 5 to 8 described below also include the structure of Figure 3A, only Figure 9 includes the structure of Figure 38.
  • the silica layer (HTO) 21 is preferably carried out by a high temperature process (HTO), for example by pyrolysis of a gaseous mixture SiH2Cl2 + N20 at a temperature of at least 250 ° C, and advantageously between 850 and 900 ° C approx.
  • HTO high temperature process
  • the silica layer thus obtained has good mechanical and electrical properties.
  • the layer 21 can be formed from dielectric materials such as Si3N4, Al203, Zr02, etc., using appropriate deposition techniques.
  • step 4 Is carried out "in situ" a prior cleaning of the surface of the p-type silicon pads exposed during the etching of the openings 22 (step 4).
  • This cleaning essentially consists in the elimination of the native silicon oxide on this surface of the studs, by heating to approximately 1000 ° C. of the wafer in an enclosure under ultra-vacuum (approximately 10 ⁇ 10 Torr), in which then performs the activation of said surface of the pads by caesiation.
  • the caesiation technique can be one of the techniques known per se from the articles cited in the preamble.
  • a layer 23 of phosphor material for example Zn0, is evaporated in grazing incidence (angle of incidence ⁇ less than 15 °), the substrate 14 being rotated around an axis 24 perpendicular to the upper surface of the substrate 14. Evaporation is stopped when the thickness of the layer 23 is sufficient to seal the openings 22.
  • the cathodes (cesized surfaces of layers 17 or 19) are thus trapped in micro-cavities.
  • the component thus produced can be annealed "in situ" in order to improve the mechanical properties of the layer 23.
  • This step is implemented when it is desired to produce a matrix display panel, that is to say a panel comprising a large number of display elements. cathodoluminescent arranged in rows and columns. These elements being of very small dimensions, one can group several of them to form a single luminous point (called "pixel").
  • the layers 17A are produced in strips parallel to each other (see also FIG. 3A) to form, for example, the columns of the matrix device.
  • Step 7 then consists in making strips 25 parallel to each other of phosphor material by etching the layer 23 produced during step 6. These strips 25 of phosphor material are perpendicular to the strips 17A and form, for the above example , the rows of the matrix device.
  • the upper surface of these strips 25 can be coated with a thin transparent layer 26 made of material which is a good electrical conductor, advantageously of indium tin oxide (ITO).
  • ITO indium tin oxide
  • a light point is obtained by applying on the one hand a voltage between a column and the substrate 14, and on the other hand a voltage between a line and the substrate 14.
  • this light point can be defined by several elementary cathodoluminescent devices: it then suffices that several of these elementary devices are formed over the width of a row and / or of a column. We can thus give any desired shape to this light point.
  • the matrix display device shown in FIG. 9 is produced, after step 2 (embodiment of FIG. 3B), according to steps 3 to 6 described above for the embodiment of FIG. 3A. These steps result in the formation of the silica layer 27, in which cavities are etched 28. The exposed surfaces of monocrystalline silicon p, cleaned and cesium-coated are referenced 29. The layer of phosphor material is referenced 30.
  • the step 7, for this device of FIG. 9, also consists in forming strips of phosphors. These strips can, as described above, be formed by etching the layer 30 of phosphor material. However, if this phosphor material is sufficiently resistive, the etching of the strips, in order to isolate them from each other, is not necessary.
  • the determination of the lines is then made by depositing a thin and transparent layer, for example of indium tin oxide, in the form of strips 31 parallel to each other (and perpendicular to the columns).
  • a layer 32 (covering at least its upper face) of translucent passivating material (for example phosphosilicate glass) so as to isolate this device from external aggressions.
  • This layer 32 has only been shown for the embodiment of FIG. 9, but it is understood that it can also be deposited on the device of FIG. 8.
  • the component whose manufacturing process has been described above is a display device.
  • the invention is not however limited to such a type of component. If the layer of phosphor material is replaced by a layer of material that is a good electrical conductor, such as molybdenum, and that each individual anode is obtained, microtubes of the triode type are obtained, which can be used to produce integrated circuits, each microtube behaving like a bipolar transistor.
  • the "getter” material can by example be one of the following elements: Ti, Ta, Zr, Ca.
  • the silica layer is then deposited in two steps separated by a step of depositing this "getter” material. This applies to both the visualization components and the microtubes.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Cold Cathode And The Manufacture (AREA)
  • Electroluminescent Light Sources (AREA)
  • Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
EP89402538A 1988-09-23 1989-09-15 Vorrichtung, wie Diode, Triode oder flache und integrierte kathodolumineszierende Anzeigevorrichtung und Herstellungsverfahren Withdrawn EP0362017A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8812470A FR2637126B1 (fr) 1988-09-23 1988-09-23 Composant tel que diode, triode ou dispositif d'affichage cathodoluminescent plat et integre, et procede de fabrication
FR8812470 1988-09-23

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EP0362017A1 true EP0362017A1 (de) 1990-04-04

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EP89402538A Withdrawn EP0362017A1 (de) 1988-09-23 1989-09-15 Vorrichtung, wie Diode, Triode oder flache und integrierte kathodolumineszierende Anzeigevorrichtung und Herstellungsverfahren

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US (1) US4986787A (de)
EP (1) EP0362017A1 (de)
JP (1) JPH02142041A (de)
FR (1) FR2637126B1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0686992A1 (de) * 1994-06-10 1995-12-13 Texas Instruments Incorporated Anzeigevorrichtung
EP0676083A4 (de) * 1992-12-23 1996-12-27 Si Diamond Techn Inc Flachanzeigevorrichtung in diodestruktur.
EP1239443A1 (de) * 2001-03-09 2002-09-11 Commissariat A L'energie Atomique Elektronenemissionsflachanzeige mit integrierter Anode-Steuervorrichtung

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Publication number Priority date Publication date Assignee Title
US5110757A (en) * 1990-12-19 1992-05-05 North American Philips Corp. Formation of composite monosilicon/polysilicon layer using reduced-temperature two-step silicon deposition
DE4041276C1 (de) * 1990-12-21 1992-02-27 Siemens Ag, 8000 Muenchen, De
JP3423511B2 (ja) * 1994-12-14 2003-07-07 キヤノン株式会社 画像形成装置及びゲッタ材の活性化方法
KR100404171B1 (ko) * 1996-12-27 2004-03-18 엘지전자 주식회사 엔이에이 성질을 갖는 실리콘 표면의 패턴 형성방법
FR2780808B1 (fr) 1998-07-03 2001-08-10 Thomson Csf Dispositif a emission de champ et procedes de fabrication
US20040005927A1 (en) * 2002-04-22 2004-01-08 Bonilla Victor G. Facility for remote computer controlled racing

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US3921022A (en) * 1974-09-03 1975-11-18 Rca Corp Field emitting device and method of making same
DE3224218A1 (de) * 1981-06-29 1983-01-13 Rockwell International Corp., 90245 El Segundo, Calif. Silicium-vakuum-elektronenvorrichtung
US4721885A (en) * 1987-02-11 1988-01-26 Sri International Very high speed integrated microelectronic tubes
JPS63187535A (ja) * 1987-01-28 1988-08-03 Canon Inc 冷陰極真空管
EP0278405A2 (de) * 1987-02-06 1988-08-17 Canon Kabushiki Kaisha Elektronen emittierendes Element und dessen Herstellungsverfahren
EP0306173A1 (de) * 1987-09-04 1989-03-08 THE GENERAL ELECTRIC COMPANY, p.l.c. Feldemissions-Vorrichtung

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US3755704A (en) * 1970-02-06 1973-08-28 Stanford Research Inst Field emission cathode structures and devices utilizing such structures
US3789471A (en) * 1970-02-06 1974-02-05 Stanford Research Inst Field emission cathode structures, devices utilizing such structures, and methods of producing such structures
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US3921022A (en) * 1974-09-03 1975-11-18 Rca Corp Field emitting device and method of making same
DE3224218A1 (de) * 1981-06-29 1983-01-13 Rockwell International Corp., 90245 El Segundo, Calif. Silicium-vakuum-elektronenvorrichtung
JPS63187535A (ja) * 1987-01-28 1988-08-03 Canon Inc 冷陰極真空管
EP0278405A2 (de) * 1987-02-06 1988-08-17 Canon Kabushiki Kaisha Elektronen emittierendes Element und dessen Herstellungsverfahren
US4721885A (en) * 1987-02-11 1988-01-26 Sri International Very high speed integrated microelectronic tubes
EP0306173A1 (de) * 1987-09-04 1989-03-08 THE GENERAL ELECTRIC COMPANY, p.l.c. Feldemissions-Vorrichtung

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0676083A4 (de) * 1992-12-23 1996-12-27 Si Diamond Techn Inc Flachanzeigevorrichtung in diodestruktur.
EP0686992A1 (de) * 1994-06-10 1995-12-13 Texas Instruments Incorporated Anzeigevorrichtung
EP1239443A1 (de) * 2001-03-09 2002-09-11 Commissariat A L'energie Atomique Elektronenemissionsflachanzeige mit integrierter Anode-Steuervorrichtung
FR2821982A1 (fr) * 2001-03-09 2002-09-13 Commissariat Energie Atomique Ecran plat a emission electronique et a dispositif integre de commande d'anode
US6876344B2 (en) 2001-03-09 2005-04-05 Commissariat A L 'energie Atomique Flat thermionic emission screen and with integrated anode control device

Also Published As

Publication number Publication date
JPH02142041A (ja) 1990-05-31
FR2637126A1 (fr) 1990-03-30
US4986787A (en) 1991-01-22
FR2637126B1 (fr) 1992-05-07

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