EP0367729A3 - Verfahren zur Herstellung von Isolationsstrukturen mit Gräben in einem Substrat aus Silizium für CMOS- und NMOS-Anordnungen - Google Patents

Verfahren zur Herstellung von Isolationsstrukturen mit Gräben in einem Substrat aus Silizium für CMOS- und NMOS-Anordnungen Download PDF

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Publication number
EP0367729A3
EP0367729A3 EP19890830446 EP89830446A EP0367729A3 EP 0367729 A3 EP0367729 A3 EP 0367729A3 EP 19890830446 EP19890830446 EP 19890830446 EP 89830446 A EP89830446 A EP 89830446A EP 0367729 A3 EP0367729 A3 EP 0367729A3
Authority
EP
European Patent Office
Prior art keywords
cmos
silicon substrate
isolation structures
thermal oxide
nmos devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19890830446
Other languages
English (en)
French (fr)
Other versions
EP0367729A2 (de
Inventor
Orio Bellezza
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of EP0367729A2 publication Critical patent/EP0367729A2/de
Publication of EP0367729A3 publication Critical patent/EP0367729A3/de
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0163—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including enhancement-mode IGFETs and depletion-mode IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
EP19890830446 1988-11-03 1989-10-16 Verfahren zur Herstellung von Isolationsstrukturen mit Gräben in einem Substrat aus Silizium für CMOS- und NMOS-Anordnungen Withdrawn EP0367729A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT8367588 1988-11-03
IT8883675A IT1225625B (it) 1988-11-03 1988-11-03 Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos.

Publications (2)

Publication Number Publication Date
EP0367729A2 EP0367729A2 (de) 1990-05-09
EP0367729A3 true EP0367729A3 (de) 1991-01-09

Family

ID=11323767

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19890830446 Withdrawn EP0367729A3 (de) 1988-11-03 1989-10-16 Verfahren zur Herstellung von Isolationsstrukturen mit Gräben in einem Substrat aus Silizium für CMOS- und NMOS-Anordnungen

Country Status (3)

Country Link
EP (1) EP0367729A3 (de)
JP (1) JPH02172254A (de)
IT (1) IT1225625B (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2870054B2 (ja) * 1989-10-25 1999-03-10 ソニー株式会社 半導体装置の製造方法
EP0445471A3 (en) * 1990-03-06 1994-10-26 Digital Equipment Corp Method of forming isolation trenches in a semiconductor substrate
US5273934A (en) * 1991-06-19 1993-12-28 Siemens Aktiengesellschaft Method for producing a doped region in a substrate
US5308790A (en) * 1992-10-16 1994-05-03 Ncr Corporation Selective sidewall diffusion process using doped SOG
US9515072B2 (en) * 2014-12-26 2016-12-06 Taiwan Semiconductor Manufacturing Company Ltd. FinFET structure and method for manufacturing thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986003620A2 (en) * 1984-12-10 1986-06-19 Ncr Corporation Process for forming diffusion regions in a semiconductor substrate
WO1986004454A1 (en) * 1985-01-25 1986-07-31 American Telephone & Telegraph Company Controlled boron doping of silicon
EP0221394A2 (de) * 1985-10-31 1987-05-13 International Business Machines Corporation Verfahren zur Herstellung einer integrierten Schaltung
EP0259605A1 (de) * 1986-08-29 1988-03-16 Siemens Aktiengesellschaft Verfahren zum Erzeugen einer definierten Dotierung in Seitenwänden und Böden von in Halbleitersubstrate eingeätzten Gräben

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986003620A2 (en) * 1984-12-10 1986-06-19 Ncr Corporation Process for forming diffusion regions in a semiconductor substrate
WO1986004454A1 (en) * 1985-01-25 1986-07-31 American Telephone & Telegraph Company Controlled boron doping of silicon
EP0221394A2 (de) * 1985-10-31 1987-05-13 International Business Machines Corporation Verfahren zur Herstellung einer integrierten Schaltung
EP0259605A1 (de) * 1986-08-29 1988-03-16 Siemens Aktiengesellschaft Verfahren zum Erzeugen einer definierten Dotierung in Seitenwänden und Böden von in Halbleitersubstrate eingeätzten Gräben

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 18, no. 6, November 1975, NEW YORK US pages 1854 - 1855; G.T. GALYON.: "ISOLATION OF DEVICE COMPONENTS." *
JOURNAL OF CRYSTAL GROWTH. vol. 17, 1972, AMSTERDAM NL pages 276 - 287; D.M. BROWN ET AL.: "CHARACTERISTICS OF DOPED OXIDES AND THEIR USE IN SILICON DEVICE FABRICATION." *

Also Published As

Publication number Publication date
IT8883675A0 (it) 1988-11-03
EP0367729A2 (de) 1990-05-09
IT1225625B (it) 1990-11-22
JPH02172254A (ja) 1990-07-03

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