EP0369964A2 - Interface pour formats de données multiples - Google Patents

Interface pour formats de données multiples Download PDF

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Publication number
EP0369964A2
EP0369964A2 EP89850378A EP89850378A EP0369964A2 EP 0369964 A2 EP0369964 A2 EP 0369964A2 EP 89850378 A EP89850378 A EP 89850378A EP 89850378 A EP89850378 A EP 89850378A EP 0369964 A2 EP0369964 A2 EP 0369964A2
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EP
European Patent Office
Prior art keywords
data
bus
word
format
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP89850378A
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German (de)
English (en)
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EP0369964A3 (fr
Inventor
Roger Ned Bailey
Robert Lockwood Mansfield
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
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International Business Machines Corp
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Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0369964A2 publication Critical patent/EP0369964A2/fr
Publication of EP0369964A3 publication Critical patent/EP0369964A3/fr
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Definitions

  • the present invention relates to data processing systems and more specifically to an information bus interface for the transfer of information in a data processing system.
  • Data processing systems often include information buses for the transfer of information between a central processing unit and peripheral devices or between several central process­ing units. Traditionally, these information buses will transfer data in single words serially over the information bus. However, as the requirements for information transfer rates for processing units increase, this technique will not be able to provide the data needed at the rate required.
  • U.S. Patent No. 4,747,070 entitled “Reconfigurable Memory System” discloses a memory system and controller where the memory includes a capability to provide serial access or parallel access. In the parallel access, the memory is configured with an address translator which chooses one of several bank output buses as the memory outputs to the system processor. In another embodiment, a cache is provided to store the information on the non-selected bank output buses.
  • U.S. Patent No. 4,370,712 entitled “Memory Controller with Address Independent Burst Mode Capability” discloses a memory controller that includes the capability to provide a number of words starting at any specific word boundary from several memory modules.
  • IBM Technical Disclosure Bulletin , Vol. 28, No. 1, June, 1985, pages 20 - 23, entitled “Dual Port, Dual Data Width Random-Access Memory Controller” discloses an invention that permits two processors to asynchronously access a common memory even though the processors have different data widths.
  • multiple data word buses are provided in the information bus.
  • different data formats are also provided wherein the first word in one format will appear on a first bus wherein in a second format the first data word will appear on the second bus.
  • an apparatus for interfacing with a parallel data bus transferring infor­mation in multiple formats inconsists a control circuit that receives or sends control signals from or to the parallel bus for regulating data transfer and for specifying one of plurality of formats.
  • An addressing circuit is provided that his connected to the control circuit for computing addresses for each of the data that is received or sent according to the specified format.
  • An accessing circuit connected to the bus control circuit and addressing circuit is also provided for storing or retrieving data for the bus according to the computed address.
  • the accessing means stores data to or receives data from a circuit that serially stores the data according to the computed address.
  • the addressing circuit computes the addresses according to either a first format having the first data received on a first data bus, or a second format having the first data word on a second data bus.
  • the first format specifies a single word transfer and the second format speci­fies a string transfer or transfer of several data words serially.
  • a processor architecture is provided that is connected by input/output controllers to a serial input/output bus.
  • This bus is a high speed eight byte wide address and data bus. Once an operation has started on this bus, according to its convention it must run until completion. In other words, once a transfer has begun, it cannot be suspended.
  • the input/output controllers that are attached to this bus are then required to buffer all data to or from the bus for its respective processor.
  • Figure 1 illustrates a simple block diagram of such a structure.
  • processors 10, 12 and 14 are interconnected by an information bus 16.
  • This information bus 16 provides address data and control signals for the transfer of information between processors 10, 12 and 14.
  • This invention addresses the bus interface control circuitry that provides for the buffering of data.
  • FIG. 2 is a block diagram of the input/output controller for the information bus.
  • the information bus consists of a control and address bus 22 connected to control logic 35.
  • Data buses 20 and 24 are connected to the multi-port register file 30. Data buses 20 and 24 provide both input and output capability for the data words on the information bus.
  • Control logic 35 is connected via lines 28 and 26 to the multi-port register file to provide read and write addresses and the read and write control signals (rd adr 0, rd adr 1, w adr 0, and w adr 1).
  • the multi-port data file provides data to slave processor 36 via line 34 and receives address information from slave processor 36 via line 32.
  • Figures 3 and 4 are timing diagrams illustrating the single word write format and string write format respectively.
  • an address valid signal on line 50 is provided at time 60.
  • the address valid signal is provided to the control logic 35.
  • the control bus line 54 receives a "00" at time 64.
  • the bus unit ID "buid” is provided at time 66. This is the identifier for the specific bus unit.
  • data word 1 on line 58 provides the effective address at time 70.
  • the effective address is the address in the register file 30 for the storage of the data.
  • the data valid signal, line 52, is provided at time 62.
  • the contents of data word 0, line 56, at time 68 is a don't care condition.
  • Data word 1, line 58, provides the word zero at time 72 (i.e., the single word being written).
  • a string write format is illustrated.
  • a string write provides a contiguous transfer of words.
  • the address valid signal on line 74 is active during time period 84.
  • the control bus signal on line 78 provides a "00" at time 88.
  • the bus unit identifier (buid) is provided at time 90.
  • the effective address is provided at time 96.
  • the data word 0 contains word 0 at time 92 and word 2 at time 94.
  • data word 1 provides word 1 at time 98 and word 3 at time 99.
  • Figures 5 and 6 illustrate the timing diagrams for the single word read and string read formats respectively.
  • the address valid signal, line 100 is active at time 110.
  • the control bus, on line 104 provides an "80" at time 114.
  • the bus unit identifier (buid) is provided at time 118 on the data word 0 line, line 106.
  • the data word 1 bus, line 108 provides the effec­tive address.
  • the data valid line, line 102 is activated by the device being read at time 112.
  • the control bus, line 104 provides the reply indication at time 116.
  • On the data word 0 line, line 106 a "00" is provided as a "don't care" signal.
  • the read word (word 0) is provided at time 124.
  • the address valid signal, line 126 is provided at time 136.
  • time 140 the control bus line, line 130, provides a "3".
  • the data word 0 line, line 132 provides the bus unit identifier (buid) at time 146 and the data word 1 line, line 134, provides the effective address at time 152.
  • the data valid line, line 128, is activated at time 138 by the device being read.
  • the first reply indication is provided on the control bus 130 at time 142 indicating that the data word 0 line, line 132, contains word 0 at time 148 and the data word 1 line, line 134, contains word 1 at time 154.
  • the second reply signal on the control bus line 130 at time 144 indicates that the data word 0 line 132 contains word 2 at time 150 and that the data word 1 line, line 134, contains word 3 at time 156.
  • Figure 7a illustrates the 32 bit format during the address cycle and data cycle for the single word read/write operations discussed in Figures 3 and 5.
  • the bus unit identifier 160 is provided together with the effective address 162 and the control word 164.
  • the control word specifies whether the operation is a read or write, a single word or string operation and if a string, the byte count.
  • the contents on the data word 0 line is a don't care 166 and the contents of the data word 1 bus is the data word (word 0) 168.
  • the control word 170 is a "00".
  • Figure 7b illustrates the string read/write format.
  • the bus unit identifier 172 is provided on the data word 0 line 172 and the effective address 174 is provided on the data word 1 line.
  • the control word 176 is provided to specify the type of operation and the byte count.
  • the first word (word 0) 178 is provided on the data word 0 line and the second word (word 1) 180 is provided on the data word 1 line.
  • the control word 182 is set to "00".
  • the third word (word 2) 184 is provided on the data word 0 line and the fourth word (word 3) 186 is provided on the data word 1 line. Again, a "00" is provided as the control word 188.
  • the multi-port register file 30 ( Figure 1) always stores the first read word in the first read word location 190 even though the first word in a single word read operation appears on the data word 1 bus and in the string read operation appears on the data word 0 bus. In a string operation the data words are stored as illustrated in Figure 7.
  • Figure 8 illustrates the control flow for the storage of the data words in the multi-port register file.
  • the controller in the multi-port register file 30 ( Figure 1) provides the address for storing the data word in the register file according to the format of the information transfer.
  • step 200 determines whether the address valid line is active. If not, the controller waits until the address valid line is active. When active, the controller determines, in step 202, if the appropriate bus unit identifier is present. In this example, "80" is the identifier for the present controller. If the bus unit identifier is not the identifier for the controller, the controller returns to step 200.
  • step 204 determines from the control line whether or not the information transfer is a string transfer. If the transfer is not a string transfer, the controller proceeds to step 206 to determine if the single word transfer is a read transfer. If the operation is a read transfer, the controller proceeds to step 210 to set the read address 1 as the effective address and the read address 0 as a don't care. Returning to step 206, if the single word operation is a write operation, the controller proceeds to step 214 to compute the write address 1 as the effective address and the write address 0 as a don't care. Exiting steps 210 or 214, the controller returns to step 200.
  • step 208 determines whether the operation is a read or a write. If the operation is a read, the read address 0 is set equal to the effective address and the read address 1 is equal to the effective address plus 1 in step 212. The controller then proceeds to step 220 to determine if the byte count is 0. If not, in step 218 the effective address is incremented. Then the controller proceeds back to step 208 to continue this loop until the byte count is 0. When the byte count becomes 0, the controller exits step 220 and returns to step 200.
  • step 208 if the string operation is a write operation, the control­ler proceeds to step 216 to compute the read address 0 as the effective address and the write address 1 as the effective address plus 1. The controller then proceeds to step 220 to begin the loop including step 218 back to step 208 until the byte count in step 220 is 0 as previously discussed.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
EP19890850378 1988-11-17 1989-10-31 Interface pour formats de données multiples Withdrawn EP0369964A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27328688A 1988-11-17 1988-11-17
US273286 1988-11-17

Publications (2)

Publication Number Publication Date
EP0369964A2 true EP0369964A2 (fr) 1990-05-23
EP0369964A3 EP0369964A3 (fr) 1991-09-18

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Family Applications (1)

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EP19890850378 Withdrawn EP0369964A3 (fr) 1988-11-17 1989-10-31 Interface pour formats de données multiples

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EP (1) EP0369964A3 (fr)
JP (1) JPH0652516B2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE36052E (en) * 1991-11-05 1999-01-19 Mitsubishi Benki Kabushiki Kaisha Data processor with bus-sizing function

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4245307A (en) * 1979-09-14 1981-01-13 Formation, Inc. Controller for data processing system
US4370712A (en) * 1980-10-31 1983-01-25 Honeywell Information Systems Inc. Memory controller with address independent burst mode capability
US4683534A (en) * 1985-06-17 1987-07-28 Motorola, Inc. Method and apparatus for interfacing buses of different sizes
US4827409A (en) * 1986-07-24 1989-05-02 Digital Equipment Corporation High speed interconnect unit for digital data processing system
JPS63118965A (ja) * 1986-11-07 1988-05-23 Fujitsu Ltd Ｄｍａワ−ド転送方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE36052E (en) * 1991-11-05 1999-01-19 Mitsubishi Benki Kabushiki Kaisha Data processor with bus-sizing function

Also Published As

Publication number Publication date
JPH02187849A (ja) 1990-07-24
EP0369964A3 (fr) 1991-09-18
JPH0652516B2 (ja) 1994-07-06

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