Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
  • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/427—Power or ground buses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/541—Dispositions of bond wires
  • H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/931—Shapes of bond pads
  • H10W72/932—Plan-view shape, i.e. in top view

Definitions

• WAFER SCALE INTEGRATED CIRCUITS This invention relates to wafer scale integrated (WSI ) circuits comprising an array of integrated circuit modules on the wafer.
• the modules correspond more or less to the "chips" which would result were the wafer to be diced and each module may be a memory module or a processing module of some kind.
• the modules are interconnected by local connections and global lines.
• the local connections are module to module connections between neighbouring modules whereas the global lines extend to all modules and comprise both power supply lines and one or more lines for carrying global clock or command signals.
• the present invention is concerned with certain problems arising in connection with global lines but the nature of the global command signals is of no importance to the invention. Nevertheless background information as to kind of signals which may be involved will be found in GB-A-2 177 825.
• the present invention may be applied to WSI circuits of the kind described in GB-A-1 377 859 and GB-A-2 177 825 in which a chain, chains or a branching chain or chains or modules may be set up by software commands, by selectively enabling the local connections referred to above.
• the invention is not however restricted to such circuits.
• the modules are preferably, but not necessarily, arranged in rows and columns so that each module (apart that is from modules at the edge of the array) has four immediate neighbours, the local connections being provided between each pair of immediate neighbours.
• each mask defines structure over the whole wafer and can therefore be configured to create not merely the fine detail required in the creation of each module but also relatively coarse structures on the scale of the wafer, such as bonding pads round the edge of the wafer and networks of global lines.
• stepper technology each mask or reticle defines the structure of a single module or of a small cluster (e.g.
• the reticle being stepped about the wafer to expose the totality of modules.
• GB-A-2 177 825 the modules are arranged in rows and columns (the choice of which is which is arbitrary) and all global lines extend in the column direction.
• a specific problem which has to be addressed is that a faulty column conductor may erect a barrier partitioning the wafer into usable and unusable portions. Even using the chain growing technique referred to above it may not be possible to get past this barrier into a substantial portion of the wafer containing many good modules. For this reason it has already been proposed (GB-A-2 178 204) to use Christmas tree-like global power lines with a central spine in the row direction, from which column conductors branch on both sides.
• the object of the present invention is to provide a solution to these problems and the invention resides in the following features which can be used singly or in various combinations.
• Each module or each module cluster extends a plurality of signal lines to corresponding bond pads, whereby bondwire connections may be made anywhere desired, in particular at any desired location at the edge of the wafer.
• the signal lines treated thus can include at least an input line and an output line for data.
• Each module or each module cluster has power supply bond pads and power is supplied to the modules by bondwires stitch bonded to these pads.
• At least some global lines extend into the wafer from two opposite sides thereof, without meeting, so that a fault in a line extending in from one side will not affect the counterpart line extending in from the other side.
• the stitch bonding can be interrupted.
• the other global lines for signals are formed in a metal layer which is interrupted by an equatorial band containing no metal. This may be achieved in various ways:
• (c) define the pattern of the metal layer using one stepper reticle for modules flanking the equatorial band and another stepper reticle for the other modules.
• Fig. 1 is a diagram of a pair of chips showing some of the connections thereof
• Fig. 2 is a similar diagram of the chips showing other connections
• Fig. 3 is a simplified block diagram of one chip
• Fig. 4 shows a wafer on a printed circuit board and the bondwire connections
• Fig. 5 illustrates a detail V of Fig. 4,
• Fig.6 illustrates a modified form of chip.
• Each module or chip 10 shown in Fig.1 is composed largely of a 1 Mbit DRAM 12 of conventional design.
• the DRAM is accessed via logic 14.
• the chip may be constructed in accordance with GB-A 2177825 to which reference should be made for full details.
• the present application uses the same symbols as GB-A 2177825 to denote signals.
• the logic 14 can receive data on commonly connected inputs XINN, XINE, XINS and XINW (all connected to XIN), pass data on to a neighbouring chip-via a selected one of four switched outputs XOUTN, XOUTE, XOUTS and XOUTW, write received data into the DRAM 12, receive data on a return path from a neighbouring chip via a selected one of four switched inputs RINN, RINE, RINS, RINW, pass such data on to commonly connected outputs ROUTN, ROUTE, ROUTS and ROUTW (all connected to ROUT) and read data from the DRAM 12 to these outputs.
• the chips are formed on a wafer by stepper technology and, because of the aspect ratio of one chip, it is convenient to step a cluster of two chips, shown in Fig.1.
• the chips are framed by a "flash" 16 in which there is overlap between successive stepper reticle placements. All of the input and output connections are so disposed along the N, E, S, W edges of the chip that N and S connections will connect up, as will E and W connections.
• XINN of the lower chip connects to XOUTS of the lower chip while RINS of the upper chip connects to ROUTN of the lower chip. Connections are thereby established over the whole wafer which will enable a chain of chips to be grown, as described in GB-A 2177825.
• the connections thus far described may be made in metal 1 and polysilicon and they are unaffected by the treatment of metal 2, described below.
• every chip or at least one chip of every cluster, has a bondpad XMIT connected to the input line XIN and a bondpad RECV connected to the output line ROUT. Accordingly, any chip can be used as a bondsite chip from which a chain of chips may be grown. In practice four chips are used as bondsite chips, as will be explained with reference to Fig.4.
• All chips have to receive supply voltages V SS and V CC such as Ov and 5v and to this end every chip has a corresponding pad so labelled. All chips also have to receive the global commands WCK (wafer clock) and CMND (command) and every chip has a corresponding bondpad.
• the bondpads V SS and V CC are not connected in the integrated circuit structure but WCK and CMND are connected by tracks 18 in metal 2, shown in Fig.2, which omits the data input and output lines of Fig.1 for simplicity.
• the power supply bondpads V CC and V SS are connected by bondwires 20 stitch-bonded to the columns of pads.
• Fig.4 The complete layout is indicated in Fig.4 which, for simplicity shows far fewer chips in a wafer than would actually be present and only representative connections are shown.
• the array of chips 10 is formed on a wafer 22 which is mounted on a printed circuit board (PCB) 24. Along the top of this board there run tracks for V SS , V CC , CMND and WCK. Along the bottom these tracks are dupl icated.
• V SS printed circuit board
• V CC Integrated Circuit
• CMND complementary metal-oxide-semiconductor
• WCK printed circuit board
• al l V CC bondpads in the top half of the wafer are connected by one bondwire 20 to the V CC track at the top of the board 24 and al l V SS bondpads are connected by the other bondwire 20 to the V SS track at the top of the board.
• the V «p and Vgg pads of the chips in the lower half of the waf er are s imilarly connected to the V «p and Vgg tracks at the bottom of the board.
• the WCK and CMND pads are connected by the metal 2 tracks 18 within the integra ted circui t s corture itself.
• the WCK and CMND bondpads of the top chip of each column are connected to the top WCK and CMND PCB tracks by bondwires 32 and the WCK and CMND bondpads of the bottom chip of each column are connected to the bottom WCK and CMND PCB tracks by bondwires 34.
• the equatorial band 26 may be formed by us ing a sl ightly modif ied reticle for the row 28 of chips above this band when masking metal 2, the bottom f lash, shown shaded in F ig.2, be ing omitted. This is il l us trated in F ig.5, showing the ends of the ha lf tracks 18, separated by a gap in the band 26 formed because the f lash 30 is not present, even though the top f lash 36 of the next chip bel ow remains.
• F ig. 6 shows an al ternative arrangement us ing a clus ter of two s ide-by-s ide chips 40 bounded lateral ly by al ternate V SS and V CC tracks. Al though these are continuous, wires may be s titch-bonded along them to ensure adequate current carrying capacity to the chips.
• CMND and WCK have tracks 42 with bondpads top and bottom, so that connections may be made at the top and bottom chips of each col umn, as in F ig.4.
• XMIT and RECV are dupl icated at each s ide as XMITW and XMITE and RECVW and RECVE so that any chip at the lef t or right hand side of the array may be used as a bonds ite chip.
• an equatorial band interrupting the tracks 42 is provided, as in F ig.4.
• the equatorial band 26 in Fig. 4 may alternatively be formed by initially laying down continuous tracks 18, i.e. using a normal reticle for all modules for metal 2, and thereafter etching gaps in the metal 2 tracks using a more crudely aligned (e.g. 2-3u) whole wafer mask.

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• Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
• Design And Manufacture Of Integrated Circuits (AREA)

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• 1989
  • 1989-05-31 KR KR1019900700196A patent/KR900702569A/ko not_active Withdrawn
  • 1989-05-31 EP EP89906418A patent/EP0378613A1/de not_active Withdrawn
  • 1989-05-31 WO PCT/GB1989/000594 patent/WO1989012320A1/en not_active Ceased

Non-Patent Citations (1)

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