EP0406366A1 - Diviseur programmable a haute vitesse. - Google Patents

Diviseur programmable a haute vitesse.

Info

Publication number
EP0406366A1
EP0406366A1 EP90900469A EP90900469A EP0406366A1 EP 0406366 A1 EP0406366 A1 EP 0406366A1 EP 90900469 A EP90900469 A EP 90900469A EP 90900469 A EP90900469 A EP 90900469A EP 0406366 A1 EP0406366 A1 EP 0406366A1
Authority
EP
European Patent Office
Prior art keywords
output
input
coupled
counter
divider
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90900469A
Other languages
German (de)
English (en)
Other versions
EP0406366B1 (fr
Inventor
Albert E Cosand
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of EP0406366A1 publication Critical patent/EP0406366A1/fr
Application granted granted Critical
Publication of EP0406366B1 publication Critical patent/EP0406366B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/665—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by presetting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits
    • H03K21/10—Output circuits comprising logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer

Definitions

  • the fixed-modulus prescaler can run at a higher speed, since it need only contain latches with no logic gates between the latches.
  • the prescaler normally supplies one clock pulse to the programmable divider for every N clock pulses presented to the prescaler input.
  • FIG. 7 is a functional block diagram of an alternative embodiment of the divider set forth in FIG. 1;
  • Counter 120 has an output designated EOC (end-of-count) coupled via path 112 to a START input of delay counter 130.
  • Delay counter 130 has a divide-enable
  • Delay counter 130 has a PRESET control output 113 coupled via path 113 to a PRESET input of count-down counter 120 and an RC-EN control output coupled via path 114 to an ENABLE input of count-down counter 120.
  • Delay counter 130 additionally includes a first output OUT coupled via path 117 to input A of multiplexer 140 and a second output HD-OUT coupled via path 118 and 118a to input B of multiplexer 140.
  • Output HD-OUT of delay counter 130 is additionally coupled via path 118b to a CLK input of adder-accumulator 150.
  • a divide-enable signal is additionally coupled via path 116a to a DIV-EN-L input of adder-accumulator 150. The least significant bit,
  • Adder-accumulator 150 has a CARRY output coupled via path 151, to a LONG-COUNT input of delay counter 130.
  • Prescaler 110 features circuitry which is symmetrical and fully differential, and it provides a differential output to drive the. half integer divider comprised of elements 120, 130, 140, 150 and 160.
  • the output 111 of prescaler 110 has the property that the output signal is the voltage difference between two symmetrical, active nodes, such that the complement of the signal is obtained with zero delay by reversing the connections to the output nodes, and the positive-going and negative-going output transitions are equally spaced in time.
  • both the normal differential output signal and the complement differential output signal of the prescaler can be • used as clock phases for the remainder of the circuitry of FIG. 1.
  • the complement clock phase allows data transitions to be clocked at the time of the negative-going edge of the normal clock phase.
  • Blocks 120, 130, 140, 150 and 160 form a true half-integer programmable divider capable of dividing by any integer or half-integer over a range determined by the width of data bus 170 and the delay incorporated into the delay counter 130 which will be discussed in more detail below.
  • the divider of FIG. 1 When the divider of FIG. 1 is dividing by a half-integer, it provides equally spaced output pulses which are alternately clocked by a rising or falling edge of the prescaler output signal.
  • the delay counter 130 is started by the EOC pulse on path 112 from counter 120 and, in the illustrative embodiment, on the fourth clock edge following the EOC pulse, delay counter 130 will enable counter 120 at its RC-EN output via path 114 to the ENABLE input of counter 120.
  • counter 130 disables presettable counter 120, generates a preset pulse at output PRESET which is coupled via path 113 to the PRESET input of count-down counter 120 and generates the divider output pulse in undelayed and half-clock delayed forms, respectively, at output OUT and HD-OUT.
  • delay counter 130 provides a one-half clock delayed version of the output pulse at output HD-OUT (clocked by the negative-going edge of the prescaler output, rather than the positive-going edge) , and, when the
  • Adder-accumulator 150 adds the least significant bit PO to a running one-bit sum on each cycle of operation of the divider.
  • the sum bit at output SUM controls multiplexer 140 over path 152 to select the normal or the half-bit-delayed outputs presented over paths 117 and 118a, respectively, to input A and B of multiplexer 140.
  • the CARRY output of adder-accumulator 150 is used to enable the long (5 clock period) count of delay counter 130 by coupling an appropriate control signal via path 151 to the LONG-COUNT of delay counter 130.
  • the programmable divider has an overall modulus with a programmable increment less than the prescaler modulus and has a maximum operating frequency equal' to a maximum operating frequency of the prescaler.
  • OR gate 443 is coupled to the D input of latch 401a, while the Q output of latch 401a is coupled to the D input of latch 401b.
  • the Q output of latch 401b is coupled via path 450-1 to a second input of AND gate 442 and to the clock inputs of latches 402a and 402b.
  • each stage of counter 120 is comprised of a pair of D-type latches with the clock inputs of each pair of a given stage coupled to the Q output of the second latch of a preceding stage and to the D input to the first latch of the pair of the preceding stage. Also, it will be understood that the Q output of the first latch of the pair of each stage is coupled to the D input of the second latch of the pair.
  • the delay counter 130 of FIG. 1 is set forth in functional block diagram detail in FIG. 5A, and its operation is most easily explained by simultaneous reference to the timing diagram of FIG. 5B.
  • START input at path 112 (which corresponds to the EOC output of count-down counter 120) is coupled to the D input of latch 501.
  • the CLK input at path 111b is coupled to the clock inputs of D-type latches 501, 502, 503, 504, 505, 506, 507 and 508.
  • NOR gate 513 The output of NOR gate 513 is coupled to a D input of latch 507, whose Q output is coupled via path
  • FIG. 6 A functional block diagram of an adder-accumulator suitable for use with the invention is set forth in FIG. 6.
  • the divide-enable input at path 116a is coupled to the input of a signal level shifter 610 having two outputs LI and L3 which for logic state purposes, are identical.
  • Output LI of shifter 610 is coupled to a reset input of D latch 601 and to a reset input of D latch 604, while output L3 is coupled to a presetting input PS of latch 602.
  • the Q output of latch 603 is coupled to the D input of latch 604 and to second inputs of both AND gates 621 and exclusive OR gate 622.
  • the adder-accumulator has a CARRY output which goes high one divider cycle earlier than the SUM output.
  • divisor data bit PO equals 1
  • SUM logic 1
  • CARRY logic zero on one cycle and with their respective logic states reversed on the next cycle. If the SUM output is then delayed one cycle, the CARRY and the delayed SUM outputs will cycle together alternating between both at logic one and both at logic zero. This is required for the programmable divider to correctly divide by a half-integer.
  • the observed subharmonic line is typically greater than 30 dB below the level that would be obtained if a simple alternation between divide-by-N and divide-by-N+1 were used to approximate the divide-by-(N+1/2) operation.
  • the exact degree of suppression of the subharmonic depends on how accurately the clock-to-data delay is matched between the normal and " the half-bit-delayed output. With careful circuit layout the clock-to-data delay can be matched well enough to avoid deleterious effects on the operation of a practical phase-locked-loop circuit.
  • a half-integer divider arranged in accordance with the invention could readily be extended to include a wider adder-accumulator multiplexer to select outputs with finer increments of delay, if all clock transitions from the prescaler were available to generate the delays.
  • a quarter-integer divider could be used to give an overall half-integer programming capability at the prescaler input. In this case, the suppression of subharmonics in the divider output would be limited by the degree to which the positive and negative zero-crossings of the input clock were evenly spaced.
  • the true fractional integer divider could even be clocked directly from an input signal with no prescaler, with the appropriate clock phases developed by hybrid junctions and summers. This would be potentially useful for minimizing the overall multiplication of the reference frequency in a phase-locked-loop synthesizer in which multiplied reference noise is a limitation. Such an approach would also allow for a faster settling time than could otherwise be achieved for a given output frequency spacing.
  • Presettable count-down counter 720 has a multiple line parallel input data bus 770 presenting a variable program-determined representation of a numerical value to which the counter is to be preset. Bus 770 is directed to DATA inputs of counter 720.
  • Counter 720 has an output designated EOC (end-of-count) coupled via path 712 to a START input of delay counter 730.
  • Delay counter 730 has a divide-enable
  • Delay counter 730 additionally includes a first output OUT coupled via path 717 to input A of multiplexer 740 and a second output HD-OUT coupled via path 718 to input B of multiplexer 740.
  • Output 719 of multiplexer 740 is coupled via path 719a to a CLK input of adder-accumulator 750.
  • a divide-enable signal is additionally coupled via path 716a to a DIV-EN-L input of adder-accumulator 750.
  • the least significant bit, PO, of information on bus 770 is coupled via path 771 to input IN of adder-accumulator 750.
  • Adder-accumulator 750 has a CARRY output coupled via path 751 to a LONG-COUNT input of delay counter 730. Additionally, adder-accumulator 750 has a SUM output coupled via path 752 to the SELECT input of multiplexer 740.

Landscapes

  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Saccharide Compounds (AREA)
  • Stored Programmes (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

Un diviseur de fréquence ou compteur programmable comprend la combinaison d'un pré-étalonneur de module fixe (110) et d'un diviseur programmable (120, 130, 140, 150, 160), le pré-étalonneur fournissant plus d'une phase d'horloge unique au diviseur programmable et le diviseur programmable utilisant les phases d'horloge multiples pour permettre un fonctionnement dans un mode nombre fractionnaire-nombre entier. La combinaison globale du pré-étalonneur et du diviseur programmable fonctionne comme un diviseur programmable pour lequel l'incrément minimal dans le module du diviseur global est inférieur au module du pré-étalonneur, mais la fréquence d'horloge maximale utilisable est la fréquence d'horloge maximale du pré-étalonneur.
EP90900469A 1988-12-19 1989-11-14 Diviseur programmable a haute vitesse Expired - Lifetime EP0406366B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US07/286,435 US4975931A (en) 1988-12-19 1988-12-19 High speed programmable divider
US286435 1988-12-19
PCT/US1989/005003 WO1990007232A1 (fr) 1988-12-19 1989-11-14 Diviseur programmable a haute vitesse

Publications (2)

Publication Number Publication Date
EP0406366A1 true EP0406366A1 (fr) 1991-01-09
EP0406366B1 EP0406366B1 (fr) 1994-06-01

Family

ID=23098597

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90900469A Expired - Lifetime EP0406366B1 (fr) 1988-12-19 1989-11-14 Diviseur programmable a haute vitesse

Country Status (11)

Country Link
US (1) US4975931A (fr)
EP (1) EP0406366B1 (fr)
JP (1) JP2577134B2 (fr)
KR (1) KR940007543B1 (fr)
AU (1) AU618434B2 (fr)
CA (1) CA2003466C (fr)
DE (1) DE68915756T2 (fr)
ES (1) ES2020823A6 (fr)
IL (1) IL92769A (fr)
NO (1) NO303308B1 (fr)
WO (1) WO1990007232A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639435B2 (en) 2000-01-20 2003-10-28 Infineon Technologies Ag Adjustable frequency divider

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5195111A (en) * 1990-09-07 1993-03-16 Nihon Musen Kabushiki Kaisha Programmable frequency dividing apparatus
JP2842004B2 (ja) * 1992-02-03 1998-12-24 日本電気株式会社 回路のテスト方式
US5428769A (en) * 1992-03-31 1995-06-27 The Dow Chemical Company Process control interface system having triply redundant remote field units
EP0602422A1 (fr) * 1992-12-15 1994-06-22 International Business Machines Corporation Changement dynamique de fréquence avec des générateurs d'horloge à division par un
EP0683566A1 (fr) * 1994-05-17 1995-11-22 Siemens Aktiengesellschaft Circuit diviseur d'un signal de synchronisation
DE19519321C2 (de) * 1995-05-26 1997-10-16 Gerhard Kultscher Ind Elektron Frequenzteiler mit dualer, aktaler, dezimaler oder hexadezimaler Divisoreingabe
DE69631002T2 (de) * 1995-09-28 2004-09-16 Sanyo Electric Co., Ltd., Moriguchi Einstellbarer Frequenzteiler
EP1020994A1 (fr) * 1995-11-22 2000-07-19 Sanyo Electric Co., Ltd. PLL avec diviseur de fréquence variable de rapport (N+1/2)
FI100285B (fi) * 1995-12-11 1997-10-31 Nokia Mobile Phones Ltd Taajuudenmuodostuspiiri
DE69624952T2 (de) * 1996-01-09 2003-08-28 Sanyo Electric Co., Ltd. Einstellbarer Frequenzteiler
US5748949A (en) * 1996-07-02 1998-05-05 Motorola Inc. Counter having programmable periods and method therefor
US6065140A (en) * 1997-04-30 2000-05-16 Motorola, Inc. Optimized computation of first and second divider values for a phase locked loop system
US5970110A (en) * 1998-01-09 1999-10-19 Neomagic Corp. Precise, low-jitter fractional divider using counter of rotating clock phases
US6114915A (en) * 1998-11-05 2000-09-05 Altera Corporation Programmable wide-range frequency synthesizer
US7003475B1 (en) 1999-05-07 2006-02-21 Medcohealth Solutions, Inc. Computer implemented resource allocation model and process to dynamically and optimally schedule an arbitrary number of resources subject to an arbitrary number of constraints in the managed care, health care and/or pharmacy industry
DE19930179C2 (de) * 1999-06-30 2001-07-05 Infineon Technologies Ag Hochgeschwindigkeitszähler
KR100510844B1 (ko) * 1999-08-21 2005-08-31 재단법인 포항산업과학연구원 중량 팔레트의 지지부재 최적위치 결정방법
US6789041B1 (en) * 2001-05-08 2004-09-07 Miranova Systems, Inc. Bi-directional signal converter
US6690525B2 (en) * 2001-05-25 2004-02-10 Infineon Technologies Ag High-speed programmable synchronous counter for use in a phase locked loop
US6975682B2 (en) * 2001-06-12 2005-12-13 Raytheon Company Multi-bit delta-sigma analog-to-digital converter with error shaping
US6611573B2 (en) * 2001-08-14 2003-08-26 Sun Microsystems, Inc. Non-integer division of frequency
RU2222101C2 (ru) * 2002-01-08 2004-01-20 Федеральное государственное унитарное предприятие Омский научно-исследовательский институт приборостроения Делитель частоты с дробным переменным коэффициентом деления
US6725245B2 (en) 2002-05-03 2004-04-20 P.C. Peripherals, Inc High speed programmable counter architecture
US6879654B2 (en) * 2003-04-25 2005-04-12 International Business Machines Corporation Non-integer frequency divider circuit
US7336756B2 (en) * 2004-10-25 2008-02-26 Miranova Systems, Inc. Reprogrammable bi-directional signal converter
US7231012B2 (en) * 2004-11-30 2007-06-12 Stmicroelectronics Pvt. Ltd. Programmable frequency divider
US8149022B2 (en) * 2007-02-09 2012-04-03 Mediatek Inc. Digital delay line based frequency synthesizer
US8131242B2 (en) * 2007-07-02 2012-03-06 Sony Corporation System and method for implementing a swap function for an IQ generator
US7724097B2 (en) * 2008-08-28 2010-05-25 Resonance Semiconductor Corporation Direct digital synthesizer for reference frequency generation
US8242850B2 (en) * 2008-08-28 2012-08-14 Resonance Semiconductor Corporation Direct digital synthesizer for reference frequency generation
EP2806562A1 (fr) * 2013-05-22 2014-11-26 Asahi Kasei Microdevices Corporation Module de diviseur de fréquence programmable avec cycle de travail proche de cinquante pour cent
US9106216B1 (en) * 2014-07-31 2015-08-11 Microsoft Technology Licensing Llc Programmable pulse generation
US10812090B2 (en) * 2018-11-26 2020-10-20 Stmicroelectronics S.R.L. Ultra-low power, real time clock generator and jitter compensation method
CN113381752B (zh) * 2021-06-24 2023-02-28 成都纳能微电子有限公司 半分频电路及方法
US11874693B2 (en) 2022-05-24 2024-01-16 Analog Devices International Unlimited Company Reconfigurable clock divider

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3873815A (en) * 1973-03-19 1975-03-25 Farinon Electric Frequency division by an odd integer factor
US3959737A (en) * 1974-11-18 1976-05-25 Engelmann Microwave Co. Frequency synthesizer having fractional frequency divider in phase-locked loop
US4017719A (en) * 1975-12-18 1977-04-12 Rca Corporation Binary rate multiplier with means for spacing output signals
US4193037A (en) * 1978-03-20 1980-03-11 Motorola, Inc. Frequency divider circuit with selectable integer/non-integer division
DE2826321C3 (de) * 1978-06-15 1981-02-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Digitaler Frequenzteiler
JPS5637734A (en) * 1979-09-04 1981-04-11 Matsushita Electric Ind Co Ltd Frequency dividing device
JPS5718129A (en) * 1980-07-07 1982-01-29 Nec Corp Pulse swallow frequency divider
JPS5718128A (en) * 1980-07-08 1982-01-29 Yamatake Honeywell Co Ltd Frequency dividing circuit
JPS5733471A (en) * 1980-07-31 1982-02-23 Fujitsu Ltd Memory access control system for multiprocessor
JPS57133728A (en) * 1981-02-12 1982-08-18 Matsushita Electric Ind Co Ltd Frequency divider
JPS59135684A (ja) * 1983-01-24 1984-08-03 Fujitsu Ltd バツフアメモリ間のデ−タバイパス方式
JPS59190724A (ja) * 1983-04-14 1984-10-29 Fuji Electric Co Ltd 周波数可変のパルス発生器
JPS603228A (ja) * 1983-06-20 1985-01-09 Nec Home Electronics Ltd 分周回路
US4555793A (en) * 1983-11-28 1985-11-26 Allied Corporation Averaging non-integer frequency division apparatus
US4773031A (en) * 1984-12-24 1988-09-20 Tektronix, Inc. Method and circuit for digital frequency multiplication
US4623846A (en) 1985-02-14 1986-11-18 Motorola, Inc. Constant duty cycle, frequency programmable clock generator
US4658406A (en) * 1985-08-12 1987-04-14 Andreas Pappas Digital frequency divider or synthesizer and applications thereof
JPS62120553A (ja) * 1985-11-20 1987-06-01 Nec Corp 命令キヤツシユメモリ方式
US4837721A (en) * 1986-06-30 1989-06-06 Itt Defense Communications, A Division Of Itt Corporation Digital divider with integer and fractional division capability
US4856032A (en) * 1987-01-12 1989-08-08 Motorola, Inc. High speed programmable frequency divider and PLL
US4809221A (en) * 1987-01-28 1989-02-28 Megatest Corporation Timing signal generator
DE3705629A1 (de) * 1987-02-21 1988-09-01 Thomson Brandt Gmbh Programmierbarer frequenzteiler sowie verfahren zur erzeugung eines niederfrequenten signals aus einem hochfrequenten signal
US4807266A (en) * 1987-09-28 1989-02-21 Compaq Computer Corporation Circuit and method for performing equal duty cycle odd value clock division and clock synchronization

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9007232A1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6639435B2 (en) 2000-01-20 2003-10-28 Infineon Technologies Ag Adjustable frequency divider

Also Published As

Publication number Publication date
NO903620D0 (no) 1990-08-16
WO1990007232A1 (fr) 1990-06-28
CA2003466A1 (fr) 1990-06-19
NO903620L (no) 1990-08-16
JPH03502870A (ja) 1991-06-27
NO303308B1 (no) 1998-06-22
DE68915756T2 (de) 1994-09-22
AU4653889A (en) 1990-07-10
AU618434B2 (en) 1991-12-19
DE68915756D1 (de) 1994-07-07
JP2577134B2 (ja) 1997-01-29
KR910700567A (ko) 1991-03-15
IL92769A0 (en) 1990-09-17
EP0406366B1 (fr) 1994-06-01
IL92769A (en) 1993-02-21
CA2003466C (fr) 1995-01-31
KR940007543B1 (ko) 1994-08-19
US4975931A (en) 1990-12-04
ES2020823A6 (es) 1991-10-01

Similar Documents

Publication Publication Date Title
AU618434B2 (en) High speed programmable divider
US5537068A (en) Differential delay line clock generator
CN110830041B (zh) 占空比50%的连续整数分频器及包括其的锁相环电路
US6914460B1 (en) Counter-based clock doubler circuits and methods
US5828250A (en) Differential delay line clock generator with feedback phase control
US5065415A (en) Programmable frequency divider
US6542013B1 (en) Fractional divisors for multiple-phase PLL systems
CN105162457B (zh) 高速分频器及使用高速分频器的锁相环路
US6661261B2 (en) Programmable divider with built-in programmable delay chain for high-speed/low power application
CA1137568A (fr) Circuit digital de comparaison de phase
CN1044556A (zh) 高速预分频器
US6906571B1 (en) Counter-based phased clock generator circuits and methods
JPH05500439A (ja) 高速プリスケーラ
JPS62230118A (ja) デジタル位相同期ル−プ回路
US7034584B2 (en) Apparatus for frequency dividing a master clock signal by a non-integer
US4575867A (en) High speed programmable prescaler
US6316982B1 (en) Digital clock with controllable phase skew
US5384816A (en) Frequency divider circuit
US6108393A (en) Enhanced prescaler phase interface
JP2006522527A (ja) 直交クロック分周器
US8218712B1 (en) Method and apparatus for dividing clock frequencies
CN120320767B (zh) 一种输出占空比50%的连续整数分频器
CN112653460B (zh) 分频器、分频方法及装置
EP0469738A2 (fr) Diviseur de fréquence à faible bruit
JPS6326565B2 (fr)

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): CH DE FR GB IT LI NL SE

17P Request for examination filed

Effective date: 19901204

17Q First examination report despatched

Effective date: 19930128

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): CH DE FR GB IT LI NL SE

REF Corresponds to:

Ref document number: 68915756

Country of ref document: DE

Date of ref document: 19940707

ET Fr: translation filed
ITF It: translation for a ep patent filed
EAL Se: european patent in force in sweden

Ref document number: 90900469.9

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: CH

Payment date: 19961030

Year of fee payment: 8

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19971130

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 19971130

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

NLS Nl: assignments of ep-patents

Owner name: RAYTHEON COMPANY;HE HOLDINGS, INC.

REG Reference to a national code

Ref country code: FR

Ref legal event code: TP

Ref country code: FR

Ref legal event code: CD

Ref country code: FR

Ref legal event code: CA

REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20031125

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20031128

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20031130

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20040112

Year of fee payment: 15

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: SE

Payment date: 20040401

Year of fee payment: 15

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20041114

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20041115

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050601

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050601

EUG Se: european patent has lapsed
GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20041114

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20050729

NLV4 Nl: lapsed or anulled due to non-payment of the annual fee

Effective date: 20050601

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20051114

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

Free format text: REGISTERED BETWEEN 20090910 AND 20090916

REG Reference to a national code

Ref country code: GB

Ref legal event code: 732E

Free format text: REGISTERED BETWEEN 20090917 AND 20090923