EP0441851A1 - Recepteur de radiodiffusion par satellite - Google Patents

Recepteur de radiodiffusion par satellite

Info

Publication number
EP0441851A1
EP0441851A1 EP89912437A EP89912437A EP0441851A1 EP 0441851 A1 EP0441851 A1 EP 0441851A1 EP 89912437 A EP89912437 A EP 89912437A EP 89912437 A EP89912437 A EP 89912437A EP 0441851 A1 EP0441851 A1 EP 0441851A1
Authority
EP
European Patent Office
Prior art keywords
circuit
radio receiver
satellite radio
receiver according
tap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP89912437A
Other languages
German (de)
English (en)
Inventor
Otto Klank
Klaus Eilts-Grimm
Jürgen LAABS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=6366294&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=EP0441851(A1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Publication of EP0441851A1 publication Critical patent/EP0441851A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/90—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/18—Automatic scanning over a band of frequencies
    • H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
    • H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J1/00—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general
    • H03J1/0008—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor
    • H03J1/0041—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers
    • H03J1/005—Details of adjusting, driving, indicating, or mechanical control arrangements for resonant circuits in general using a central processing unit, e.g. a microprocessor for frequency synthesis with counters or frequency dividers in a loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
    • H03J7/02—Automatic frequency control
    • H03J7/04—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant
    • H03J7/06—Automatic frequency control where the frequency control is accomplished by varying the electrical characteristics of a non-mechanically adjustable element or where the nature of the frequency controlling element is not significant using counters or frequency dividers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/5631—Resource management and allocation
    • H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions

Definitions

  • the invention relates to a satellite radio receiver according to the preamble of claim 1.
  • Signals that satellite radio receivers receive from a satellite reception system can be subject to a frequency drift.
  • the cause of the frequency drift is an unstable oscillator of the satellite reception system or another intermediate converter. Because of the high transmission frequency, even small relative frequency deviations have a strong absolute deviation on the intermediate frequency in the satellite radio receiver. This phenomenon can mean that the automatic frequency control of the carrier oscillator for the demodulation circuit can no longer compensate for the frequency drift.
  • the object of the invention is to improve a satellite radio receiver in such a way that rapid and reliable tuning is possible even in the event of frequency deviations of the received signal which go beyond the control range of the automatic frequency control for the carrier oscillator.
  • This object is achieved in a satellite radio receiver according to the preamble of claim 1 by the features specified in the label.
  • the invention first uses a missing synchronizing signal as a criterion for the tuning.
  • the PLL local oscillator is tuned in large frequency steps (search).
  • search search
  • the superimposition frequency which is optimal for the compensation of the frequency deviation is achieved very quickly. This will approximate the capture range, for example of the 4PSK demodulator, reached.
  • the frequency steps for the final tuning of the PLL superposition oscillator are reduced.
  • the PLL local oscillator is then further tuned in small frequency steps until the frequency deviation of the demodulator -VCOS lies within the limits of a window which is in the vicinity of the center frequency of the tuning range and is, for example, smaller than the limits two small increments.
  • Fig. 1 is a block diagram of a satellite radio broadcasting receiver with a satellite receiving system
  • FIG. 2 shows a circuit diagram of a comparator circuit as part of an AFC circuit from FIG. 1
  • Fig. 3 is a circuit diagram for the extraction of a
  • the satellite receiving system consists of a satellite antenna 41 and two frequency converters 42 and 43.
  • the satellite radio receiver comprises a receiving part 33 with a mixer 45, a PL superposition oscillator 44 and a control circuit 34, an IF amplifier 46, a demodulator circuit 47 and a carrier oscillator 36, an AFC circuit 1, a synchronous signal evaluation circuit 40, like a decoding circuit 49. Sound signals can be tapped at the output of the decoding circuit 49.
  • the PLL superposition oscillator 44 can be set to a predetermined, agreed frequency, and an intermediate frequency with the nominal value of the IF then results at the output of the mixer 45.
  • the signal which is preferably in 4PSK modulation, can be demodulated in the demodulator circuit 47 downstream of the IF amplifier 46. The. Are used for carrier regeneration during de-odulation
  • Carrier oscillator 36 which is controlled so that it oscillates phase-synchronously to the modulated signal.
  • the oscillator 30 receives the input signal from the output of the demodulator circuit 47 via the loop filter 51.
  • the demodulator 47 can no longer trace the carrier oscillator 36.
  • This effect which is disadvantageous for signal recovery, is used to readjust the local oscillator 44 via the control circuit 34 in such a way that the intermediate frequency is regulated to its nominal value.
  • the control circuit 34 in particular a microprocessor, receives the command that
  • the PLL local oscillator 44 to adjust gradually.
  • the re-tuning direction is predetermined by the respective output of the circuits 40, 48.
  • the control circuit 34 also receives from the
  • Synchronous signal evaluation circuit 40 a signal, the state of which depends on the recognition or non-recognition of a synchronous signal. If there is no synchronous signal, ie if the demodulator 47 has not caught, the PLL local oscillator 44 is retuned in large steps, preferably 250 kHz. If, on the other hand, a synchronous signal is present, the PLL local oscillator 44 becomes small Steps of preferably 62.5 kHz matched. The chronological sequence of steps is so designed that it corresponds to the system settling time. The tuning process is continued in the manner of a search until the demodulator has caught. The absorption process in the capture area is continued in small steps until a window with the width of two small steps around the center frequency of the demodulator is reached.
  • the AFC circuit 1 contains a comparator circuit 48 which compares the AFC signal with an upper and a lower threshold value.
  • FIG. 2 shows the design of a comparator circuit 48
  • FIG. 2 shows, wherein a first comparator 20 is provided for the upper and a second comparator 21 for the lower threshold value.
  • the one inputs 16, 17 of the comparators 20, 21 are supplied with the AFC signal via resistors 12 and 13 and the other inputs 18, 19 are supplied with comparison voltages via resistors 14 and 15 and a voltage divider circuit 5 ... 9.
  • Outputs 31, 23 of the comparator circuit 48 are connected to the control circuit 34, the output 31 specifying one and the other output 23 specifying the other tuning direction.
  • Two end connections of the voltage divider circuit 5 ... 9 are connected to fixed reference voltages + U, ground and a tap is connected to an adjustable reference voltage U. Another tap is due to a positive feedback voltage U. ,, which is tapped at the outputs 22, 23 of the comparators 20, 21.
  • the adjustable reference voltage U. . is set to a value that the carrier oscillator 36 to a
  • the voltage divider circuit comprises a series circuit comprising resistors 5, 6, 7, 8 and 9, the resistor 5 having its free end at positive potential + U, while the resistor 9 having its free end is at zero potential (mass).
  • the input 18 of the first comparator 20 is connected via the resistor 14 to the tap between the resistors 5 and 6 and the input 19 of the second comparator 21 via the resistor 15 to the tap between the resistors 7 and 8.
  • the tapping between the resistors 6 and 7 is due to the adjustable reference voltage u e: ns - ( ./ while the tapping between the resistors 8 and 9 is due to the coupling voltage U.
  • the adjustable reference voltage U. is generated in a circuit arrangement which comprises a series circuit comprising a resistor 2, a variable resistor 3 with a tap 10 and a resistor 4, the resistor 2 having a free end at a positive potential + U, while the resistor 4 is at its free end at a negative potential -U.
  • the tap 10 is connected to the tap between the resistors 6 and 7.
  • a further connection of the tap 10 is to a switch 37 which is used for a comparison and via which the tap 10 can be connected to the control input of the carrier oscillator 36.
  • the output 22 of the first comparator 20 is connected via a series resistor 28 to the control input of an inverter 30 designed as an NPN transistor, the output of which forms the first output 31 of the comparator circuit 48.
  • the output of the second comparator 21 forms the second output 23 of the comparator circuit 48.
  • outputs 22 and 23 are via resistors 24 and 25 connected to the taps between the resistors 8 and 9.
  • the outputs 22 and 23 are connected to the positive potential + 5V via resistors 26 and 27, as is a resistor 29 connected to the output 31 of the transistor, which results in a TTL matching with regard to the signal level.
  • the control input of the carrier oscillator 36 which is temporarily free during the adjustment, is connected to the tap 10 of the changeable resistor 3 by closing the switch 37.
  • the voltage supplied to the control input of the carrier oscillator 36 is now set such that it can be adjusted to the carrier frequency of 70 MHz in the exemplary embodiment.
  • a change in temperature causes, for example, a displacement of the window relative to the center frequency of the demodulator 47.
  • A is used to compensate for the temperature influence
  • Temperature compensation circuit 50 Since the tuning voltage for the control input of the VCO 36 is subjected to the influence of the temperature compensation circuit 50, the tuning voltage is already at the output of a
  • the switching point of the first comparator 20 is above the reference voltage U by the voltage drop across the resistor 6 plus a hysteresis voltage. . and the switching point of the second comparator 21 around the voltage drop across the resistor 7 plus a slight hysteresis voltage below the reference voltage Usi. ⁇ st ..
  • a window is thus set for the limits of the frequency deviations. Outside the window, the PLL local oscillator 33 is retuned step by step in small increments, and the tuning directions are predefined differently. The system rests within the window, the control loop acts interrupted.
  • the tuning voltage of the carrier oscillator 36 is fed to the signal input 32 of the comparator circuit 48 and compared with the potential of the switching point of the first comparator 20 and the second comparator 21. If the tuning voltage is within the window, the output 23 is at the positive control limit, while the output 22 of the first comparator 20 is switched through to the negative control limit is. As a result, the transistor 30 is blocked and the output 31 is also at the positive modulation limit. The outputs 23 and 31 thus carry both signals logically H. The PLL local oscillator 44 is correctly tuned.
  • the output 31 is switched through to the negative control limit, while the output 23 maintains the position at the positive control limit.
  • the outputs 31 and 23 thus carry the signals logic L and logic H.
  • the frequency of the PLL superposition oscillator 44 is readjusted.
  • the output 23 is switched through to the negative output limit, while in this case the output 31 maintains the position at the positive control limit .
  • the outputs 31 and 23 carry the signals logic H and logic L.
  • the frequency control of the PLL local oscillator 44 acts in the opposite direction in this case.
  • the inputs connected to the outputs 23 and 31 are switched to inactive by the synchronization signal evaluation circuit 40, so that the control loop is interrupted.
  • the control circuit 34 starts a station search. If a signal is detected or a synchronous signal is generated, the control loop takes over the further re-tuning, the control circuit 34 evaluating the signals received from the comparator circuit 48 to obtain the Abtim direction.
  • the circuit described has the advantage that the window width is independent of the setting of the variable resistor 3.
  • the dimensioning of the resistors within the voltage divider circuit and the arrangement of the resistors 6 and 7 to obtain the comparator switching points ensures that a change in setting due to a possibly necessary replacement of components results in the same potential shifts at the inputs 18 and 19 of the comparators 20 and 21 Has.
  • the 4PSK demodulator circuit 47 includes a phase-locked loop 47, 51, 50, 36 (PLL) in which, when the signal is received to recover the carrier signal that is not present in the signal spectrum, the control input of a voltage-controlled oscillator (VCO) 36 is one of the output signals from the control signal 4PSK demodulator circuit 47 obtained tuning voltage is fed through a loop filter 51 and a subsequent VCO temperature compensation circuit 50.
  • VCO voltage-controlled oscillator
  • connection from the control input of the VCO 36 to a switch 37, via which the control input can be connected to the tap 10 of the variable resistor 3 with simultaneous interruption of the phase locked loop.
  • This connection is provided for the basic setting of the free-running VCO 36 to a frequency of 70 MHz at a positive potential + 6.7 V at the tap 10 before the adjustment of the 4PSK demodulator circuit.
  • the output voltage of the loop filter 51 is a direct measure of the frequency or frequency deposits of the carrier signal in the intermediate frequency positions.
  • the evaluation circuit 40 can simulate the existence of such a synchronous signal even in the absence of a synchronous signal and adversely affect the coordination.
  • Fig. 3 shows a circuit for obtaining an error signal, i.e. an error signal for controlling the control circuit 34, with which this effect can be overcome.
  • an error signal i.e. an error signal for controlling the control circuit 34
  • Synchronous signal evaluation circuit 40 connected a circuit for integrating concealment signals.
  • concealment signals are usually generated and evaluated in evaluation circuits for processing digital signals, for example by means of an IC SAA 7500.
  • These concealment signals are integrated in FIG. 3. This is achieved by means of an RC element 53, 54, by means of which the capacitor 54 is charged from the operating voltage ÜB via the resistor 53 to a logic high voltage. This voltage is at the input of control circuit 34 in FIG. 1. The full logic high voltage indicates that the search is initiated. This state of charge of the capacitor 54 is retained as long as a large number of error signals occur at the input of the evaluation circuit 40.
  • the capacitor 54 is discharged via the resistor 55, the diode 56 and the circuit 40; the voltage at the input of the control circuit 34 drops to logic low and causes a switchover to tuning with a small step width until the window area around the center frequency of the demodulator 47 is reached.
  • a larger time constant is favorable for charging the capacitor 54 with the resistor 53.
  • a small time constant is required for the discharge above 57, 40, ie for the switchover to fine tuning.
  • a microprocessor for example of the type ⁇ PD7811, is advantageous for the control circuit 34.
  • the latter can not only take over the tasks of the control circuit 34, but also, in addition to evaluating the information from the comparator 48 and the synchronizing signal circuit 40 for the search and fine-tuning process, also the timing of the switchover of the control circuit 34 according to FIG. 3 for querying the tax ⁇ lines 481 and 482 and for step-by-step changes in the frequency of the oscillator 44.
  • the processor inserts different waiting times to ensure that the system settles correctly, which can replace or support the integration according to FIG. 3. Under unfavorable reception conditions, brief failures of the synchronization can occur. At this time, the processor must not immediately switch to the search mode because otherwise long mute times would interfere. The processor waits for a new synchronization of the system in a predetermined period of time without changing the tuning of the oscillator.
  • the circuit shown in FIG. 1 can be modified such that the frequency of the oscillator 36 is evaluated in a high-precision discriminator and the control voltage is fed to the comparator circuit 48. This reduces the temperature influences.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Astronomy & Astrophysics (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Superheterodyne Receivers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Radio Relay Systems (AREA)

Abstract

Un récepteur de radiodiffusion par satellite reçoit les signaux d'une installation de réception de satellite qui comporte un ou plusieurs changeurs de fréquence. Ces changeurs de fréquence peuvent être soumis à une déviation de fréquence, par exemple sous l'influence de la température, qui ne peut être compensée par un circuit de commande d'audiofréquence (AFC) contenue dans le récepteur de radiodiffusion par satellite et qui commande un oscillateur d'onde porteuse pour la régénération de porteuse dans un circuit de démodulation. Un oscillateur local prévu pour un mélangeur est transformé en oscillateur local à verrouillage de phase (PLL) (44) accordable avec de grands ou de petits incréments. Le circuit AFC (1) et un circuit d'évaluation de signaux de synchronisation (40) sont reliés à un circuit de commande (34) par lequel l'oscillateur local PLL (44) est accordé en dehors de la plage de réglage du circuit AFC (1) en cas de signaux de synchronisation non reconnus à grands incréments ou de signaux de synchronisation connus à petits incréments jusque dans la plage de réglage du circuit AFC (1). Le récepteur de radiodiffusion par satellite décrit peut être connecté à des installations de réception de satellite, où l'on constate une déviation sommaire de la fréquence d'entrée nominale due à la présence de plusieurs changeurs de fréquence, ou à des appareils individuels privés, où la stabilité de fréquence est limitée pour des raisons de coût.
EP89912437A 1988-11-02 1989-10-31 Recepteur de radiodiffusion par satellite Pending EP0441851A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3837130A DE3837130A1 (de) 1988-11-02 1988-11-02 Satelliten-rundfunkempfaenger
DE3837130 1988-11-02

Publications (1)

Publication Number Publication Date
EP0441851A1 true EP0441851A1 (fr) 1991-08-21

Family

ID=6366294

Family Applications (2)

Application Number Title Priority Date Filing Date
EP89120170A Expired - Lifetime EP0367214B1 (fr) 1988-11-02 1989-10-31 Récepteur de radiodiffusion par satellite
EP89912437A Pending EP0441851A1 (fr) 1988-11-02 1989-10-31 Recepteur de radiodiffusion par satellite

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP89120170A Expired - Lifetime EP0367214B1 (fr) 1988-11-02 1989-10-31 Récepteur de radiodiffusion par satellite

Country Status (15)

Country Link
EP (2) EP0367214B1 (fr)
JP (1) JP3037352B2 (fr)
KR (1) KR0158187B1 (fr)
CN (1) CN1042460A (fr)
AT (1) ATE158905T1 (fr)
AU (1) AU4514289A (fr)
DD (1) DD286072A5 (fr)
DE (2) DE3837130A1 (fr)
ES (1) ES2109220T3 (fr)
FI (1) FI102436B1 (fr)
HU (2) HU208201B (fr)
MY (1) MY104459A (fr)
TR (1) TR25651A (fr)
WO (1) WO1990005410A1 (fr)
ZA (1) ZA898312B (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4003082C1 (en) * 1990-02-02 1991-06-20 Blaupunkt-Werke Gmbh, 3200 Hildesheim, De Sound broadcasting station receiver esp. UHF car radio - controls frequency of mixing oscillator using program memory for subcarriers
JPH05268501A (ja) * 1991-12-27 1993-10-15 Gold Star Co Ltd 衛星放送受信システム
EP0626775A1 (fr) * 1993-05-22 1994-11-30 SELECO S.p.A. Dispositif d'accord automatique comportant un circuit de synthèse de tension et une mémoire numérique
JPH09219693A (ja) * 1996-02-09 1997-08-19 Mitsubishi Electric Corp デジタル放送受信機
DE19815953C1 (de) * 1998-04-09 1999-09-23 Grundig Ag Verfahren und Vorrichtung zur Kompensation von Frequenzabweichungen beim Empfang von Satelliten-Rundfunksignalen mittels einer Satellitenempfangsanlage
GB2368751B (en) * 2000-09-20 2004-04-21 Nec Technologies Removal of reference frequency offset of a local oscillator in a telecommunications receiver
EP1926306A1 (fr) * 2006-11-24 2008-05-28 Thomson Licensing Dispositif et procédé pour l'accord fin automatique basé sur la détection du signal de synchronisation
CN103188175B (zh) * 2011-12-30 2018-05-04 国民技术股份有限公司 一种频率补偿电路、解调系统及解调方法
CN115528941B (zh) * 2022-10-18 2026-04-07 上海大学 一种三相逆变器的管压降自动补偿方法
CN119995695B (zh) * 2025-04-15 2025-10-28 中国星网网络系统研究院有限公司 卫星时频基准小步调频功能的测试方法及测试系统

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4041535A (en) * 1976-07-22 1977-08-09 Matsushita Electric Corporation Of America Frequency synthesizer tuning system with signal seek control
JPS5657324A (en) * 1979-10-16 1981-05-19 Sanyo Electric Co Ltd Digital electronic tuning system
US4476580A (en) * 1980-06-17 1984-10-09 Sanyo Electric Co., Ltd. Automatic continuous tuning control apparatus for a receiver
US4538175A (en) * 1980-07-11 1985-08-27 Microdyne Corporation Receive only earth satellite ground station
US4367558A (en) * 1980-12-22 1983-01-04 Motorola, Inc. Method for automatically searching for an RF station
US4405947A (en) * 1981-05-08 1983-09-20 Rca Corporation Dual search mode type tuning system
JPS57208465A (en) * 1981-06-18 1982-12-21 Pioneer Electronic Corp Discriminating circuit for frequency
JPS5915335A (ja) * 1982-07-15 1984-01-26 Maspro Denkoh Corp 衛星放送受信装置
US4498191A (en) * 1983-06-06 1985-02-05 General Electric Company Digital automatic frequency control with tracking

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9005410A1 *

Also Published As

Publication number Publication date
EP0367214A1 (fr) 1990-05-09
EP0367214B1 (fr) 1997-10-01
WO1990005410A1 (fr) 1990-05-17
DE58909819D1 (de) 1997-11-06
HU208201B (en) 1993-08-30
TR25651A (tr) 1993-05-12
AU4514289A (en) 1990-05-28
DD286072A5 (de) 1991-01-10
JP3037352B2 (ja) 2000-04-24
ATE158905T1 (de) 1997-10-15
ZA898312B (en) 1990-07-25
JPH04501640A (ja) 1992-03-19
FI102436B (fi) 1998-11-30
FI102436B1 (fi) 1998-11-30
KR0158187B1 (ko) 1999-03-20
HU896588D0 (en) 1991-07-29
MY104459A (en) 1994-03-31
CN1042460A (zh) 1990-05-23
DE3837130A1 (de) 1990-05-03
ES2109220T3 (es) 1998-01-16
KR900702647A (ko) 1990-12-08
FI912111A0 (fi) 1991-04-30

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