EP0466948B1 - Système de communication avec un système multiprocesseur servant comme contrÔle central - Google Patents

Système de communication avec un système multiprocesseur servant comme contrÔle central Download PDF

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Publication number
EP0466948B1
EP0466948B1 EP90113584A EP90113584A EP0466948B1 EP 0466948 B1 EP0466948 B1 EP 0466948B1 EP 90113584 A EP90113584 A EP 90113584A EP 90113584 A EP90113584 A EP 90113584A EP 0466948 B1 EP0466948 B1 EP 0466948B1
Authority
EP
European Patent Office
Prior art keywords
message
callp
cmy
processing
ltg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP90113584A
Other languages
German (de)
English (en)
Other versions
EP0466948A1 (fr
Inventor
Mark Clark
Wolfgang Dr. Dipl.-Phys. Siegmund
Hans-Dieter Dr. Wunderlich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to ES90113584T priority Critical patent/ES2081876T3/es
Priority to EP90113584A priority patent/EP0466948B1/fr
Priority to DE59010106T priority patent/DE59010106D1/de
Priority to AT90113584T priority patent/ATE133805T1/de
Priority to US07/727,977 priority patent/US5327419A/en
Publication of EP0466948A1 publication Critical patent/EP0466948A1/fr
Application granted granted Critical
Publication of EP0466948B1 publication Critical patent/EP0466948B1/fr
Priority to GR960400125T priority patent/GR3018856T3/el
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored program control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Definitions

  • the invention relates to a method according to the preamble of patent claim 1.
  • a process running on a processor processes tasks / subtasks of, for example, error handling procedures, time monitoring procedures or procedures in switching technology.
  • two or more processes cannot process a subtask at the same time. This is controlled by process monitoring in the operating system. It is problematic, however, that different processes can access a memory register at the same time and thereby cause undefined states.
  • European patent application 0 274 715 A3 a method is described as a simultaneous one Access of two processes to a memory register can be prevented. The SECURE procedure described there prevents the entry of a processor number in the relevant memory registers from simultaneous access by a first process and a competing second process to this memory register.
  • the invention is based on the object of designing the communication system defined at the outset in such a way that the processing of tasks is coordinated in the correct sequence, and large-scale time delays are avoided.
  • the object is achieved by the features mentioned in the characterizing part of patent claim 1.
  • the introduction of the holding table is essential for the invention.
  • the exclusive locking of the central bus system by a processor for the duration of an access to the holding table means no restriction of the loss of dynamics of the multiprocessor system.
  • the holding procedure thus coordinates the tasks within the system.
  • the time advantage that is achieved through the parallel processing of tasks by different processors is far greater than the slight loss of time that arises from the coordination processes themselves (e.g. locking the central bus system, queuing processes, etc.).
  • the messages are stored according to the FIFO principle in an input list EL located in the common memory system CMY, and processed on the processes CALLP1 ... CALLP n assigned to the processors P1 ... P n . Furthermore, so-called channel registers CHR1 ... CHR n are assigned to a connection; It contains parameters about the current status of a connection (for example, which LTG x connection module the subscriber is connected to, or which switching matrix is included in the connection path).
  • participants A, B are connected to the LTG x connection module.
  • the A-participant lifts the handset of his terminal. In this way, it notifies the communication system of a connection request to a B subscriber that was not yet known. Lifting the handset causes the system to write the corresponding message M 1 in the input list EL provided for this purpose and located in the common memory system CMY.
  • the A-subscriber then tries to dial the number of the B-subscriber. This causes the system to write a corresponding message M2 in the EL input list.
  • An analogous procedure takes place with the messages M3, M4 of this connection and the messages from other connections.
  • CALLP n are in the active or passive state, depending on whether corresponding connection requests exist on the part of the participants.
  • a process is reported back to the operating system after a message has been processed.
  • the operating system assigns the process that has become free to process a new message. In the exemplary embodiment, this should be the message M1; this means that M1 is processed by the process CAllP x .
  • a second freed process CAllP y should process the message M2 at the same time.
  • Another process with higher priority can now interrupt the process CAllP x , for example. This means that the result of the message M 1 can only be stored later in the relevant memory registers (for example the channel register). The result of this is that the messages M 1 ...
  • M n originally stored in the input list EL according to the FIFO principle are now stored in the corresponding memory registers in the reverse order after they have been processed.
  • This order is the basis for further processing; however, in many cases it now represents a message sequence that is no longer logical in itself.
  • the establishment of a connection is characterized in that a message M 1 (lifting the handset) is followed by a message M 2 (dialing).
  • M 1 lifting the handset
  • M 2 dialing
  • reversing this order contradicts the logical establishment of a connection, which in itself leads to the immediate termination of this connection.
  • Such a termination can be avoided with the help of the holding table HT located in the common storage system CMY.
  • the messages M 1 ... M n of a connection from a source LTG x are particularly affected with regard to possible time delays, since here the immediate succession of two messages from the input list EL entails a greater probability of reversing the order.
  • Each currently activated process CALLP x must therefore, before processing a message M x , verify the origin of the message, in this case the LTG x connection module. This is done by analyzing the message header of the corresponding message that contains the place of origin. The relevant, currently activated process CALLP x then enters the indicator of the source of the message in the holding table HT. The entry is only made in the case when no other message from the same source is currently being processed, i.e. there is no indicator of the same source in the holding table HT. Otherwise, the relevant process CALLP x takes over the processing of the next message in the input list EL.
  • the relevant process CALLP x additionally describes the holding table HT with its own process-specific indicator and a time monitoring parameter, which will be discussed in more detail later.
  • the process CALLP deletes x the hallmark of the source in the holding table HT, which is now just another activated process CALLP y a message My can edit the same source LTG x.
  • This procedure ensures that only one message from one source is processed at a time and, consequently, that the order of processed messages is not reversed.
  • the input list EL is stored in a reserved memory area of the CMY memory system.
  • the beginning is marked by a bookmark READ - INDEX, the end by a character WRITE-INDEX.
  • the bookmark is used by the process CALLP x to process the message M x and is only increased when a message M x is read out by the process CALLP x .
  • the bookmark remains unchanged during "anticipatory" reading due to the holding procedure.
  • the first accessing process blocks the central bus system B: CMY for the duration of its access. This blocks access to all other devices connected to the central bus system B: CMY.
  • the central bus system B: CMY is blocked by a processor command provided for this purpose.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Computer And Data Communications (AREA)

Claims (5)

  1. Procédé destiné à empêcher que des informations se répètent dans un système de communication, qui comprend des groupes (LTG₁ à LTGn) de raccordement ayant chacun des terminaux, qui leur sont raccordés, ainsi qu'un système à processeur multiple destiné à la commande centrale, qui comporte un bus central (B : CMY) de système et une pluralité de processeurs (P₁ à Pn) étant connectés à ce bus central de système, et qui comporte un système (CMY) de mémoire relié également au bus (B : CMY) central de système, commun à toutes les unités du système à processeur multiple et comprenant au moins une liste (EL) d'introduction pour l'établissement/la gestion de liaisons de terminaux, les messages (M₁ à Mn) importants pour les liaisons et destinés au traitement postérieur étant mémorisés temporairement dans la liste (EL) d'introduction par des processus (CallP₁ à CallPn) se déroulant sur la pluralité de processeurs (P₁ à Pn),
    caractérisé en ce que,
    on rend dépendant le traitement d'un premier message (My) provenant de l'un des groupes (LTG₁ à LTGn) de raccordement et enregistré dans la liste (EL) d'introduction, par un premier processus (CallPy) se déroulant sur un premier processeur (Py), d'un second processus (CallPx) se déroulant sur un second processeur (Px) et traitant un second message (Mx), lorsque les premier et second messages (My) proviennent du même groupe (LTG₁ à LTGn) de raccordement, par le fait que le second processus (CallPx) traitant le second message (Mx) enregistre dans un tableau (HT) de maintien mis en oeuvre dans le système (CMY) commun de mémoire une caractéristique de ce groupe (LTG₁ à LTGn) de raccordement avant le début du traitement du second message (Mx) et n'efface de nouveau cette caractéristique que lorsque le traitement du second message (Mx) est terminé et par le fait que le premier processus (CallPy) ne prend en charge le traitement du premier message (My) que si à cet instant il n'y a aucune introduction de la caractéristique du même groupe (LTG₁ à LTGn) du raccordement dans le tableau (HT) de maintien par un autre processus.
  2. Procédé suivant la revendication 1, caractérisé en ce qu'un premier processus (CallPy) inhibé pendant le traitement du premier message (My) prend en charge le traitement du prochain message présent dans la liste (EL) d'introduction.
  3. Procédé suivant la revendication 1, caractérisé en ce qu'un contrôle temporel des processus (CallP₁ à CallPn) se déroulant sur la pluralité des processeurs (P₁ à Pn) est mis en oeuvre, ce contrôle temporel provoquant un effacement automatique de la caractéristique dans le tableau (HT) de maintien après une durée prescrite de manière fixe.
  4. Procédé suivant la revendication 1, caractérisé en ce que l'on empêche, en réservant de manière exclusive le bus (B : CMY) central de système pendant le temps de l'accès d'un processus (CallPx) justement activé au tableau (HT) de maintien, un accès simultané par un autre processus (CallPy) justement activé et concurrent.
  5. Procédé suivant la revendication 1, caractérisé en ce qu'une procédure de lecture/procédure d'écriture destinée à la lecture/écriture des messages (M₁ à Mn) importants dans la liste (EL) d'introduction utilise un signe (READ-INDEX) de lecture/ (WRITE- INDEX) d'écriture et la procédure de lecture est commandée de telle sorte que le signe (READ-INDEX) de lecture saute les vides engendrés par la procédure de maintien dans la liste (EL) d'introduction.
EP90113584A 1990-07-16 1990-07-16 Système de communication avec un système multiprocesseur servant comme contrÔle central Expired - Lifetime EP0466948B1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
ES90113584T ES2081876T3 (es) 1990-07-16 1990-07-16 Sistema de comunicacion con un sistema multiprocesador que sirve para el control central.
EP90113584A EP0466948B1 (fr) 1990-07-16 1990-07-16 Système de communication avec un système multiprocesseur servant comme contrÔle central
DE59010106T DE59010106D1 (de) 1990-07-16 1990-07-16 Kommunikationssystem mit einem der zentralen Steuerung dienenden Multiprozessorsystem
AT90113584T ATE133805T1 (de) 1990-07-16 1990-07-16 Kommunikationssystem mit einem der zentralen steuerung dienenden multiprozessorsystem
US07/727,977 US5327419A (en) 1990-07-16 1991-07-10 Communication system having a multiprocessor system serving the purpose of central control
GR960400125T GR3018856T3 (en) 1990-07-16 1996-02-01 Communications system with a multi-processor system serving as the central control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP90113584A EP0466948B1 (fr) 1990-07-16 1990-07-16 Système de communication avec un système multiprocesseur servant comme contrÔle central

Publications (2)

Publication Number Publication Date
EP0466948A1 EP0466948A1 (fr) 1992-01-22
EP0466948B1 true EP0466948B1 (fr) 1996-01-31

Family

ID=8204219

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90113584A Expired - Lifetime EP0466948B1 (fr) 1990-07-16 1990-07-16 Système de communication avec un système multiprocesseur servant comme contrÔle central

Country Status (6)

Country Link
US (1) US5327419A (fr)
EP (1) EP0466948B1 (fr)
AT (1) ATE133805T1 (fr)
DE (1) DE59010106D1 (fr)
ES (1) ES2081876T3 (fr)
GR (1) GR3018856T3 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0657083B1 (fr) * 1992-08-25 1996-07-03 Siemens Aktiengesellschaft Systeme de coordination de demandes de connexion
US5590176A (en) * 1993-08-30 1996-12-31 Lucent Technologies Inc. Arrangement for local trunk hunting in a distributed switching system
JPH07231483A (ja) * 1993-12-22 1995-08-29 Matsushita Electric Ind Co Ltd 無線データ通信システム
CA2137167C (fr) * 1993-12-22 1999-09-21 Tony J. Brice Methode et architecture de gestion de donnees
FR2762917B1 (fr) * 1997-05-02 1999-06-11 Alsthom Cge Alcatel Procede d'affectation dynamique de taches a des evenements arrivant sur un ensemble de files d'attente
FR2799020A1 (fr) * 1999-09-28 2001-03-30 Koninkl Philips Electronics Nv Dispositif a plusieurs processeurs ayant une interface pour une memoire collective
US6738840B1 (en) * 1999-08-31 2004-05-18 Koninklijke Philips Electronics N.V. Arrangement with a plurality of processors having an interface for a collective memory
US7089561B2 (en) * 2001-06-01 2006-08-08 Microsoft Corporation Methods and systems for creating and communicating with computer processes
US7133942B2 (en) * 2001-12-07 2006-11-07 International Business Machines Corporation Sequence-preserving multiprocessing system with multimode TDM buffer
US7596792B2 (en) * 2002-08-07 2009-09-29 Hewlett-Packard Development Company, L.P. Method and system for supporting a plurality of event types
JP2007264794A (ja) * 2006-03-27 2007-10-11 Fujitsu Ltd 並列分散処理プログラム及び並列分散処理システム
US9003413B1 (en) * 2009-09-28 2015-04-07 Xilinx, Inc. Thread synchronization by transitioning threads to spin lock and sleep state

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4073005A (en) * 1974-01-21 1978-02-07 Control Data Corporation Multi-processor computer system
JPS58140862A (ja) * 1982-02-16 1983-08-20 Toshiba Corp 相互排他方式
US4654845A (en) * 1985-03-18 1987-03-31 At&T Parallel call processing system and method
EP0362903B1 (fr) * 1985-10-15 1994-11-30 Unisys Corporation Processeur à usage spécial se chargeant de plusieurs fonctions du système d'exploitation dans un grand système de traitement de données
ATE78655T1 (de) * 1987-01-12 1992-08-15 Siemens Ag Verfahren zur lastverteilung unter den zentralen prozessoren einer multiprozessorzentralsteuereinheit eines vermittlungssystems.

Also Published As

Publication number Publication date
ATE133805T1 (de) 1996-02-15
US5327419A (en) 1994-07-05
DE59010106D1 (de) 1996-03-14
EP0466948A1 (fr) 1992-01-22
ES2081876T3 (es) 1996-03-16
GR3018856T3 (en) 1996-05-31

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