Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
  • H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
  • H03D3/02—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal
  • H03D3/04—Demodulation of angle-, frequency- or phase- modulated oscillations by detecting phase difference between two signals obtained from input signal by counting or integrating cycles of oscillations
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
  • H03K9/06—Demodulating pulses which have been modulated with a continuously-variable signal of frequency- or rate-modulated pulses
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K9/00—Demodulating pulses which have been modulated with a continuously-variable signal
  • H03K9/08—Demodulating pulses which have been modulated with a continuously-variable signal of duration- or width-mudulated pulses or of duty-cycle modulated pulses

Definitions

• This invention relates to a method and apparatus f detecting and demodulating signals with temporally modulat features, and particularly to frequency modulated signals.
• FM Frequency Modulation
• a sinusoidal carri signal of constant amplitude and frequency is modulated an input signal of a lower frequency and of varyi amplitude.
• FM thereby produces an output signal that constant in amplitude, varying in frequency in accordan with the input signal, and within a specified frequency ran called the deviation bandwidth.
• t instantaneous amplitude of the input signal is linear transformed into a change d ⁇ in the instantaneous frequen ⁇ (t) of the carrier frequency ⁇ c .
• a frequency demodulation must be performed using an demodulator.
• FM demodulators are well known, and consist of devic such as ratio detectors, Foster Seeley discriminators, phas locked loop detectors, pulse-counting detectors, a quadrature or coincidence detectors. All of the demodulators — whether implemented as analog or digit apparatus — pass data to post-processing stages, and ultimately to an output amplifier.
• the Heathkit AJ-1510 Digital FM Tuner employs a digital discrimination technique for demodulating a frequency modulated signal.
• the discriminator is of the pulse position modulation type, is inductorless and diodeless, and contains two integrated circuits: a retriggerable monostable multivibrator, and an operational amplifier.
• An input signal at the retriggerable monostable multivibrator causes it to change states for a fixed period of time, as determined by an RC network to provide a sequence of pulses of constant width and amplitude that are generated at about one-half of the IF rate. Each pulse represents a zero-crossing event.
• Signal information is represented as deviations in the frequency of the zero-crossing pulses from a constant IF frequency.
• the frequency modulated signals typically are amplified and "hard-limited” to produce square waves which have zero- crossings spaced in the same manner as the zero-crossings of the FM signals.
• the square waves are then converted into a sequence of constant width and amplitude pulses, one pulse for each zero-crossing of the modulated input signal.
• Each pulse is integrated (or filtered) and subsequently differentiated to reproduce the modulating input signal information.
• pulse integration demodulators that employ a single one-shot multivibrator that is triggered at each zero- crossing.
• recovery time difficulties are encountered during high frequency operation because the internal delay of the multivibrator approaches the period of the high frequency signals as the operating frequency is increased.
• a source of frequency modulated signals is coupled to a coincidence detector by a first and second signal path.
• the first and second signal paths have unequal signal del characteristics, so that the coincidence detector provid an output signal that includes a series of constant wid pulses, wherein pulse width is determined by a difference signal delay between the first and second signal paths.
• low pass filter is coupled to the coincidence detector recover the signal modulation represented by the series constant width pulses.
• An apparatus and method is provided for demodulating frequency modulated (FM) , pulse-width modulated (P M) , other temporally modulated signal.
• modulating signal informati is extracted from a modulated signal as numeric information.
• a hi gain stage is applied to an incoming FM signal to produce corresponding sequence of square waves.
• the period betwe zero-crossings of the square waves is precisely measured a represented numerically using a high-speed clock and at lea one counter.
• Numerical period information is then provid to a signal processor that serves to convert the sequence period measurement values into a demodulated signal with high signal-to-noise ratio.
• the resulting FM intermediate frequen (IF) signal is "hard-limited" to yield a hard-limited FM signal that substantially resembles a sequence of squa waves which are provided to a sign detector for detecti zero-crossings.
• the frequency the local oscillator signal . is chosen so as to yie relatively low FM IF frequencies.
• the sign detector coupled to a pair of gating circuits, each gating circuit being coupled to a respective pulse counter, and to a clock. The gating circuits are alternately enabled in accordance with the instantaneous sign of the hard-limited FM IF signal.
• each sample gating circuit When enabled, each sample gating circuit provides a sequence of clock pulses from the clock to a respective pulse counter. Each pulse counter stores a respective count value that represents the period between zero-crossings of the hard- limited FM IF signal.
• the foregoing elements together constitute a digital discriminator.
• a numerical processor connected to the counters of the digital discriminator, is responsive to the changing respective count values, and reconstructs in real time the original modulating input signal.
• the numerical processor performs calculations upon the signal including: weighting, scaling, impulse response filtering, windowing, and interpolation/decimation. Increasing the rate of the clock yields improved resolution in the reconstructed modulating signal, up to the maximum resolution of the counting circuit. Subsequent digital filtering provides a low pass filter function that effectively eliminates high frequency components.
• the digital demodulator of the invention exploits the linearity of digital processing to provide excellent performance. Since the demodulation method of the invention requires only low level signals and introduces minimal noise, lower total noise levels result, and a high signal-to-noise ratio is achieved. Consequently, the demodulator of the invention can more easily receive weak signals, and suffers fewer "drop-outs", a problem that is now common in fringe reception areas, as well as in dense urban centers. Also, the invention reduces the need for amplification of a received signal, thereby increasing reliability and reception quality. Therefore, at a given level of transmission power, greater transmission range is possible. One potential product area is in satellite broadcast applications; a smaller antenna could be used when the method of the invention is employed within the receiver.
• th invention can be practiced using currently available relatively inexpensive components. Also, since it i consistent and cooperative with existing modulation standard and transmission formats, the invention actually increase the value of the currently installed base of transmissio equipment. Although the invention provides benefits whe included in 2-way radio, cellular telephone, and FM broadcas applications, the invention is not limited to a specifi frequency band, or to a particular application.
• the demodulation method and apparatus of the inventio introduces negligible noise, as contrasted with the level of noise added by conventional FM demodulation circuitry.
• a so-terme "reciprocal fit count scaling" method is employed tha provides better performance than a linear count scalin method, and improved performance with respect to a least squares-fit, nonlinear count scaling method.
• Such improve performance provides an estimated signal with significantl higher scaling accuracy, lower total harmonic distortion, an an excellent signal-to-noise ratio.
• the reciproca count scaling method provides an exact analytic solution, an guarantees the most accurate and optimal results attainabl from a system of this type.
• Fig. 1 is a block diagram of a digital discriminato cooperative with a numerical processor
• Fig. IA is a block diagram of a digital discriminato cooperative with a signal processor
• Fig. IB is a block diagram of a digital discriminato cooperative with a digital to analog converter
• Fig.2 is a schematic diagram of a digital discriminator of the type which may be used in the circuits of Figs. 1, IA and IB;
• Fig. 3 is a flow diagram of a process implemented by the numerical processor of Fig. 1;
• Fig. 3 is a flow diagram of a process that includes reciprocal fit count scaling
• Fig. 3B is a flow diagram of a process that includes reciprocal fit count scaling and window functions
• Fig. 3C is a flow diagram of a process that includes a bounds-checking routine and a second order fit
• Fig. 4 is a plot of linear scaled and weighted count values versus the original count values, together with a plot of scaled and weighted count values augmented with a second-order nonlinear term versus the original count values;
• Fig. 5 is a plot of the difference of the linear scaled and weighted count values and the scaled and weighted count values augmented with a second-order nonlinear term, versus the original count values
• Fig. 6 is a plot of scaled and weighted count values augmented with a second-order nonlinear term versus the original count values, together with a plot of reciprocal fit count values versus the original count values
• Fig. 7 is a plot of the difference of the scaled and weighted count values augmented with a second-order nonlinear term and the reciprocal fit count values, versus the original count values.
• a digital discriminator 10 is shown in cooperation with a numerical processor 12.
• the digital discriminator 10 utilizes zero-crossing detection and period measurement of a "hard-limited" FM IF signal to recover an associated modulating signal by exploiting the fact that the instantaneous frequency of an FM IF signal is inversely proportional to the instantaneous period of t associated modulating signal.
• Discrimination is accomplished by applying "hard-limited" FM IF signal to the sign detector 14.
• an input signal is amplified and th clipped to provide what is essentially a square wave.
• T sign detector 14 ascertains the instantaneous polarity alo each corresponding half-cycle of the FM IF signal, there defining the moment of each zero-crossing.
• the peri between zero-crossings is determined by providing informati regarding the moment of each zero-crossing to gating circui 16 and 18.
• the gating circuits 16 and 18 are alternate enabled or disabled in accordance with the instantaneous si of the hard-limited FM IF signal provided by the si detector 14.
• each sample gating circu provides a sequence of clock pulses from the clock 20 to respective pulse counter 16 or 18 until the other pul counter 18 or 16 is enabled.
• a short sequence of clo pulses between zero-crossings corresponds to a lar modulating signal amplitude, while a long sequence of syst clock pulses corresponds to a small modulating sign amplitude.
• Each sequence of clock pulses is integrated a respective counter 22 or 24 to provide a count value th represents the period of a half cycle of the FM IF signa
• the counters 22 and 24 alternately provide count values the numerical processor 12, which can be a commercial available digital signal processor, such as the 2101 Digit Signal Processor by Analog Devices.
• t counters 22 and 24 alternately provide count values to signal processor 12' that can perform at least digital-t analog conversion.
• the output of the signal processor is usable demodulated signal.
• FIG. IB a preferred embodiment of the discriminator 10 of FIG. 1 will now be discussed.
• a hard limited IF FM signal 26 is applied to the primary winding of transformer 28.
• This transformer stage provides the required impedance matching to the preceding circuit stages and dc decoupling or blocking to the succeeding stage.
• the center tap of the secondary of transformer 28 is biased by a reference voltage source 29 at the mid-point of the circuit supply voltage to provide a DC reference voltage.
• the reference voltage source 29 establishes a voltage level about which the oppositely phased voltages developed across the secondary winding of transformer 28 are symmetrical.
• the signal 30 from the transformer 28 is limited in amplitude by small signal diodes 31-36, and is low pass filtered by resistor and capacitor pairs 38, 40 and 42, 44.
• This limited and filtered signal 46 is applied in a differential manner to the inverting and non-inverting inputs of comparator 48.
• Switching hysteresis is provided by applying positive feedback from both Q and ⁇ Q outputs via resistors 50 and 52, respectively.
• the comparator outputs Q and ⁇ Q produce gate pulses proportional in width to the zero crossings of the FM IF signal.
• This gate pulse is applied to one of the inputs on each of the NAND gates 54 and 56.
• Clock 58 provides a source of high frequency clock pulses which is similarly applied to the other inputs of NAND gates 54 and 56.
• the resultant output of NAND gates 54 and 56 contain multiple sample clock periods wherein the number of sample clock periods are directly proportional to the width of the gating pulse.
• Comparator 48 outputs Q and?-? are applied to one input of OR gate 60 and 62 this signal is combinatorially or'd with the READ signal to provide &CLR
• each counter is latched into the corresponding 8-bit lat on the rising edge of the alternate counters "gate pulse” and ⁇ Q . This allows the data to be latched before t information is cleared from the counter during the next val clear signal. Period information in the form of "cou values" are subsequently read from each counter on alternating basis. Data is available to the data bus duri a valid READ signal from the numerical processor 12 (FI 1), signal processor 12' (FIG. IA) or DAC 12" (FIG. IB). Given the incoming binary pulse-count data provided the counters 22 and 24, the system shown in the embodime of FIG. IB, for example, provides complete demodulation an FM IF signal, in the sense that a voltage proportional a commensurate with the binary pulse-count data is output the DAC 12.
• T filters used include, but are not limited to, direct fo (DF) , finite impulse response (FIR) , and infinite impul response (IIR) filter realizations.
• DF direct fo
• FIR finite impulse response
• IIR infinite impul response
• A(x) the filter output
• IIR coefficients a k previous inputs are convolved with FIR coefficients b--.
• Butterworth filter can be applied to a signal template, in real time, just prior to signal output to the DAC stage 12.
• a Butterworth filtering technique was chosen due to its exceptionally flat passband response, and approaches a true "brick-wall" type filter in its digital realization.
• the numerical processor 12 of Fig. 1 will now be discussed.
• DSP digital signal processing
• Current DSP microprocessors are typically based on the "Harvard Architecture".
• the primary difference between the Harvard-type and the Von Neumann-type architectures is the separate data and instruction buses within the Harvard Architecture chip. This bus scheme allows for simultaneous data and program memory fetches.
• DSP chip technology Another important innovation in DSP chip technology is the so-termed single cycle instruction set. This capability allows each instruction in a DSP chip to be executed in one clock cycle, brought about by implementing the instruction sets of DSP chips as part of the architecture itself, rather than in microcode, as is common in most non-DSP processors.
• Parallelism refers to the capability of a signal processing device to carry out more than one operation at a time.
• data may be read from the parallel data bus via parallel input/output port, while the address of the incomi data is being placed into the shifter stack and the ne program instruction is concurrently being fetched from t instruction stack.
• excellent "pseudocode" example of parallelism in a D processor is as follows: fetch an instruction; compute t next instruction's address; perform one or two da transfers; update one or two data address pointers; a perform a computation, all within a single cycle.
• Pelining refers to a process whereby the result( of a first operation within the processor are immediate available as input(s) to a second operation, without t added requirement that data be moved via a program step.
• the result of a shifter operation may be direct used as an input to a multiplier accumulator section.
• the numerical processor 12 of Fig. 1 receives zero- crossing interval information from the counters 22, 24, and performs a differentiation process, to be described below, on successive interval values to recover modulating amplitude information. Since there are two zero-crossing events in a sinusoidal wave, an instantaneous frequency value F(t) can be recovered by taking the reciprocal of twice the period T(t) between successive zero-crossing events. Thus,
• the zero-crossing periods T(t) are given (within the limits of quantization) by:
• the accuracy of the digitization process is therefo dependent upon the frequency of the clock.
• F clocl . l/T -lock .
• a typical system clock spe is 50 Megahertz, which results in an uncertainty e ⁇ 10 nanoseconds, as calculated from equation (3) .
• the me error in e(t) is zero, since the ideal quantization err probability density function is symmetric.
• t standard deviation is approximately 0.29*T clock , which is al the rms value of the uncertainty e(t) .
• the rms value of e( can also be considered as a measure of signal noise due digitization. For example, if the maximum period betwe zero-crossings is quantized using 256 quantizing increment the peak signal-to-rms-noise ratio would be 0.4%, or abo 48 db.
• the actual number of quantizing increments, i.e., clo pulses that fit within a zero-crossing period is bounded the deviation frequency (DF) bandwidth.
• the width of zero-crossing period is simply the clock frequency divid by twice the quantity "IF frequency ⁇ the DF frequency
• the maximum number of clock pulses in a digitiz sample is given by:
• N m x C 2T cl0Ck ( IF + DF ⁇ ) ] -- .
• DN F clock * DF / (IF 2 - DF 2 ) .
• BCD binary coded decimal
• Count values provided to the numerical processor 12 are scaled and weighted, as explained below, to exploit the full n-bit range of the numerical processor.
• a "windowing" process for pulse averaging, using a Rectangular Window, or a Hamming Window, for example, and for providing data filtering and a preliminary treatment of digital quantization errors; and low-pass filtering, for limiting the data to a specific frequency band, and for removing noise, thereby improving the signal-to-noise ratio.
• Data thus processed by the numerical processor 12 is subsequently provided to a digital-to-analog converter (DAC) .
• DAC digital-to-analog converter
• N(i) represents the "i"th time-period count value between zero-crossings "i-1" and "i”
• A(i) is the "i"th scaled and weighted count value.
• the constants a and b are found using the full-sca positive (FSP) , and full-scale negative (FSN) DSP process values.
• the FSP and FSN values are determined by t "full-range" n-bit value, e.g., 65,536 for 16 bits, such th FSP is equal to (Full-Range)/2-1, and FSN is equal -(Full-Range) /2, expressed in a two's complement bina representation.
• a and b are given by:
• a so-term rectangular averaging window of width M slides over t scaled and weighted count values A(i) , where M is the numb of count values within the averaging window, and the M cou values are averaged together to provide an average scaled a weighted count value A(j) over the last M count values.
• value A(j) can be generated for each A(i) by advancing t window by one count value to A(i-t-l) , or a value A(j) can generated for every nth count value A(i+n) to reduce the da rate, thereby allowing more time for other operations.
• A(j) (1 / M) * SUM(A(i) ) , (9b)
• Window functions such as the simple window averaging just described are used to pre-condition incoming data.
• Other typical window functions are, for example, of the Hamming or Von Hann type, that generally serve to deemphasize the effect of certain coefficients within a sliding window, while augment the effect of others within the window.
• the Hamming window coefficients w H (n) are of form:
• w H (m) [a, b, c], where a, b, and c are constants computed according to equation (14) .
• the window can advance by one or more count values, and upon each advance, the inner product of the array w H (m) and the array of values within the window is computed to yield a scalar quantity. To reduce the data rate, the window can advance by more than one value each time it advances.
• the Hamming or Von Hann window function can be used in addition to, or in place of, the simple rectangular window averaging scheme discussed above.
• the method of the invention employs low-pass filtering to reduce inband noise, and smooth out residual quantization jitter.
• the filters used include, but are not limited to, direct form (DF) , finite impulse response (FIR) , and infinite impulse response (IIR) filter realizations.
• A(x) the filter output
• A(x - k) the filter output
• previous outputs, A(x - k) a convolved with IIR coefficients a k
• previous inputs a convolved with FIR coefficients t ⁇ .
• a low order (e.g. 5-10 zer and poles) IIR Butterworth filter is applied to a sign template, in real time, just prior to signal output to t
• Fig. 3 illustrates the sequence of process used to transform the sequence of count values provided the discriminator 10 of Fig. 1 to the numerical processor 1
• the values N are first weighted and scaled (90) , and then a window averaged (92) , thereby reducing the rate of da passed to subsequent calculations.
• a window transformation technique such as
• T data is then filtered (96) by a low-pass filter, just pri to being introduced to the DAC step (98) .
• the clock rate for measuring zero-crossing intervals preferably a rate of generally at least 8 times the Nyqui rate of the highest audio frequencies encountered so as minimize distortion.
• the zero-crossing periods T(t) of equation (1) are giv within the limits of count sample quantization uncertaint i.e., one clock period (e,g., about 100 nanoseconds), equation (2) .
• a so-termed "bounds-checking" routine is used.
• noise manifests itself as count anomalies. These count anomalies occur throughout the full range of count values, including "In-Band Noise", which falls within the range of N ⁇ to H, ⁇ .
• the numerical processor implements the bounds-checking routine, which routine parses through incoming zero-crossing count data, and identifies data which falls outside of the range N,-,--. to - a -- ; by testing for data below N min and testing for data above N ⁇ . Should a value fall outside of the range of N ⁇ to N m _ 0 ., it is assigned a value at a corresponding extremum point, i.e., the FSN or FSP point.
• the bounds- checking routine is shown in Fig. 3C as step 126, occurring after the step of period measurement 124. Steps 128-136 illustrate subsequent steps in a polynomial curve-fitting method, described below.
• Equation (9) in conjunction with incoming binary count data, represents a complete signal demodulation estimation process.
• Equation (9) is the equation of a straight line
• equation (1) is the equation of a reciprocal function. Over a very short region, a straight line can sufficiently model a curve.
• the range of numbers encompassed here is large, suggesting that a "linear fit" might perform well only at the endpoints of the range of the fit, i.e., between and N ⁇ , and poorly in the middle of this range, i.e., at linear IF.
• N 200
• the FSP Value, FSN Value, and an Intermediate Value used to generate a second-order nonlinear equation w coefficients that make the nonlinear equation "closest” the expression of equation (1) in a "Least Squares” sen
• the coefficients for estimating data in the range N min to can be found using a least-squares-fit process, such as employing the Vandermonde matrix, as can be found in the MATHLAB User's Guide, by the MATHWORKS, October 1990.
• polynomial solution is of form
• c 0 , c,, and c 2 are the zeroth, first, and second or coefficients respectively, and N is an incoming zero-cross count value.
• Intermediate Value equal to zero (0)
• Fig. 4 shows the sec order solution in the range of zero-crossing count val from 166 to 250, with the data curve corresponding to the linear equation overlaid as a reference.
• a data set was generated which contains the difference between the linear and the second order fit.
• the results are shown in Fig. 5, wherein it can be determined that almost 75% of the estimated values from the linear fit will incur at least 5% error.
• a so-termed "reciprocal fit count scaling" method is employed that provides better performance than the linear count scaling method, and improved performance with respect to the least-squares-fit nonlinear count scaling method.
• Such improved performance provides an estimated signal with significantly higher scaling accuracy, lower total harmonic distortion, and an excellent signal-to-noise ratio.
• the reciprocal count scaling method provides an exact analytic solution, and guarantees the most accurate and optimal results attainable from a system of this type.
• the value of the average instantaneous frequency F is bounded by the deviation frequency extrema DF- ⁇ and DF where OF B ⁇ a is equal to -DF- ⁇ .
• number of counts N(t) within a period T(t) is direc proportional to the reciprocal of the product of the sys clock period T -lock with the instantaneous deviation freque "IF + DF(t)".
• N(t) [ 2T cl0Ck (IF + DF(t) ) ]--.
• N m [ 2T cl ⁇ k (IF + DF ⁇ ) ]-'.
• N min [ 2T clock (IF + DF ⁇ ) ] " ' .
• Count values N(t) are provided to the numeri processor 12 that scales and weights the count values N according to a set of scaling and weighting coefficients provide scaled and weighted values.
• the numerical processor empl its full "n-bit" range, and may apply a linear fit meth a least squares fit method, or a reciprocal fit (RF) meth
• RF reciprocal fit
• N(i) represents the "i"th time-period sam count value between zero-crossings "i-1" and "i”
• A represents the "i"th scaled and weighted count value, with maximum/minimum extrema of +2 15 .
• Equation (19) in conjunction with the incoming binary count data and a precalculated knowledge of the count extrema, represents a complete signal demodulation method.
• the parameters a and b are found using full-scale positive (FSP) and full-scale negative (FSN) numerical processor values.
• the FSP and FSN values of the numerical processor are determined by the "full-range” n-bit value, i.e., 65536 for 16 bits, where FSP is equal to "full range/2 - 1", and FSN is equal to "-full range/2".
• a and b are evaluated by
• A(i) [FSP/(N ⁇ - ⁇ ] * ( (2*N B ⁇ l *N n ⁇ lx /N i ) - (N ⁇ +N- ⁇ +N- ⁇ )! . (24)
• the least squares nonlinear scaling method provides a very high level of sig resolution, making the theoretically predicted differe between the least squares method and the exact reciprocal scaling method apparently inconsequential.
• the average theoretical error associated with the le squares approximation as compared to the reciprocal scaling method is 0.20%, i.e., 0.02 dB difference, while maximum theoretical error associated with any given d point is just 1.0%, i.e., 0.1 dB difference.
• reciprocal fit scaling method provides an improvement signal-to-noise ratio of approximately 1 dB.
• the optimal choice is the recipro fit scaling method.
• Figs. 3A and 3B show how the reciprocal fit steps and 112, respectively, occur in two exemplary embodiments the method of the invention. Steps 100, 104-108, 110,

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