EP0694932B1 - Drosselspuleanordnung - Google Patents

Drosselspuleanordnung Download PDF

Info

Publication number
EP0694932B1
EP0694932B1 EP95304759A EP95304759A EP0694932B1 EP 0694932 B1 EP0694932 B1 EP 0694932B1 EP 95304759 A EP95304759 A EP 95304759A EP 95304759 A EP95304759 A EP 95304759A EP 0694932 B1 EP0694932 B1 EP 0694932B1
Authority
EP
European Patent Office
Prior art keywords
metallisation
inductor
spiral
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP95304759A
Other languages
English (en)
French (fr)
Other versions
EP0694932A1 (de
Inventor
David John Pedder
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intarsia Corp
Original Assignee
Intarsia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intarsia Corp filed Critical Intarsia Corp
Publication of EP0694932A1 publication Critical patent/EP0694932A1/de
Application granted granted Critical
Publication of EP0694932B1 publication Critical patent/EP0694932B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H01F27/29—Terminals; Tapping arrangements for signal inductances
    • H01F27/292—Surface mounted devices

Definitions

  • Very compact inductors may also be realised in an integrated form within the upper metallisation layers of a multichip module type D (MCM-D) substrate structure.
  • MCM-D multichip module type D
  • Such inductors can provide inductance values between 1 and 100 nH within a 1mm square footprint (using single or multilayer spiral structures), with self resonant frequencies between 20GHz and 500 Mhz.
  • Quality factor in these MCM-D inductors is determined by the inductor resistance at low frequencies, while the peak quality factor is related to the nature and dielectric structure of the substrate employed.
  • High resistivity silicon substrates with inductors defined in an aluminiumm-polyimide structure can provide quality factors between about 5 and 20, depending upon the inductor structure and inductance value.
  • the inductor device comprises a trimmable metallisation layer formed on the second major surface of said second substrate.
  • the completed single or multilayer plated copper inductor structure is then coated with a suitable passivation (for example a layer of silicon nitride) or a metallic, non-solderable barrier layer material (for example chromium or titanium). If a nonconducting passivation layer is employed, then vias are opened in this layer at the locations where input and output connections are required.
  • a suitable passivation for example a layer of silicon nitride
  • a metallic, non-solderable barrier layer material for example chromium or titanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Magnetic Heads (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Vehicle Body Suspensions (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)

Claims (8)

  1. Drosselspulen-Einrichtung für eine Anbringung auf einem Multichip-Modul, auf einer Direkt-Chip-Befestigungs-Anordnung oder auf einer Oberflächenanbringungs-Anordnung, wobei das Multichip-Modul, die Direkt-Chip-Befestigungs-Anordnung oder die Oberflächenanbringungs-Anordnung umfasst: ein erstes im wesentlichen planares Substrat (4) aus einem elektrisch isolierenden Material, wobei das erste Substrat darauf eine Vielzahl von elektrisch verbindenden Strukturen aufweist, dadurch gekennzeichnet, dass die Einrichtung ein zweites im wesentlichen planares Substrat (2) aus einem elektrisch isolierenden Material, welches erste und zweite gegenüberliegende Hauptoberflächen aufweist, eine spiralförmige Metallisierungsstruktur (1), die auf der ersten Hauptoberfläche des zweiten Substrats (2) ein induktives Element definierend gebildet ist, und eine Vielzahl von Lötbumps (3), die auf der ersten Hauptoberfläche gebildet sind, wobei wenigstens zwei der Lötbumps auf der spiralförmigen Metallisierungsstruktur (1) zum elektrischen Verbinden der spiralförmigen Metallisierungsstruktur mit jeweiligen der elektrisch verbindenden Strukturen auf dem ersten Substrat (4) gebildet sind.
  2. Drosselspulen-Einrichtung nach Anspruch 1, wobei eine trimmbare Metallisierungsschicht (6) auf der zweiten Hauptoberfläche des zweiten Substrats (2) gebildet ist.
  3. Drosselspulen-Einrichtung nach Anspruch 1, wobei die spiralförmige Metallisierungsstruktur (1) auf einer Schicht (5) aus einem Material mit geringer Permitivität, aufgebracht auf dem zweiten Substrat, gebildet ist.
  4. Drosselspulen-Einrichtung nach Anspruch 2, wobei die trimmbare Metallisierungsschicht (6) in einem konzentrischen Ringmuster gebildet ist.
  5. Drosselspulen-Einrichtung nach Anspruch 2, wobei die trimmbare Metallisierungsschicht (6) in einem spiralförmigen Muster gebildet ist.
  6. Drosselspulen-Einrichtung nach Anspruch 1, wobei wenigstens ein Teil der spiralförmigen Metallisierungsstruktur (1) mit einer nicht-lötbaren Metallisierungsschicht beschichtet ist.
  7. Drosselspulen-Einrichtung nach Anspruch 1, wobei wenigstens ein Teil der spiralförmigen Metallisierungsstruktur (1) mit einer Schicht aus einem elektrisch isolierenden Material beschichtet ist.
  8. Drosselspulen-Einrichtung nach Anspruch 1, wobei das zweite Substrat (2) ein Ferritmaterial ist.
EP95304759A 1994-07-29 1995-07-07 Drosselspuleanordnung Expired - Lifetime EP0694932B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9415316A GB2292016B (en) 1994-07-29 1994-07-29 Inductor device
GB9415316 1994-07-29

Publications (2)

Publication Number Publication Date
EP0694932A1 EP0694932A1 (de) 1996-01-31
EP0694932B1 true EP0694932B1 (de) 2003-02-26

Family

ID=10759075

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95304759A Expired - Lifetime EP0694932B1 (de) 1994-07-29 1995-07-07 Drosselspuleanordnung

Country Status (5)

Country Link
EP (1) EP0694932B1 (de)
JP (1) JPH0864422A (de)
AT (1) ATE233428T1 (de)
DE (1) DE69529709D1 (de)
GB (1) GB2292016B (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19854234C1 (de) * 1998-11-24 2000-06-21 Bosch Gmbh Robert Induktives Bauelement mit planarer Leitungsstruktur und Verfahren zur Herstellung desselben
US6310386B1 (en) * 1998-12-17 2001-10-30 Philips Electronics North America Corp. High performance chip/package inductor integration
JP4005762B2 (ja) * 1999-06-30 2007-11-14 株式会社東芝 集積回路装置及びその製造方法
AU2001274414A1 (en) * 2000-06-30 2002-01-08 Jds Uniphase Corporation Microelectronic packages including reactive components, and methods of fabricating the same
US6894593B2 (en) * 2003-02-12 2005-05-17 Moog Inc. Torque motor
JP4291164B2 (ja) 2004-01-08 2009-07-08 富士通メディアデバイス株式会社 弾性表面波装置
JP2008198923A (ja) * 2007-02-15 2008-08-28 Matsushita Electric Ind Co Ltd コイル部品
US8539666B2 (en) 2011-11-10 2013-09-24 Harris Corporation Method for making an electrical inductor and related inductor devices
CN110797333B (zh) * 2018-08-01 2026-05-08 台达电子工业股份有限公司 功率模块及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2079066B (en) * 1980-06-23 1983-09-21 Hull Corp Trimmable electrical inductors
JPS58196005A (ja) * 1982-05-10 1983-11-15 Toutsuu:Kk インダクタおよびその製造方法
JPS63116410A (ja) * 1986-11-05 1988-05-20 Fujikura Ltd プリントコイルとそのインダクタンス調整方法
GB8902431D0 (en) * 1989-02-03 1989-03-22 Plessey Co Plc Flip chip solder bond structure for devices with gold based metallisation
EP0398485B1 (de) * 1989-05-16 1995-08-09 Gec-Marconi Limited Verfahren zur Herstellung einer Flip-Chip-Lötstruktur für Anordnungen mit Gold-Metallisierung
US5349743A (en) * 1991-05-02 1994-09-27 At&T Bell Laboratories Method of making a multilayer monolithic magnet component
EP0529503A1 (de) * 1991-08-22 1993-03-03 Hewlett-Packard Company Flip-chip-Vorrichtung mit flexibler Befestigung
US5363080A (en) * 1991-12-27 1994-11-08 Avx Corporation High accuracy surface mount inductor
JPH06140267A (ja) * 1992-10-29 1994-05-20 Kyocera Corp インダクタンスの調整方法
GB2290171B (en) * 1994-06-03 1998-01-21 Plessey Semiconductors Ltd Inductor chip device

Also Published As

Publication number Publication date
JPH0864422A (ja) 1996-03-08
GB9415316D0 (en) 1994-09-21
ATE233428T1 (de) 2003-03-15
GB2292016B (en) 1998-07-22
GB2292016A (en) 1996-02-07
EP0694932A1 (de) 1996-01-31
DE69529709D1 (de) 2003-04-03

Similar Documents

Publication Publication Date Title
EP0694933B1 (de) Struktur einer abgleichbaren Drosselspule
US5747870A (en) Multi-chip module inductor structure
US5478773A (en) Method of making an electronic device having an integrated inductor
EP0685857B1 (de) Chip-induktivität Anordnung
US6727571B2 (en) Inductor and method for adjusting the inductance thereof
KR100885352B1 (ko) 반도체 장치 및 반도체 장치의 제조 방법
US20030162386A1 (en) Semiconductor device and its manufacturing method
CA1182583A (en) Thin film discrete decoupling capacitor
US5773897A (en) Flip chip monolithic microwave integrated circuit with mushroom-shaped, solder-capped, plated metal bumps
JP2006287196A (ja) 高ｑプレーナインダクタおよびｉｐｄ応用例
US20080090406A1 (en) Via attached to a bond pad utilizing a tapered interconnect
EP0694932A1 (de) Drosselspuleanordnung
KR100844063B1 (ko) 전자 기판의 제조 방법, 전자 기판, 및 전자 기기
US20040164819A1 (en) Variable capacitance circuit, variable capacitance thin film capacitor and radio frequency device
CN110690131A (zh) 一种具有大键合力的三维异构焊接方法
US6159817A (en) Multi-tap thin film inductor
CN110739236A (zh) 一种具有防溢锡结构的新三维异构堆叠方法
CN117769126A (zh) 高共面度的电子元件及其制作方法
US5874199A (en) Method of forming oversized solder bumps
US12620530B2 (en) Device and process for implementing silicon carbide (SiC) surface mount devices
KR100348250B1 (ko) 마이크로 수동소자의 제조 방법
CN119153232B (zh) 电容芯片结构以及制造方法
WO2001004953A1 (en) Method for manufacturing a semiconductor device having a metal layer floating over a substrate
WO2002001638A2 (en) Microelectronic packages including reactive components, and methods of fabricating the same
JP2005302907A (ja) インダクタ

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AT DE ES FR IT

17P Request for examination filed

Effective date: 19960716

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: MITEL SEMICONDUCTOR LIMITED

17Q First examination report despatched

Effective date: 19981209

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: INTARSIA CORPORATION

RBV Designated contracting states (corrected)

Designated state(s): AT DE ES FR IT

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Designated state(s): AT DE ES FR IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20030226

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030226

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20030226

REF Corresponds to:

Ref document number: 69529709

Country of ref document: DE

Date of ref document: 20030403

Kind code of ref document: P

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20030527

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20030828

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

EN Fr: translation not filed
26N No opposition filed

Effective date: 20031127