EP0705465A1 - Reseau analogique et numerique configurable - Google Patents

Reseau analogique et numerique configurable

Info

Publication number
EP0705465A1
EP0705465A1 EP93915717A EP93915717A EP0705465A1 EP 0705465 A1 EP0705465 A1 EP 0705465A1 EP 93915717 A EP93915717 A EP 93915717A EP 93915717 A EP93915717 A EP 93915717A EP 0705465 A1 EP0705465 A1 EP 0705465A1
Authority
EP
European Patent Office
Prior art keywords
matrix
analog
array
basic
bbb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP93915717A
Other languages
German (de)
English (en)
Other versions
EP0705465B1 (fr
Inventor
Bedrich Hosticka
Werner Schardein
Berthold Weghaus
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Original Assignee
Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV filed Critical Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
Publication of EP0705465A1 publication Critical patent/EP0705465A1/fr
Application granted granted Critical
Publication of EP0705465B1 publication Critical patent/EP0705465B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • the present invention relates to a configurable, analog and digital array.
  • the subject matter of the invention relates to a configurable analog / digital module array.
  • User-programmable circuits in the form of configurable arrays have been known for a number of years.
  • the customary programmable circuits on the market are designed as configurable digital arrays.
  • Such user-programmable circuits therefore mainly cover the area of digital applications. It is common to such digital, user-programmable circuits that a plurality of cells are provided at gate level or register level, which can be programmed by the user and can be variably connected via prefabricated connection paths.
  • Such user-programmable circuits are often used only for checking a circuit design, and after the final circuit version has been determined, it must be converted into a so-called "full customer circuit".
  • full customer circuit Such an implementation is over with one prototypes existing in several different building blocks are generally not readily possible and generally require a so-called redesign.
  • European patent application EP-0499383A2 shows a user-programmable integrated circuit with an analog section with user-configurable analog circuit modules, a digital section with user-configurable digital circuit modules and an interface section with user-configurable interface circuits for analog / digital Signal conversion and for digital / analog signal conversion, and a user-configurable connection and input / output architecture.
  • the networking of the elements made possible by such a circuit is extremely limited. For example, no feedback between circuit elements is possible.
  • the known circuit can be programmed and controlled by connecting solid basic components to other components, as is shown, for example, in FIGS. 3a, 3b of this document.
  • resistors and capacitors can optionally be connected to existing circuit blocks.
  • a hierarchical structuring and organization that enables the construction of closed analog subsystems for the subsequent configuration within an overall system. light, is not possible with this known technique.
  • DE-3417670A1 shows a programmable analog circuit in the form of a programmable filter, in which a number of filter modules, an attenuator and an isolating amplifier can be interconnected in a user-programmable manner.
  • a number of filter modules, an attenuator and an isolating amplifier can be interconnected in a user-programmable manner.
  • the present invention is therefore based on the object of creating a configurable, analog and digital array with which an entire system with analog and optionally digital basic components can be configured largely freely by the user.
  • the configurable analog and digital array according to the invention comprises a hierarchical structure with at least two first-order matrix arrangements and at least one second-order matrix arrangement.
  • Each of the first-order matrix arrangements has a plurality of basic modules arranged in rows or columns, which are at least partially analog basic modules, and has a first switch matrix for controllable mutual connection of the signal inputs and / or the signal outputs of the basic building blocks and for the controllable connection thereof to matrix inputs and / or matrix outputs of this first-order matrix arrangement.
  • the second-order matrix arrangement comprises a second switch matrix for the controllable mutual connection of the matrix inputs and / or matrix outputs of the first-order matrix arrangement and for the controllable connection of the same with array inputs and / or array outputs.
  • the system defined in this way can include controllable analog and digital function blocks of different architectures and degrees of complexity in the form of an integrated circuit on a common substrate in such a way that the existing sub-modules or basic modules can be flexibly and reversibly interconnected and to a large extent as desired
  • Predefined overall system for mixed analog / digital signal processing can be configured.
  • This system therefore forms a "building block" with a certain basic quantity of basic building blocks in the form of analog and digital blocks, which can be parameterized and thus modified and can be interconnected or configured to form an overall system within certain limits.
  • the basic modules preferably have an analog and / or digital control input. Certain properties of the basic building blocks can thus be varied, ie parameterized, within specified limits.
  • the signals for the analog and digital control inputs of a basic module are programmed into writable, readable and erasable memory elements which serve as parameterization registers and which are located directly on the basic modules and can be reset or deleted there at any time .
  • properties such as its gain factor, its bandwidth, its power loss, its offset, etc. can be entered as required. be put.
  • a first-order matrix arrangement can optionally contain a multiplying digital / analog converter, to which a binary data word can be fed from such a parameterization register, so that the digital / analog converter generates an analog control signal on the output side with which the analog control input of the basic building block can be controlled.
  • the basic modules are configured to form an overall system by controlling the analog and digital control inputs of the basic module and by controlling switches of the first and second matrix arrangement via the matrix inputs and the array inputs.
  • a shift register is preferably provided, into which the data for the configuration can be read in serially and which forms the parameterization registers.
  • a parallel interface can be provided which enables the configuration data to be introduced in parallel into the array.
  • a host computer can be used to generate the configuration data to generate the control data.
  • a microcontroller can also be provided on a chip, which takes over the routing (setting of the configuration register), whereby it receives information supplied from outside in the form of e.g. evaluates a network list. This can also be temporarily stored in a separate area (RAM, EPROM or the like).
  • circuit arrangement of the first arrangement formed by the basic components within the matrix arrangement of the first order can be assembled into a practically freely selectable overall system by means of the matrix arrangement of the second or higher order.
  • the hierarchical structure according to the invention of the configurable array consisting of first-order matrix arrangements and at least one second-order matrix arrangement allows measures to be tested as well as testability by means of measures which are conventional in the field of digitally configurable arrays of the configured system.
  • all combinatorial logic functions are designed as minimalized functions for this purpose and can therefore be tested completely.
  • registers which are connected via a scan path.
  • Programmable signature registers and a boundary scan path can also be provided.
  • the observability of special internal nodes of the overall system is provided. This can be done, for example, by means of switchable decoupling elements (eg amplifiers), which in turn can optionally be switched to an output pin or an analog basic module. This should lead to a measurement which is essentially load-free for the network node.
  • the array structure according to the invention enables certain internal module connections to be separated and internal nodes to be set via external chips Inputs or module outputs.
  • the variable design of the array according to the invention enables the configuration of test systems which carry out an on-chip test and, with a suitable constellation, extensively check the functionality of the overall system. Mixed analog / digital parts can also be included in such self-test systems.
  • At least some of the basic modules are assigned a qualification register which is designed as a read / write memory or as a fixed value memory and at least information about the total failure of the basic module and, if appropriate, information about the operating properties of the basic module includes.
  • a qualification register which is designed as a read / write memory or as a fixed value memory and at least information about the total failure of the basic module and, if appropriate, information about the operating properties of the basic module includes.
  • special configuration measures can be used to extract component and circuit parameters for each individual chip on which the array is implemented. The results of this parameter extraction are then built into parameterizable functional macro models and used in all further simulations. It is thus possible to largely compensate for parameter variations in the component and circuit parameters caused by process fluctuations by adapting the simulation environment.
  • a characterization plan for specific circuit properties can then be drawn up for each chip, which can be used by the configuration software as the basis for qualifying each circuit part for specific tasks.
  • a unique identification code can be stored on each chip. This can be done, for example, in the form of a PROM area that is burned by the user, i.e. can be described as a read-only memory.
  • a qualification register By assigning a qualification register to each of the basic modules, information about the functionality of the basic modules can be stored. Like him- thinks such a qualification within the qualification register includes, for example, information about the total failure of the basic building block or features about other properties. On the one hand, this information can be determined by the manufacturer during testing and provided in the qualification registers, so that the chip yield can be increased. Since each module type occurs several times on the chip, there is sufficient redundancy. On the other hand, the qualification can also be carried out by the user at any time. This enables flexible qualification depending on the application. However, this method also allows failures that have occurred during operation to be localized, marked and avoided by reconfiguring the system, all qualification registers being taken into account. This aspect increases the reliability of the system, since it is possible to "repair" the system on site without having to intervene in the hardware.
  • those modules that are not statically lossless can be separated from the operating voltage via a power cut-off input.
  • This configuration makes it possible to deselect unused or defective basic modules and thus to reduce the power loss of the overall system.
  • this aspect can be of great importance.
  • such an input can also be controlled in certain time slots during operation to limit the power loss.
  • a separate memory element within the basic module which can be programmed separately, is preferably used to deselect a basic module.
  • the array according to the invention supplies adaptive systems.
  • the configured system can deliver output signals that modify the system itself in a certain way, ie reconfigure it automatically. This can be done, for example, by changing the programmable wiring or by changing the module properties. With a suitable design, the arrangements can be modified in real time.
  • the array according to the invention is preferably implemented in BICMOS technology.
  • This technology is particularly suitable because, on the one hand, it has the ability to perform high-quality analog functions through bipolar components and, on the other hand, it allows maximum integration through low-loss CMOS technology.
  • the concept of flexible interconnection requires good driver properties, the driver having to react flexibly to the load capacities. In principle, however, a solution in CMOS technology or in another technology suitable for large-scale integration is also conceivable.
  • the transfer of a prototype, which is configured on the array according to the invention, to an optimized circuit for larger quantities can be accomplished in a simple manner in that the data determined during the configuration, together with the analog and digital library elements, is added to the the desired overall system are bound together in a suitable CAD environment, elements that are not used being left out and the additions serving the wiring and programmability, such as multiplexers and registers, being replaced by fixed wiring. Since the entire system was already completely replicated within the configurable module array according to the invention, the problem of a transition to other modules does not arise with the technology according to the invention.
  • the analog basic building blocks of the array according to the invention include, for example, integrators, comparators, stronger, phase detectors and adjustable references.
  • the adjustable references can be realized by multiplying digital-to-analog converters.
  • 1 shows a second-order loop filter formed by basic building blocks within the first-order matrix arrangement
  • FIG. 3 shows a frequency-locked control loop (FLL) formed from the circuits according to FIGS. 1 and 2 by the second-order matrix arrangement;
  • FLL frequency-locked control loop
  • FIG. 6 shows an illustration of a second-order loop filter formed by the first-order matrix arrangement of the array according to the invention
  • FIG. 8 shows an illustration corresponding to FIG. 5 of the array according to the invention when programmed as a frequency-locked control loop.
  • 1 shows a first possible structuring within a first level of the array according to the invention, which, as will be further explained below, is formed by a first-order matrix arrangement. This is referred to as the first level, since only basic modules II, 12, VI are configured within this level.
  • the configuration shown here comprises two integrators II, 12 or low-pass filters of the first order, which can be controlled digitally for a coarse setting and analogously for a fine setting, and a likewise controllable amplifier VI.
  • Vdc With the reference symbol Vdc; Vac are digital or analog control inputs.
  • FIG. 2 shows a further first level of the array according to the invention, that is to say also a partial configuration of basic components, which is formed by a first-order matrix arrangement.
  • two voltage comparators K 1, K 2 are provided, which are followed by a phase detector PD.
  • Fig. 3 shows the block diagram of an FLL (Frequency Locked Loop), i.e. a frequency locked loop.
  • FLL Frequency Locked Loop
  • This circuit is formed from three blocks, which are each formed on the first level of the digital array according to the invention, as is illustrated by FIGS. 1 and 2.
  • the circuit shown in Fig. 3 can be referred to as a second level circuit.
  • the hierarchical structure of the analog / digital design of the entire array according to the invention is clear.
  • Macros of the first level are formed on the basis of basic building blocks, which in turn can configure a system of the second level, whereby this can also be done in conjunction with basic building blocks from the lower levels.
  • the exemplary embodiment shown here is structured over two levels. It is obvious to a person skilled in the art that the concept of a hierarchical array according to the invention can be carried out over several levels.
  • FIG. 4 shows the circuit architecture of a programmable, controllable transconductance amplifier OTA in differential path technology.
  • This structure is intended to clarify the control possibilities of a basic building block, representative of the other basic building blocks.
  • the digital setting is a rough setting. This is done by data word W2.
  • the fine adjustment takes place starting from the data word W1 via a programmable, multiplying digital / analog converter MDAC, such analog control voltages also being able to be provided externally.
  • a 10-bit latch L is used for digital programming both for the coarse adjustment and for the fine adjustment. These latches L are contained in the BBB rows / lines of the basic building blocks, which are shown in FIG. 5 and are explained in more detail below with reference to FIG. 5.
  • the digital control brings about a rough digital setting by switching on or off pre-configured current and voltage references within the first-order matrix arrangements via data word W2.
  • the transconductance can also be kept programmable.
  • references for dynamic adjustment can be scaled.
  • the embodiment shown there comprises an inventive configurable analog and digital array arrangement, four matrix arrangements M 11 # M 12 , M 13 , M 14 first order and a matrix arrangement M 2 second order.
  • Each first-order matrix arrangement MIT, M 12 ' M 1 3 ' M 14 comprises a plurality of basic building blocks BBB, which are shown there as BBB rows / lines 1 to 12.
  • the connections between the basic components within the matrix arrangements M ⁇ l , M 12 , M 13 , M 14 are made by means of first switch matrices S- ⁇ to S 4 , which in the example shown can be designed as (8 x 8) switch matrices.
  • decodable line selectors can be used on the periphery, which can separate and / or connect incoming and outgoing signal / supply paths. All external connections of the matrix can be programmed as inputs or outputs or bidirectional connections. Multiplexers in the selectors allow variable signal / supply routing.
  • crossing and linking two different elementary networking states, namely the crossing and linking, can primarily be implemented.
  • a crossing point MSU When a crossing point MSU is programmed, a conductive, bidirectional connection of a horizontal and a vertical line segment is created. Further intersection points MSU can be connected to these segments, so that line segments which run in parallel can also be realized. If the selectors at the matrix edges are deactivated, these line segments end at the matrix periphery.
  • the switching matrices are only shown without separation units. Unless otherwise shown, the signal paths in the structures shown each end at the matrix periphery. As is also shown in FIG.
  • the second-order matrix arrangement M 2 likewise comprises a switch matrix which, in the exemplary embodiment shown here, is designed as a (16 ⁇ 16) switch matrix.
  • the vertical signal lines of this matrix are the input and output lines of the switching matrices S ⁇ i to S 4 of the first-order matrix arrangements.
  • Horizontal lines of the switch matrix of the second-order matrix arrangement are formed by outputs of a 256-bit shift register 17 and array input and array output lines. The latter form an interface 18 for the array.
  • the switch matrices S- ⁇ to S 5 consist of 1-bit switches and memories, which are arranged field-shaped. By setting a “1” or “0”, signal and / or supply paths can be connected or separated.
  • FIG. 6 shows the implementation of the loop filter according to FIG. 1 by means of a first order matrix arrangement M ⁇ in the first level of the array.
  • Circuit elements denoted by the same reference numerals denote the same components in all the figures, so that their function and structure need not be explained again.
  • the configuration which is predetermined by the content of the shift register 13, selects certain basic modules from the BBB rows / lines 1, 2, 3 and interconnects them in the desired manner.
  • the function of the 64-bit shift register 13 for the analog configuration and that of the 16-bit shift register 19 for the rough digital control also become particularly clear here.
  • FIG. 7 shows a representation corresponding to FIG. 2 of a phase detector with two voltage comparators, as it is formed by the third matrix arrangement M 13 of the first order becomes.
  • the 64-bit shift register 15 is used for the analog configuration, while the 16-bit shift register 20 is used for the rough digital control.
  • FIG. 8 shows the entire wiring network which is formed by the array according to FIG. 5 in order to implement the frequency-locked control loop according to FIG. 3 in the second level of the array. Since the components have been explained with reference to the previous figures, no further explanation of the individual matrix arrangements is required.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Evolutionary Computation (AREA)
  • Fuzzy Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un réseau analogique et numérique réalisé en au moins deux plans dans une structure hiérarchisée. Ce réseau comprend au moins deux configurations matricielles du premier ordre dont chacune comporte une pluralité de modules de base disposés en rangs et/ou en colonnes, qui sont au moins en partie des modules de base analogiques, ainsi qu'une première matrice de commutation destinée à assurer la connexion mutuelle commandée des entrées et des sorties de signaux des modules de base et celle de ces derniers avec des entrées et des sorties matricielles. Ce réseau comprend également une configuration matricielle du second ordre qui comporte une seconde matrice de commutation destinée à assurer la connexion mutuelle commandée des entrées et des sorties matricielles des configurations matricielles du premier ordre et la connexion commandée de ces dernières avec les entrées et les sorties du réseau.
EP93915717A 1993-06-25 1993-06-25 Reseau analogique et numerique configurable Expired - Lifetime EP0705465B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP1993/001637 WO1995000921A1 (fr) 1993-06-25 1993-06-25 Reseau analogique et numerique configurable

Publications (2)

Publication Number Publication Date
EP0705465A1 true EP0705465A1 (fr) 1996-04-10
EP0705465B1 EP0705465B1 (fr) 1996-10-30

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US (1) US5677691A (fr)
EP (1) EP0705465B1 (fr)
DE (1) DE59304375D1 (fr)
WO (1) WO1995000921A1 (fr)

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Publication number Publication date
WO1995000921A1 (fr) 1995-01-05
US5677691A (en) 1997-10-14
DE59304375D1 (de) 1996-12-05
EP0705465B1 (fr) 1996-10-30

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