EP0705465B1 - Reseau analogique et numerique configurable - Google Patents

Reseau analogique et numerique configurable Download PDF

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Publication number
EP0705465B1
EP0705465B1 EP93915717A EP93915717A EP0705465B1 EP 0705465 B1 EP0705465 B1 EP 0705465B1 EP 93915717 A EP93915717 A EP 93915717A EP 93915717 A EP93915717 A EP 93915717A EP 0705465 B1 EP0705465 B1 EP 0705465B1
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Prior art keywords
array
matrix
analog
bbb
inputs
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German (de)
English (en)
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EP0705465A1 (fr
Inventor
Bedrich Hosticka
Werner Schardein
Berthold Weghaus
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Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
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Fraunhofer Gesellschaft zur Foerderung der Angewandten Forschung eV
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • the present invention relates to a configurable, analog and digital array.
  • the subject matter of the invention relates to a configurable analog / digital module array.
  • User programmable circuits in the form of configurable arrays have been known for a number of years.
  • the customary programmable circuits on the market are designed as configurable digital arrays.
  • Such user-programmable circuits therefore mainly cover the area of digital applications. It is common to such digital, user-programmable circuits that a plurality of cells are provided at gate level or register level, which can be programmed by the user and variably connected via pre-configured connection paths.
  • European patent application EP-0499383A2 shows a user-programmable integrated circuit with an analog section with user-configurable analog circuit modules, a digital section with user-configurable digital circuit modules and an interface section with user-configurable interface circuits for analog / digital signal conversion and for digital / analog signal conversion, and a user configurable Connection and input / output architecture.
  • the networking of the elements made possible by such a circuit is extremely limited. For example, no feedback between circuit elements is possible.
  • the known circuit can be programmed and controlled by wiring solid basic components with other components, as is shown, for example, in FIGS. 3a, 3b of this document. For example, resistors and capacitors can be connected to existing circuit blocks.
  • a hierarchical structuring and organization that enables the construction of completed analog subsystems for subsequent configuration within an overall system, is not possible with this known technique.
  • DE-3417670A1 shows a programmable analog circuit in the form of a programmable filter, in which a number of filter modules, an attenuator and an isolation amplifier can be interconnected in a user-programmable manner.
  • a number of filter modules, an attenuator and an isolation amplifier can be interconnected in a user-programmable manner.
  • US-A-4,847,612 shows a configurable array, with at least two first-order matrix arrangements, with a plurality of basic components arranged in rows and / or columns and a first switch matrix, and at least one second-order matrix arrangement with a second switch matrix, which comprises the at least two matrix arrangements connects first order, in which all the basic components are digital and the outputs are coupled via the first-order matrix arrangements.
  • the present invention is therefore based on the object of creating a configurable, analog and digital array with which a complete system with analog and possibly digital basic components can be configured largely freely by the user.
  • the configurable analog and digital array according to the invention comprises a hierarchical structure with at least two first-order matrix arrangements and at least one second-order matrix arrangement.
  • Each of the first-order matrix arrangements has a plurality of basic modules arranged in rows or columns, which are at least partially analog basic modules, and has a first switch matrix for controllable mutual connection of the signal inputs and / or the signal outputs of the basic building blocks and for the controllable connection thereof to matrix inputs and / or matrix outputs of this first-order matrix arrangement.
  • the second-order matrix arrangement comprises a second switch matrix for the controllable mutual connection of the matrix inputs and / or matrix outputs of the first-order matrix arrangement and for the controllable connection thereof to array inputs and / or array outputs.
  • the system defined in this way can include controllable analog and digital function blocks of different architectures and levels of complexity in the form of an integrated circuit on a common substrate in such a way that the existing sub-modules or basic modules can be flexibly and reversibly interconnected and form a largely arbitrarily predefinable overall system for the mixed analog / digital signal processing can be configured.
  • This system therefore forms a "building block" with a certain basic quantity of basic building blocks in the form of analog and digital blocks, which can be parameterized and thus modified and which can be interconnected or configured to form an overall system within certain limits.
  • the basic modules preferably have an analog and / or digital control input. Certain properties of the basic building blocks can thus be varied, ie parameterized, within specified limits.
  • the signals for the analog and digital control input of a basic module are programmed into writable, readable and erasable memory elements, which serve as parameterization registers and which are located directly on the basic modules, and can be reset or deleted there at any time.
  • properties such as its amplification factor, its bandwidth, its power loss, its offset etc. can be set as required will.
  • a first-order matrix arrangement can optionally contain a multiplying digital / analog converter, to which a binary data word can be fed from such a parameterization register, so that the digital / analog converter generates an analog control signal on the output side, with which the analog control input of the basic module is controlled can.
  • the configuration of basic modules to form an overall system is carried out by controlling the analog and digital control inputs of the basic module and by controlling switches of the first and second matrix arrangement via the matrix inputs and the array inputs.
  • a shift register is preferably provided, into which the data for the configuration can be read in serially and which forms the parameterization registers.
  • a parallel interface can be provided which enables the configuration data to be introduced in parallel into the array.
  • a host computer can be used to generate the configuration data to generate the control data.
  • a microcontroller can also be provided on a chip, which takes over the routing (setting of the configuration registers), whereby it receives information supplied from outside in the form of e.g. evaluates a network list. This can also be buffered in a separate area (RAM, EPROM or similar).
  • the first-order circuit arrangement formed by the basic components within the first-order matrix arrangement can be assembled into a practically freely selectable overall system by means of the second-order or higher-order matrix arrangement.
  • the hierarchical structure according to the invention of the configurable array consisting of first-order matrix arrangements and at least one second-order matrix arrangement allows both the testability of the individual basic components and the testability of the configured system by means of measures which are inherently common in the field of digitally configurable arrays.
  • all combinatorial logic functions in digital structures are designed as minimalized functions and are therefore fully testable.
  • the observability of special internal nodes of the overall system is provided. This can be done, for example, by means of switchable decoupling elements (e.g. amplifiers), which in turn can optionally be switched to an output pin or an analog basic module. This should lead to a measurement which is essentially load-free for the network node.
  • the array structure according to the invention enables certain internal module connections to be separated and internal nodes to be set via external chips Inputs or module outputs.
  • the variable design of the array according to the invention enables the configuration of test systems which carry out an on-chip test and, with a suitable constellation, extensively check the functionality of the overall system. Mixed analog / digital parts can also be included in such self-test systems.
  • At least some of the basic modules are assigned a qualification register which is designed as a read / write memory or as a read-only memory and contains at least information about the total failure of the basic module and possibly information about the operating properties of the basic module.
  • a qualification register which is designed as a read / write memory or as a read-only memory and contains at least information about the total failure of the basic module and possibly information about the operating properties of the basic module.
  • a characterization plan for specific circuit properties can then be drawn up for each chip, which can be used by the configuration software as the basis for qualifying each circuit part for specific tasks.
  • a unique identification code can be stored on each chip. This can be done, for example, in the form of a PROM area that is burned by the user, i.e. can be described as a read-only memory.
  • a qualification register By assigning a qualification register to each of the basic modules, information about the functionality of the basic modules can be stored. As mentioned, Such a qualification within the qualification register includes, for example, information about the total failure of the basic building block or features about other properties. On the one hand, this information can be determined by the manufacturer during testing and provided in the qualification registers, so that the chip yield can be increased. Since each module type occurs several times on the chip, there is sufficient redundancy. On the other hand, the qualification can also be carried out by the user at any time. This enables flexible qualification depending on the application. However, this procedure also makes it possible to localize failures that have occurred during operation, to mark them and to avoid them by reconfiguring the system, taking into account all qualification registers. This aspect increases the reliability of the system, since it is possible to "repair" the system on site without having to intervene in the hardware.
  • those modules that are not statically lossless can be separated from the operating voltage via a power cut-off input.
  • This configuration makes it possible to deselect unused or defective basic components and thus to reduce the power loss of the overall system.
  • this aspect can be of great importance.
  • such an input can also be controlled in certain time slots during operation to limit the power loss.
  • a separate memory element within the basic module which can be programmed separately, is preferably used to deselect a basic module.
  • the array according to the invention supplies adaptive systems.
  • the configured system can deliver output signals that modify the system itself in a certain way, ie reconfigure it automatically. This can be done, for example, by changing the programmable wiring or by changing the module properties. With a suitable design, the arrangements can be modified in real time.
  • the array according to the invention is preferably implemented in BICMOS technology.
  • This technology is particularly suitable because, on the one hand, it has the ability to perform high-quality analog functions through bipolar components and, on the other hand, it allows maximum integration through low-loss CMOS technology.
  • the concept of flexible interconnection requires good driver properties, the driver having to react flexibly to the load capacities. In principle, however, a solution in CMOS technology or in another technology suitable for large-scale integration is also conceivable.
  • the transfer of a prototype, which is configured on the array according to the invention, to an optimized circuit for larger quantities can be accomplished in a simple manner in that the data determined during the configuration together with the analog and digital library elements form the desired overall system in one suitable CAD environment, whereby unused elements are omitted and the additions for wiring and programmability, such as multiplexers and registers, are replaced by fixed wiring. Since the entire system was already completely replicated within the configurable module array according to the invention, the problem of a transition to other modules does not arise with the technology according to the invention.
  • the analog basic components of the array according to the invention include, for example, integrators, comparators, amplifiers, phase detectors and adjustable references.
  • the adjustable references can be realized by multiplying digital-to-analog converters.
  • first level 1 shows a first possible structuring within a first level of the array according to the invention, which, as will be further clarified below, is formed by a first-order matrix arrangement.
  • This is referred to as the first level, since only basic modules I1, I2, V1 are configured within this level.
  • the configuration shown here comprises two integrators I1, I2 or low-pass filters of the first order, which can be controlled both digitally for a coarse adjustment and analogously for a fine adjustment, and an amplifier V1 which can also be controlled.
  • Vdc With the reference symbol Vdc; Vac are digital or analog control inputs.
  • FIG. 2 shows a further first level of the array according to the invention, that is to say also a partial configuration of basic components, which is formed by a first-order matrix arrangement.
  • two voltage comparators K1, K2 are provided, which are followed by a phase detector PD.
  • Fig. 3 shows the block diagram of an FLL (Frequency Locked Loop), i.e. a frequency locked loop.
  • FLL Frequency Locked Loop
  • This circuit is formed from three blocks, each of which is formed on the first level of the digital array according to the invention, as is illustrated by FIGS. 1 and 2.
  • the circuit shown in Fig. 3 can be referred to as a second level circuit.
  • the hierarchical structure of the analog / digital design of the entire array according to the invention is clear.
  • Macros of the first level are formed on the basis of basic building blocks, which in turn can configure a system of the second level, whereby this can also be done in conjunction with basic building blocks from the lower levels.
  • the exemplary embodiment shown here is structured over two levels. It is obvious to a person skilled in the art that the concept of a hierarchical array according to the invention can be carried out over several levels.
  • FIG. 4 shows the circuit architecture of a programmable, controllable transconductance amplifier OTA using differential path technology.
  • This structure is intended to clarify the control options of a basic building block on behalf of the other basic building blocks.
  • the digital setting is a rough setting. This is done by data word W2.
  • the fine adjustment takes place starting from the data word W1 via a programmable, multiplying digital / analog converter MDAC, whereby such analog control voltages can also be provided externally.
  • a 10-bit latch L is used for digital programming both for the coarse adjustment and for the fine adjustment. These latches L are contained in the BBB rows of the basic building blocks, which are shown in FIG. 5 and are explained in more detail below with reference to FIG. 5.
  • the digital control brings about a rough digital setting by switching on or off pre-configured current and voltage references within the first-order matrix arrangements via data word W2.
  • the transconductance can also be kept programmable.
  • references for dynamic adjustment can be scaled.
  • the embodiment shown there comprises an inventive configurable analog and digital array arrangement, four matrix arrangements M 11 , M 12 , M 13 , M 14 first order and a matrix arrangement M 2 second order.
  • Each first-order matrix arrangement M 11 , M 12 , M 13 , M 14 comprises a plurality of basic building blocks BBB, which are shown there as BBB rows / lines 1 to 12.
  • the connections between the basic components within the matrix arrangements M 11 , M 12 , M 13 , M 14 are made by means of first switch matrices S 1 to S 4 , which in the example shown can be designed as (8 x 8) switch matrices.
  • decodable line selectors can be used on the periphery, which can separate and / or connect incoming and outgoing signal / supply paths. All external connections of the matrix can be programmed as inputs or outputs or bidirectional connections. Multiplexers in the selectors allow variable signal / supply routing.
  • intersection point MSU a conductive, bidirectional connection of a horizontal and a vertical line segment is created. Further intersection points MSU can be connected to these segments, so that line segments which run in parallel can also be realized. If the selectors at the matrix edges are deactivated, these line segments end at the matrix periphery.
  • the switching matrices are only shown without separation units. Unless otherwise shown, the signal paths in the structures shown each end at the matrix periphery.
  • the second-order matrix arrangement M 2 likewise comprises a switch matrix which, in the exemplary embodiment shown here, is designed as a (16 ⁇ 16) switch matrix.
  • the vertical signal lines of this matrix are the input and output lines of the switching matrices S 1 to S 4 of the first-order matrix arrangements.
  • Horizontal lines of the switch matrix of the second-order matrix arrangement are formed by outputs of a 256-bit shift register 17 and array input and array output lines. The latter form an interface 18 for the array.
  • the switch matrices S 1 to S 5 consist of 1-bit switches and memories, which are arranged in a field. By setting a “1” or “0”, signal and / or supply paths can be connected or separated.
  • FIG. 6 shows the implementation of the loop filter according to FIG. 1 by means of a first order matrix arrangement M 11 in the first level of the array.
  • Circuit elements denoted by the same reference numerals denote the same components in all the figures, so that their function and structure need not be explained again.
  • the configuration which is predetermined by the content of the shift register 13, selects certain basic modules from the BBB rows / lines 1, 2, 3 and interconnects them in the desired manner.
  • the function of the 64-bit shift register 13 for the analog configuration and that of the 16-bit shift register 19 for the rough digital control also become particularly clear here.
  • FIG. 7 shows a representation corresponding to FIG. 2 of a phase detector with two voltage comparators, as it is formed by the third matrix arrangement M 13 of the first order becomes.
  • the 64-bit shift register 15 is used for the analog configuration, while the 16-bit shift register 20 is used for the rough digital control.
  • FIG. 8 shows the entire wiring network which is formed by the array according to FIG. 5 in order to implement the frequency-locked control loop according to FIG. 3 in the second level of the array. Since the components have been explained with reference to the previous figures, no further explanation of the individual matrix arrangements is required.

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Abstract

L'invention concerne un réseau analogique et numérique réalisé en au moins deux plans dans une structure hiérarchisée. Ce réseau comprend au moins deux configurations matricielles du premier ordre dont chacune comporte une pluralité de modules de base disposés en rangs et/ou en colonnes, qui sont au moins en partie des modules de base analogiques, ainsi qu'une première matrice de commutation destinée à assurer la connexion mutuelle commandée des entrées et des sorties de signaux des modules de base et celle de ces derniers avec des entrées et des sorties matricielles. Ce réseau comprend également une configuration matricielle du second ordre qui comporte une seconde matrice de commutation destinée à assurer la connexion mutuelle commandée des entrées et des sorties matricielles des configurations matricielles du premier ordre et la connexion commandée de ces dernières avec les entrées et les sorties du réseau.

Claims (14)

  1. Réseau configurable, avec
    au moins deux dispositions en matrice (M11, M12, M13, M14) de premier ordre avec une pluralité de composants de base (BBB) disposés en rangée et/ ou colonne et, chacune, une première matrice de commutateurs (S1, S2 S3, S4), et
    au moins une disposition en matrice (M2) de second ordre avec une seconde matrice de commutateurs (S5) qui relie les au moins deux dispositions en matrice (M11, M12, M13, M14) de premier ordre,
    caractérisé par le fait que
    les composants de base (BBB) sont des composants de base numériques et au moins en partie analogiques,
    les dispositions en matrice (M11, M12, M13, M14) de premier ordre et la disposition en matrice (M2) de second ordre sont disposées sur un substrat commun,
    le réseau configurable présente un dispositif (13, 14, 15, 16) destiné à entrer des données de configuration et à configurer le réseau,
    la première matrice de commutateurs (S1, S2, S3, S4) concernée peut être commandée par le dispositif (13, 14, 15, 16) destiné à entrer des données de configuration, pour relier mutuellement les entrées de signal et/ou les sorties de signal des composants de base et pour relier les composants de base aux entrées de matrice et/ou aux sorties de matrice de la disposition en matrice de premier ordre,
    la seconde matrice de commutateurs (S5) est reliée directement aux entrées de réseau et aux sorties de réseau (17, 18) et peut être commandée par le dispositif (13, 14, 15, 16) destiné à entrer des données de configuration, pour relier mutuellement les entrées de matrice et/ou les sorties de matrice des dispositions en matrice (M11, M12, M13, M14) de premier ordre et pour relier les entrées de matrice et les sorties de matrice des dispositions en matrice (M11, M12, M13, M14) de premier ordre à des entrées de réseau et des sorties de réseau (17, 18).
  2. Réseau suivant la revendication 1, caractérisé par le fait que les composants de base (BBB) présentent, par ailleurs, une entrée de commande analogique et/ou numérique.
  3. Réseau suivant la revendication 2, caractérisé par le fait que chaque disposition en matrice (M11, M12, M13, M14) de premier ordre présente un registre de paramétrage (13, 14, 15, 16, 19, 20) qui contient tant des signaux de commande numériques pour les entrées de commande numérique des composants de base (BBB, 19, 20) que les bits de commande pour les commutateurs (13, 14, 15, 16).
  4. Réseau suivant la revendication 2 ou 3, caractérisé par le fait que chaque disposition en matrice (M11, M12, M13, M14) de premier ordre présente un convertisseur numérique/analogique multiplicateur (MDC) qui peut être soumis à l'admission d'un mot de données binaire (W1) d'un registre de paramétrage (19, 20) pour générer un signal de commande analogique (Vac) pour l'entrée de commande analogique du composant de base (BBB).
  5. Réseau suivant l'une des revendications 2 à 4, caractérisé par le fait que la configuration de composants de base (BBB) pour former un système global par la commande des entrées de commande analogique et numérique des composants de base (BBB) et par la commande des commutateurs (MSU) des premières et seconde dispositions en matrice (M11, M12, M13, M14; M2) s'effectue par les entrées de matrice et les entrées de réseaux.
  6. Disposition suivant la revendication 5, caractérisée par le fait qu'il est prévu un registre à tiroir (13, 14, 15, 16, 17) dans lequel peuvent être entrées en série des données pour la configuration et qui constitue le registre de paramétrage.
  7. Réseau suivant la revendication 5, caractérisé par le fait qu'il est prévu une interface parallèle qui permet l'entrée en parallèle des données de configuration dans le réseau.
  8. Réseau suivant l'une des revendications 1 à 7, caractérisé par le fait qu'à chacun d'au moins une partie des composants de base (BBB) est associé un registre de qualification qui se présente sous forme de mémoire d'écriture/ lecture ou de mémoire à valeur fixe qui contient au moins une information sur la défaillance totale du composant de base (BBB).
  9. Réseau suivant la revendication 8, caractérisé par le fait que le registre de qualification contient, par ailleurs, des informations sur les propriétés de fonctionnement du composant de base (BBB).
  10. Réseau suivant l'une des revendications 1 à 9, caractérisé par le fait qu'au moins les composants de base (BBB) qui ne sont statiquement pas sans perte peuvent être mis hors tension de fonctionnement par l'intermédiaire d'une entrée de coupure de courant.
  11. Réseau suivant l'une des revendications 1 à 10, caractérisé par le fait que le réseau est mis en ouvre selon la technologie BICMOS.
  12. Réseau suivant l'une des revendications 1 à 11, caractérisé par le fait que les composants de base (BBB) analogiques comprennent au moins l'un des composants suivants: intégrateurs, comparateurs, amplificateurs, détecteurs de phase et références réglables.
  13. Réseau suivant la revendication 12, caractérisé par le fait que les références réglables sont constituées par des convertisseurs numérique/analogique multiplicateurs (MDAC).
  14. Réseau suivant l'une des revendications 1 à 13, caractérisé par le fait que la première matrice de commutateurs (S1, S2 S3, S4) et la seconde matrice de commutateurs (S5) se composent d'une pluralité de commutateurs et de mémoires à 1 bit (MSU) disposés en matrice.
EP93915717A 1993-06-25 1993-06-25 Reseau analogique et numerique configurable Expired - Lifetime EP0705465B1 (fr)

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PCT/EP1993/001637 WO1995000921A1 (fr) 1993-06-25 1993-06-25 Reseau analogique et numerique configurable

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EP0705465B1 true EP0705465B1 (fr) 1996-10-30

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US5677691A (en) 1997-10-14
EP0705465A1 (fr) 1996-04-10
DE59304375D1 (de) 1996-12-05

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