EP0806719B1 - Circuit pour générer une tension de référence - Google Patents

Circuit pour générer une tension de référence Download PDF

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Publication number
EP0806719B1
EP0806719B1 EP97106833A EP97106833A EP0806719B1 EP 0806719 B1 EP0806719 B1 EP 0806719B1 EP 97106833 A EP97106833 A EP 97106833A EP 97106833 A EP97106833 A EP 97106833A EP 0806719 B1 EP0806719 B1 EP 0806719B1
Authority
EP
European Patent Office
Prior art keywords
transistor
collector
resistor
base
whose
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97106833A
Other languages
German (de)
English (en)
Other versions
EP0806719A3 (fr
EP0806719A2 (fr
Inventor
Stephan Dr. Weber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP0806719A2 publication Critical patent/EP0806719A2/fr
Publication of EP0806719A3 publication Critical patent/EP0806719A3/fr
Application granted granted Critical
Publication of EP0806719B1 publication Critical patent/EP0806719B1/fr
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/265—Current mirrors using bipolar transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to a circuit arrangement for generation a reference potential with a first transistor, the Emitter is connected to a reference potential and its Base and collector are interconnected with one another second transistor, the base of which is connected to the base of the first Transistor is connected to a first resistor, the between the collector of the first transistor and an output terminal switched to tap the reference potential is, with a second resistor that is between the collector of the second transistor and the output terminal is, with a third resistor connected between the emitter of the second transistor and the reference potential is, with a third transistor, the base of which is connected to the collector of the second transistor and its emitter with the reference potential connected and with a controlled power source, that between a supply potential and the output terminal is switched and the input side with the Collector of the third transistor is coupled.
  • bandgap reference Such a circuit arrangement, also referred to as a bandgap reference is described in EP-A-0 411 657.
  • a another bandgap reference is from Paul R. Gray, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Second Edition, John Wiley and Sons, 1984, pp. 293-296.
  • a bandgap reference is often used with integrated circuits used as internal reference voltage source.
  • a frequency-compensated bandgap reference is also in GB 2 256 949 A.
  • the object of the invention is to provide a circuit arrangement Specify the type mentioned, despite good noise behavior has short on and off times.
  • the controlled current source has a circuit arrangement fourth transistor whose collector has the supply potential, its emitter with the output terminal and its Base connected to the collector of the third transistor is. Is between the base and collector of the fourth transistor switched another power source.
  • the further current source can have a fifth transistor have its base with the output terminal and its emitter with the interposition of a fourth resistor is connected to the reference potential. Furthermore are a sixth transistor whose emitter is interposed a fifth resistor with the supply potential is connected, the collector of which is connected to the base of the fourth transistor is connected and its base with the Collector of the fifth transistor is coupled, as well as a seventh transistor, its base and collector together and coupled to the collector of the fifth transistor are and its emitter with the interposition of a sixth Resistance is connected to the supply potential, intended.
  • the noise of the circuit arrangement according to the invention is further reduced.
  • the noise of the others Current source has an influence especially at high frequencies on the noise behavior of the entire circuit arrangement. This is particularly annoying when the other Current source pnp transistors are used because of this the noise and the size of the parasitic capacitances are far from an ideal transistor.
  • the inserted eighth resistor insulates especially at high Frequencies the not ideal working other power source and thus improves the noise behavior and the output resistance.
  • the stability is improved because the effective capacity at the output of the further power source now not so much the phase reserve of the whole Circuit arrangement affects.
  • the insertion of a series resistor is particularly recommended when realizing sixth and seventh transistor as pnp transistors on one Current output of the circuit arrangement.
  • an npn transistor T1 is provided, whose emitter is connected to a reference potential M and whose base and collector are both interconnected as also via a common resistor R1 with a reference potential leading output terminal U are coupled.
  • the base and collector of transistor T1 is the base of one npn transistor T2 connected, the emitter via a Resistor R3 with the reference potential M and its collector coupled to the output terminal U via a resistor R2 is.
  • the emitter is also a npn transistor T4 connected, the collector with a supply potential V is connected.
  • the basis of the Transistor T4 is connected to the collector of an NPN transistor T3 connected, whose emitter to the reference potential M and Base is connected to the collector of transistor T2.
  • a capacitor C1 is connected in parallel with the resistor R2.
  • the base of the transistor T4 is also a Resistor R8 and a current source circuit to the supply potential V connected.
  • the current source circuit has a pnp transistor T6, its emitter via a resistor R5 with the supply potential V and its collector via resistor R8 the base of the transistor T4 or the collector of the transistor T3 is connected.
  • the base of transistor T6 is connected to the base and collector of a pnp transistor T7, whose emitter via a resistor R6 with the supply potential V is coupled.
  • Base and collector of the transistor T7 and the base of transistor T6 are above it also connected to the collector of an npn transistor T5, its emitter via a resistor R4 to the reference potential M is connected and its base with the output connection U is connected.
  • an output connection I which carries a reference current. Is to the output terminal I with the collector of a pnp transistor T8 connected, the emitter via a resistor R7 is connected to the supply potential V and its base is connected to the bases of transistors T6 and T7.
  • the dimensioning of the capacitor C1 depends on the respective application from, although here with higher capacities Noise behavior and, at lower capacities, the switch-on behavior becomes cheaper.
  • the resistor R8 becomes like this chosen as large as possible to ensure the highest possible insulation guarantee.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Control Of Electrical Variables (AREA)
  • Amplifiers (AREA)

Claims (2)

  1. Circuit de production d'un potentiel de référence
    comprenant un premier transistor (T1) dont l'émetteur est relié à un potentiel (M) de référence et dont la base et le collecteur sont reliés entre eux,
    comprenant un deuxième transistor (T2) dont la base est reliée à la base du premier transistor (T1),
    comprenant une première résistance (R1) qui est montée entre le collecteur du premier transistor (T1) et une borne (U) de sortie destinée à prélever le potentiel de référence,
    comprenant une deuxième résistance (R2) qui est montée entre le collecteur du deuxième transistor (T2) et la borne (U) de sortie,
    comprenant une troisième résistance (R3) qui est montée entre l'émetteur du deuxième transistor (T2) et le potentiel (M) de référence,
    comprenant un troisième transistor (T3) dont la base est reliée au collecteur du deuxième transistor (T2) et dont l'émetteur est relié au potentiel (M) de référence et comprenant une source (T4) de courant commandée qui est montée entre un potentiel (V) d'alimentation et la borne (U) de sortie et qui est couplée du côté de l'entrée au collecteur du troisième transistor (T3),
       caractérisé en ce que
    il est prévu une capacité (C1) qui est montée en parallèle à la deuxième résistance (R2),
    la source (T3, T4) de courant qui est commandée comporte un quatrième transistor (T4) dont le collecteur est relié au potentiel (V) d'alimentation, dont l'émetteur est relié à la borne (U) de sortie et dont la base est reliée au collecteur du troisième transistor (T3),
    il est monté entre la base et le collecteur du quatrième transistor (T4) une autre source (T5, T6, T7, R4, R5, R6) de courant et
    l'autre source (T5, T6, T7, R4, R5, R6) de courant comporte :
    un cinquième transistor (T5) dont la base est reliée à la bome (U) de sortie et dont l'émetteur est relié avec interposition d'une quatrième résistance (R4) au potentiel (M) de référence,
    un sixième transistor (T6) dont l'émetteur (T6) est relié avec interposition d'une cinquième résistance (R5) au potentiel (V) d'alimentation, dont le collecteur est relié à la base du quatrième transistor (T4) et dont la base est couplée au collecteur du cinquième transistor (T5),
    un septième transistor (T7) dont la base et lé collecteur sont couplés entre eux ainsi qu'au collecteur du cinquième transistor (T5) et dont l'émetteur est relié avec interposition d'une sixième résistance (R6) au potentiel (V) d'alimentation.
  2. Circuit selon la revendication 1,
       caractérisé en ce qu'une huitième résistance (R8) est montée en série de l'aufre source (T6, T7) de courant.
EP97106833A 1996-05-10 1997-04-24 Circuit pour générer une tension de référence Expired - Lifetime EP0806719B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19618914 1996-05-10
DE19618914A DE19618914C1 (de) 1996-05-10 1996-05-10 Schaltungsanordnung zur Erzeugung eines Referenzpotentials

Publications (3)

Publication Number Publication Date
EP0806719A2 EP0806719A2 (fr) 1997-11-12
EP0806719A3 EP0806719A3 (fr) 1998-09-16
EP0806719B1 true EP0806719B1 (fr) 2001-08-01

Family

ID=7793979

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97106833A Expired - Lifetime EP0806719B1 (fr) 1996-05-10 1997-04-24 Circuit pour générer une tension de référence

Country Status (3)

Country Link
US (1) US5883543A (fr)
EP (1) EP0806719B1 (fr)
DE (2) DE19618914C1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6811309B1 (en) 2000-07-26 2004-11-02 Stmicroelectronics Asia Pacific Pte Ltd Thermal sensor circuit
DE10357772A1 (de) * 2003-12-10 2005-07-14 Siemens Ag Steuereinheit und Steuervorrichtung mit der Steuereinheit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4553083A (en) * 1983-12-01 1985-11-12 Advanced Micro Devices, Inc. Bandgap reference voltage generator with VCC compensation
JPS60229125A (ja) * 1984-04-26 1985-11-14 Toshiba Corp 電圧出力回路
US5028527A (en) * 1988-02-22 1991-07-02 Applied Bio Technology Monoclonal antibodies against activated ras proteins with amino acid mutations at position 13 of the protein
JPH0680486B2 (ja) * 1989-08-03 1994-10-12 株式会社東芝 定電圧回路
US5029295A (en) * 1990-07-02 1991-07-02 Motorola, Inc. Bandgap voltage reference using a power supply independent current source
KR930001577A (ko) * 1991-06-19 1993-01-16 김광호 기준전압 발생회로
JP2953226B2 (ja) * 1992-12-11 1999-09-27 株式会社デンソー 基準電圧発生回路
US5757224A (en) * 1996-04-26 1998-05-26 Caterpillar Inc. Current mirror correction circuitry

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BIRRITTELLA M S ET AL: "DESIGN TECHNIQUES FOR IC VOLTAGE REGULATORS WITHOUT P-N-P TRANSISTORS" IEEE JOURNAL OF SOLID-STATE CIRCUITS, NEW YORK, NY, US, Bd. 22, Nr. 1, Februar 1987. *

Also Published As

Publication number Publication date
US5883543A (en) 1999-03-16
EP0806719A3 (fr) 1998-09-16
DE59704169D1 (de) 2001-09-06
EP0806719A2 (fr) 1997-11-12
DE19618914C1 (de) 1997-08-14

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