EP0809229A2 - Dispositif de commande de balayage d'une matrice intégrée monolithique de diodes électroluminescentes - Google Patents

Dispositif de commande de balayage d'une matrice intégrée monolithique de diodes électroluminescentes Download PDF

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Publication number
EP0809229A2
EP0809229A2 EP97107141A EP97107141A EP0809229A2 EP 0809229 A2 EP0809229 A2 EP 0809229A2 EP 97107141 A EP97107141 A EP 97107141A EP 97107141 A EP97107141 A EP 97107141A EP 0809229 A2 EP0809229 A2 EP 0809229A2
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EP
European Patent Office
Prior art keywords
column
light emitting
row
coupled
transistor
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Application number
EP97107141A
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German (de)
English (en)
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EP0809229A3 (fr
Inventor
Rong-Ting Huang
Phil Wright
Farid Akhbari
Jerald A. Hallmark
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Motorola Solutions Inc
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Motorola Inc
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Publication of EP0809229A3 publication Critical patent/EP0809229A3/fr
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3216—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates, in general, to display devices, and more particularly, to a novel drive device for operating a display.
  • this invention relates to Light Emitting Device (LED) arrays, and more specifically to a monolithic drive device integrated with an LED array.
  • LED Light Emitting Device
  • Matrix addressing techniques are well known in the art and have been utilized to control various types of displays such as light emitting diode displays, liquid crystal device (LCD) displays, and field emission device (FED) displays.
  • Matrix addressing schemes typically organize the light emitting elements or pixels into a number of rows and columns with each pixel at an intersection of a particular row and a particular column. Illuminating the pixel requires activating an intersecting row and column thereby providing a closed current path that includes the pixel to be illuminated.
  • Circuitry for driving an LED matrix display having rows and columns with a plurality of pixels includes a memory with a certain number of bits width, where the number of bits is equal to the number of pixels, a column output for supplying the number of bits in parallel to a matrix display connected to the column output, and row selection and driver circuitry connected to the memory and to the column output for selecting a complete row of bits of data stored in the memory and supplying the complete row of bits to the column output.
  • Memory for the driver circuitry is for example any of the electronic memories available on the market including but not limited to ROMs, PROMs, EPROMs, EEPROMs, RAMs, etc.,.
  • Image information is generally supplied to the LED driver circuitry memory by way of a data input and is stored in a predetermined location by means of an address supplied to the address input.
  • the stored data is supplied to the LED display a complete row at a time by way of a latch/column driver.
  • Each bit of data for each column in the row is accessed in memory and transferred to a latch circuit.
  • the current data is then supplied to the column drivers to drive each pixel in the row simultaneously.
  • a shift register is sequentially selecting a new row of data each time a pulse is received from a clock.
  • the newly selected row of pixels is actuated by row drivers so that data supplied to the same pixels by a latch/column driver causes the pixel to emit the required amount of light.
  • the shift register takes advantage of the fact that random access to the rows and columns is not generally required in matrix displays, they need only be addressed sequentially.
  • the advantage to the shift register approach is that it only requires a clock pulse to initiate a new row sequence.
  • an LED matrix display could be a simple monochrome configuration, a display utilizing monochrome grayscale, or color.
  • a simple monochrome display only a one bit digital signal is needed for each pixel, as the pixel is either on or off.
  • a display utilizing monochrome grayscale either an analog signal or a multi-bit digital signal is required.
  • a sixteen level grayscale for example, needs a four bit digital signal.
  • Full color generally requires at least three light emitting elements per pixel, one for each of the basic colors (red, green and blue), and a type of grayscale signal system to achieve the appropriate amount of each color.
  • each pixel contains a single light emitting device which must be driven in a range of values to achieve a range of gray (gray scale) between full on (white) and full off (black).
  • gray gray scale
  • the data drivers In order to get good gray scale, the data drivers generally have to be able to deliver an accurate analog voltage to each pixel.
  • analog driver circuits are very expensive and, since there must be hundreds of data drivers (one for each row of light emitting devices), are the major part of the display cost.
  • each pixel contains at least three light emitting devices, each of which produces a different color (e.g. red, green, and blue) and each of which must be driven (generally a row at a time) in a range of values to achieve a range of that specific color between full on and full off.
  • full color displays contain three times as many analog drivers, which at least triples the manufacturing cost of the display.
  • the additional analog drivers require additional space and power, which can be a problem in portable electronic devices, such as pagers, cellular and regular telephones, radios, data banks, etc.
  • the columns and rows of the LED matrix require drivers for each individual column or row with additional latching circuits for the column drivers.
  • This configuration is heavily dependent on a large number of I/O terminal counts and the circuit becomes burdensome and not conducive to miniaturization.
  • Displays utilizing two dimensional arrays, or matrices, of pixels each containing one or more light emitting devices are very popular in the electronic field and especially in portable electronic and communication devices, because large amounts of data and pictures can be transmitted very rapidly and to virtually any location.
  • One problem with these matrices is that each row (or column) of light emitting devices in the matrix must be separately addressed and driven with a video or data driver.
  • a drive device and matrix of light emitting devices including a plurality of light emitting devices with each light emitting device having a first contact and a second contact, the first contacts being organized into a plurality of rows of first contacts and the second contacts being organized into a plurality of columns of second contacts.
  • a plurality of row circuits is provided, coupling each row of first contacts to one of a current sink or a power source.
  • a plurality of column decoding switches is provided, each coupled to a plurality of individual columns of first contacts and to another of the current sink or the power source.
  • a plurality of column data lines are coupled, one each column data line coupled to one each of the column decoding switches, for selecting and activating a selected column decoding switch when an activating signal is supplied to a column data line associated with the selected column decoding switch.
  • a plurality of column address lines are coupled, each to each of the plurality of column decoding switches, for selecting an addressed one of the plurality of individual columns of first contacts coupled to the selected column decoding switch and coupling the addressed one of the plurality of individual columns to the another of the current sink or the power source. Whereby one contact of a selected light emitting device of the matrix is coupled to the current sink by a row circuit and another contact of the selected light emitting device is coupled to the power source by the addressed one of the plurality of individual columns.
  • Similar decoding switches may be used in either or both of the column and row circuits. All of the decoding switches used for either column or row scanning have common address lines. As a result, when the decoding switches are integrated onto the same chip as the LED matrix, the apparatus and the proposed scanning method provides a great reduction in the column and row related I/O terminal count.
  • FIG. 1 illustrates a light emitting device (LED) array integrated circuit 10.
  • Integrated circuit 10 includes an array 11 of 240 by 144 light emitting devices or elements designated pixels, each pixel with a unique column and row electrical connection. It will of course be understood that integrated circuit 10 is being utilized for purposes of this explanation and could in fact include any of a large variety of arrays and specifically, different numbers of columns and rows and/or different types of devices.
  • a plurality of column decoder switches 12 are attached to 60 column data lines, C0 through C59.
  • Lines C0 through C59 are designated as data lines, with data signals interchangeably designated C0 through C59, and two pairs of complimentary input signals, A 0 , A 0 ⁇ , A 1 and A 1 ⁇ , are applied as address signals to the four address lines, interchangeably designated A 0 , A 0 ⁇ , A 1 and A 1 ⁇ .
  • Each column decoder switch 12 is illustrated as having address signals A 0 , A 0 ⁇ , A 1 , and A 1 ⁇ , and one of C0 through C59 applied thereto.
  • the proposed column decoding switch 12 provides a great reduction in the column related I/O count.
  • the improvements provided by the reduced number of elements for driving the column circuits 13 includes, specifically, a reduction in the number of I/O terminals and in the array power dissipation.
  • the means of addressing columns 13 of array 11 is generally as follows:
  • FIG. 1 Also illustrated in FIG. 1 is a plurality of row decoder switches 15, each with an individual data line of a plurality of input data lines R 0 through R 35 coupled thereto (for a total of 36 row decoder switches 15 in this embodiment).
  • Four individual (i.e. separate and distinct) rows 14 of array 11 are coupled to each row decoder switch 15.
  • Each row decoder switch 15 is activated by the individual signal on data lines R 0 through R 35 coupled thereto and by signals on row address lines B 0 , B 0 ⁇ , B 1 , and B 1 ⁇ .
  • the means of addressing rows 14 of array 11 is generally as follows:
  • a fixed power supply (see FIG 7) is include in a silicon driver integrated circuit and connected as a power source to column decoding circuits 12. Also, a constant current sink circuit (see FIG. 7) is included in the silicon driver integrated circuit and connected as a power return circuit from row drivers 15. All of column decoding switches 12 have common address lines. As a result, the columns can be scanned sequentially, with no greater than n/4 (where n is the total number of columns) column decoders 12 at once depending on the input signal from the column input select lines, C n . All of row decoding switches 15 have common address lines.
  • the rows can be scanned sequentially, with no greater than m/4 (where m is the total number of rows) row decoders 14 at once depending on the row input signal, R n .
  • Power dissipation is limited by the MESFET leakage current. As a result, the power dissipation is much lower than that obtained from LED array 11 with a conventional decoding switch.
  • the instant invention thereby reduces the number of I/O terminals required to address LED each pixel of array 11 and greatly reduces the power consumption of LED integrated circuit 10.
  • Decoder switch 12 n includes a plurality of column decoder circuits 16, 17, 18, and 19 connected to output a signal to one of column 0 through column 3 of LED array 11 in response to appropriate address signals.
  • a truth table 30 illustrated in FIG. 3 which will be referenced as the illustration of FIG. 2 is described.
  • Truth table 30 illustrates the signal levels of each address line, A 0 , A 0 ⁇ , A 1 , A 1 ⁇ , which are designated as a '1' or a '0', with column decoder switch 12 n selected by a high data signal C n .
  • a 0 and A 0 ⁇ are complementary signals and A 1 and A 1 ⁇ are complementary signals so that when one of the pair is a logic high the other is a logic low level.
  • a first row 31 illustrates the logic signals required for the selection of column circuit 16, note that the data line C n is at a logic high level, A 0 and A 1 are at a logic low level and A 0 ⁇ and A 1 ⁇ are at a logic high level.
  • truth table 30 which illustrates the logic signals required for the selection of column circuit 17, the data line C n is still at a logic high level, with A 0 and A 1 ⁇ being a logic low level and A 0 ⁇ and A 1 being a logic high level.
  • truth table 30 which illustrates the logic signals required for the selection of column circuit 18, the data line C n is still at a logic high level, with A 0 and A 1 ⁇ being a logic high level and A 0 ⁇ and A 1 being a logic low level.
  • any column decoder switch 12 n is selected by applying a logic high level signal to the associated data line C n and any of the columns attached to the selected decoder switch 12 n are selected by activating an appropriate combination of address line A 0 , A 0 ⁇ , A 1 , and A 1 ⁇ .
  • FIG. 4 illustrates a selection logic truth table 40 for row decoder switches 15 n , which is similar to the column selection of truth table 30.
  • a specific row decoder switch 15 n (representative of all row decoder switches 15) is selected by supplying a logic high level signal to the associated data line R n .
  • selection of one of four rows is accomplished by means of address lines B 0 , B 0 ⁇ , B 1 , and B 1 ⁇ .
  • Data line R n is, when activated, designated a 1 in the circuit logic.
  • FIG. 5 a schematic diagram of a preferred embodiment of a single column decoder circuit 20 (four of which are included in each column decoder switch 12, as will be explained presently) is illustrated.
  • Column decoder circuit 20 includes three field effect transistors (FETs) 21, 22, and 23 connected in series between a terminal 24, adapted to have a source of power connected thereto (5 volts in the embodiment), and a specific column 13 n (illustrated as terminal 13 n ).
  • terminal 24 is connected to similar terminals of the other four column decoder circuits in the column decoder switch and to a fixed power supply.
  • Address line A 0 is illustrated as an electrical terminal coupled to the gate of FET 21.
  • FET 21 will couple the potential from terminal 24 to second FET 22 when a high signal is delivered on address line A 0 .
  • FET 21 will not conduct when the address line A 0 has a low signal applied thereto.
  • Address line A 1 supplies an activating signal to the gate of FET 22 which signal path contains two level shifting diodes 25 and 26.
  • Level shifting diodes 25 and 26 provide a voltage shift to the gate of FET 22 to prevent forward biasing the gate-drain diode of FET 22.
  • FET 22 will conduct when address signal A 1 is at a high level and will couple the potential from FET 21 to FET 23. However, if FET 21 is not conducting then there is nothing to couple to FET 23. A low level logic signal from address line A 1 will prevent FET 23 from conducting.
  • Four level shifting diodes, 27, 28, 29, and 30 are connected in series with the gate terminal of FET 23 and provide a circuit path for data line C n , which will either turn on FET 23 and couple a potential from FET 22 on a high signal or will prevent any activation signal from reaching column 13 n , if the signal on data line C n is a low signal.
  • the four level shifting diodes, 27, 28, 29, and 30 provide increased level shiftin of data line C n from the increased number of diodes.
  • a row decoding switch 33 is illustrated including three series connected FETs 34, 35, and 36 having address lines B 0 and B 1 , and row data signal R n , respectively, attached to the gates thereof.
  • the free terminal of FET 34 is connected to an associated row 14 n , illustrated as a terminal 14 in FIG. 6.
  • FET 34 couples row 14 to FET 35 upon an activation signal (logic high) being applied to address line B 0 .
  • the signal on data line B 1 must be at a logic high level to activate FET 35 to further complete an electrical circuit to FET 36.
  • Data line R n must now be at a logic high level to complete the electrical circuit from row 14 n to a current sink, illustrated as a terminal 38.
  • terminal 38 is connected to similar terminals of the other four row decoder circuits in the row decoder switch and to a constant current sink. Electrical conductivity from row 14 n to terminal 38 completes an electrical circuit which activates any light emitting device or devices coupled between the intersection of column 13 n and row 14 n to emit light.
  • FIG. 7 illustrates a plurality of LED's in array 11 comprised of column 0 through column 2 n -1 and row 0 through row 2 m -1.
  • LED 0 is electrically connected to column decoder switch 12 0 and row decoder switch 15 0 , as a singular illustration of a plurality of column decoder switches 12 and a plurality of row decoder switches 15 connected to a plurality of columns and rows of LEDs in array 11 for addressing and activating a specific LED.
  • FIG. 7 illustrates schematically a column decoder switch 12 (described in FIGS.
  • LED array 83 Illustrated in FIG. 8 is an epi-structure 80 with monolithic integration of a low power decoding switch 82 (illustrated as a single FET) and an LED array 83 (illustrated as a single LED) onto the same substrate.
  • LED array 83 includes a plurality of doped and undoped epitaxial layers formed sequentially on a simi-insulating gallium arsenide substrate 84.
  • the epitaxial layers are an n+-GaAs layer 85, a n-InGap layer 86, an n-AlInP layer 87, an undoped AIGaInP layer 88, an undoped AlInP layer 89, a p-AlInP layer 90, a p-InGaP layer 91 approximately 200 ⁇ thick , and an undoped GaAs layer 92 approximately 500 ⁇ thick to form LED array 83 integrated with corresponding switch 82.
  • implants 94 provided for pixel isolation, implant 95 provided electrical connection to the lower terminal of each pixel, and implant 96 provided for row isolation. Metalized connections to each LED in array 83 are provided by contacts 97 and 98.
  • Switch 82 includes device isolation implants 100, source and drain connection implants 102 and 104, and metalized contacts 112, 113, and 114 for source, gate and drain terminals, respectively. Additional information on this type of array can be found in U.S. Patent No. 5,453,386, entitled “Method of Fabrication of Implanted LED Array", issued September 26, 1995, and assigned to the same assignee. Also, for integration techniques, see U.S. Patent No. 5,483,085, entitled “Electro-Optic Integrated Circuit With Diode Decoder” issued January 9, 1996 and assigned to the same assignee.
  • a modified epi-structure 120 is illustrated in FIG. 9 which includes a decoding switch 122 integrated with an LED array 130 as a monolithic integration onto the same substrate.
  • LED array 130 is similar to LED array 83 of FIG. 8.
  • Decoding switch 122 is similar to switch 82 of FIG. 8 except that is fabricated by adding additional epitaxial layers after LED array 130 is fabricated so that p-dopant outdiffusion from LED 130 to FET 122 during the device fabrication is less of a problem.
  • an LED display can be provided with only one of the assembly of column or row decoding switches and the other of the assembly of row or column (these are of course interchangeable) decoding switches can be replaced with normal hardwired connections, some form of decoding, a shift register, or the like.
  • All the column decoding switches have common address lines. As a result, the column can be scanned sequentially or as n/4 where n is the number of columns at once depending on the input power supply from a driver. All the row decoding switches have common address lines. As a result rows can be scanned sequentially or as m/4 where m is the number of rows at once depending on the status of input row control signal,R n . Level shifting diodes used to prevent a MESFET gate from being driven into forward bias are integrated with MESFETs. As a result the output voltage of the decoding switch is compatible with the output voltage of commercial TTL circuits.
  • the instant invention reduces the number of I/O terminals to activate LED pixels and greatly reduces the power consumption of the LED integrated circuit.
  • the added reduction of I/O terminals, from 384 to 140 is a great improvement over the array without the integration of decoding switches.
  • the integrated circuit can be formed in any convenient semiconductor material system or in any convenient organic system.
  • the LED array and switches can be formed in a variety of ways while still performing the stated functions.
  • a variety of different light emitting devices may be utilized and fabricated in a variety of somewhat modified and/or interchanged steps.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Control Of El Displays (AREA)
EP97107141A 1996-05-23 1997-04-30 Dispositif de commande de balayage d'une matrice intégrée monolithique de diodes électroluminescentes Withdrawn EP0809229A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65239996A 1996-05-23 1996-05-23
US652399 1996-05-23

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EP0809229A2 true EP0809229A2 (fr) 1997-11-26
EP0809229A3 EP0809229A3 (fr) 1997-12-03

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EP2234162A3 (fr) * 1998-08-07 2011-03-09 LG Electronics Inc. Panneau d'affichage électroluminescent en matière organique et procédé pour sa fabrication
US9653441B1 (en) 2016-06-20 2017-05-16 International Business Machines Corporation Monolithic integration of a III-V optoelectronic device, a filter and a driving circuit

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2234162A3 (fr) * 1998-08-07 2011-03-09 LG Electronics Inc. Panneau d'affichage électroluminescent en matière organique et procédé pour sa fabrication
EP1176579B1 (fr) * 2000-07-26 2005-06-01 Lg Electronics Inc. Commande de courant pour un dispositif d'affichage
US9653441B1 (en) 2016-06-20 2017-05-16 International Business Machines Corporation Monolithic integration of a III-V optoelectronic device, a filter and a driving circuit

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CN1180881A (zh) 1998-05-06
JPH1063226A (ja) 1998-03-06
EP0809229A3 (fr) 1997-12-03

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