EP0849672A3 - Nichtintrusive Kodehaltepunkte in einem Prozessorbefehlsausführungspipeline - Google Patents

Nichtintrusive Kodehaltepunkte in einem Prozessorbefehlsausführungspipeline Download PDF

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Publication number
EP0849672A3
EP0849672A3 EP97310418A EP97310418A EP0849672A3 EP 0849672 A3 EP0849672 A3 EP 0849672A3 EP 97310418 A EP97310418 A EP 97310418A EP 97310418 A EP97310418 A EP 97310418A EP 0849672 A3 EP0849672 A3 EP 0849672A3
Authority
EP
European Patent Office
Prior art keywords
microprocessor
emulation
pipeline
execution pipeline
unprotected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP97310418A
Other languages
English (en)
French (fr)
Other versions
EP0849672B1 (de
EP0849672A2 (de
Inventor
Douglas E. Dean
Natarajan Seshan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP0849672A2 publication Critical patent/EP0849672A2/de
Publication of EP0849672A3 publication Critical patent/EP0849672A3/de
Application granted granted Critical
Publication of EP0849672B1 publication Critical patent/EP0849672B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3648—Debugging of software using additional hardware
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
EP97310418A 1996-12-20 1997-12-22 Nichtintrusive Kodehaltepunkte in einem Prozessorbefehlsausführungspipeline Expired - Lifetime EP0849672B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3476896P 1996-12-20 1996-12-20
US34768P 1996-12-20

Publications (3)

Publication Number Publication Date
EP0849672A2 EP0849672A2 (de) 1998-06-24
EP0849672A3 true EP0849672A3 (de) 2000-03-15
EP0849672B1 EP0849672B1 (de) 2004-04-07

Family

ID=21878478

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97310418A Expired - Lifetime EP0849672B1 (de) 1996-12-20 1997-12-22 Nichtintrusive Kodehaltepunkte in einem Prozessorbefehlsausführungspipeline

Country Status (3)

Country Link
EP (1) EP0849672B1 (de)
JP (1) JP3746367B2 (de)
DE (1) DE69728507T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6385742B1 (en) 1998-03-06 2002-05-07 Lsi Logic Corporation Microprocessor debugging mechanism employing scan interface
GB2337834B (en) * 1998-03-06 2003-02-12 Lsi Logic Corp Microprocessor debugging
EP0992906B1 (de) * 1998-10-06 2005-08-03 Texas Instruments Inc. Vorrichtung und Verfahren für einen Software-Haltepunkt während eines Verzögerungsschlitzes
US8612201B2 (en) * 2006-04-11 2013-12-17 Cadence Design Systems, Inc. Hardware emulation system having a heterogeneous cluster of processors
CN104778116B (zh) * 2014-01-09 2018-09-18 深圳市中兴微电子技术有限公司 一种多断点的软件调试装置和方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313848A2 (de) * 1987-10-30 1989-05-03 Motorola Inc. Datenprozessor mit Entwicklungsunterstützungsmerkmalen
WO1996038787A2 (en) * 1995-05-26 1996-12-05 Nat Semiconductor Corp Code breakpoint decoder

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0313848A2 (de) * 1987-10-30 1989-05-03 Motorola Inc. Datenprozessor mit Entwicklungsunterstützungsmerkmalen
WO1996038787A2 (en) * 1995-05-26 1996-12-05 Nat Semiconductor Corp Code breakpoint decoder

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BRANSTETTER R ET AL: "ULTRA-RELIABLE DIGITAL AVIONICS (URDA) PROCESSOR ARCHITECTURE", PROCEEDINGS OF THE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE. (NAECON),US,NEW YORK, IEEE, pages 274-280, XP000510775, ISBN: 0-7803-1894-3 *

Also Published As

Publication number Publication date
EP0849672B1 (de) 2004-04-07
JP3746367B2 (ja) 2006-02-15
JPH10326189A (ja) 1998-12-08
DE69728507T2 (de) 2005-03-24
EP0849672A2 (de) 1998-06-24
DE69728507D1 (de) 2004-05-13

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