EP0889509B1 - Contrôle de la durée de vie pour des dispositifs semi-conducteurs - Google Patents

Contrôle de la durée de vie pour des dispositifs semi-conducteurs Download PDF

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Publication number
EP0889509B1
EP0889509B1 EP98111147A EP98111147A EP0889509B1 EP 0889509 B1 EP0889509 B1 EP 0889509B1 EP 98111147 A EP98111147 A EP 98111147A EP 98111147 A EP98111147 A EP 98111147A EP 0889509 B1 EP0889509 B1 EP 0889509B1
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European Patent Office
Prior art keywords
bonding
wafer
wafers
layer
buffer layer
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Expired - Lifetime
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EP98111147A
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German (de)
English (en)
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EP0889509A3 (fr
EP0889509A2 (fr
Inventor
John Manning Savidge Neilson
John Lawrence Benjamin
Maxime Zafrani
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/01—Manufacture or treatment
    • H10D8/045—Manufacture or treatment of PN junction diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0102—Manufacture or treatment of thyristors having built-in components, e.g. thyristor having built-in diode
    • H10D84/0105—Manufacture or treatment of thyristors having built-in components, e.g. thyristor having built-in diode the built-in components being field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding

Definitions

  • the present invention is directed to minority carrier lifetime control in semiconductor devices, and more particularly to method and device in which a layer adjacent a blocking layer of a semiconductor device is provided with a significantly higher density of recombination centers.
  • the switching speed of semiconductor devices (such as during reverse recovery or turn-off) and the gain of parasitic bipolar transistors in field effect transistors are reduced by reducing the minority carrier lifetime.
  • the minority carrier lifetime is the time to recombination of an electron in a P type semiconductor material or of a hole in an N type semiconductor material.
  • Carrier lifetime is reduced by performing a lifetime control procedure to reduce minority carrier lifetime so that the carriers, the holes and electrons, remaining after conduction will recombine more rapidly.
  • the present invention is directed to an improved lifetime control procedure and to devices fabricated with the procedure.
  • Carrier lifetime control procedures provide locations, known as recombination centers, in the semiconductor device where recombination of the carriers is facilitated.
  • the recombination centers whose density may be on the order of 0.1 to 1.5 ppma (parts per million atomic), are locations of crystallographic strain which may be caused by the generation of dislocations in the crystal structure of the silicon, such as by introduction of impurities.
  • Various methods for generating recombination centers are known.
  • silicon may be doped with a heavy metal dopant, such as gold or platinum.
  • the heavy metal dopant (the impurity) generates recombination centers because the heavy metals have energy levels within the forbidden energy band of silicon.
  • a further method of generating recombination centers is to generate dislocations throughout the silicon by bombarding it with radiation, such as high energy electrons, neutrons or protons.
  • the dangling bonds in these dislocations have mid-band energy levels which serve as recombination centers for the carriers.
  • the specification of U.S. Patent No. 4,684,413 discloses the method steps.
  • a semiconductor device may include a substrate 12 with a layer 14 which is more lightly doped and performs various functions depending on the type of device in which it is found.
  • Layer 14 is denoted herein as a blocking layer, although its functions may vary.
  • Blocking layer 14 is atop a relatively more heavily doped layer 16, denoted herein as a buffer layer, which has been found to be the preferred location for a high density of recombination centers.
  • This preferred location for a high density of recombination centers in a thin layer adjacent blocking layer 14 produces low current leakage, low on-voltage for a given switching speed, and a robust avalanche breakdown. Leakage is lower because recombination centers also are generation centers and generate leakage currents if they are located in blocking layer 14 where they are subjected to the high electric fields which appear in blocking layer 14 when the device is supporting a high voltage. On-voltage is lower for a given speed because carriers in blocking layer 14 are rapidly removed by the electric field which builds as voltage on the device increases, but carriers outside blocking layer 14 are inaccessible to the electric field and must be removed by the slower process of recombination.
  • recombination centers in blocking layer 14 cause a higher on-voltage but are not as effective in improving switching speed as those outside blocking layer 14.
  • Recombination centers in blocking layer 14 may also cause "fragile" breakdown characteristics because they trap some of the majority carriers and so increase the resistivity of the material forming blocking layer 14.
  • the resistivity of blocking layer 14 is too high, the high field region in avalanche breakdown may become unstable and cause a localized overheating and burnout (denoted a "fragile" breakdown).
  • Reducing the number of recombination centers in blocking layer 14 reduces the likelihood of increasing the resistivity of blocking layer 14 and makes avalanche breakdown more robust, i . e ., less "fragile"
  • wafer bonding may be used to fabricate silicon devices.
  • the bonding surfaces of two silicon wafers are polished sufficiently flat so that when the polished surfaces are brought into contact with each other, enough of the neighboring silicon atoms can form covalent bonds across the wafer-to-wafer bonding interface to link the two wafers into a single crystal.
  • the present invention takes advantage of this wafer bonding process to facilitate the formation of the preferred buffer layer which has a significantly higher density of recombination centers than the adjacent blocking layer.
  • WO 92/09099 discloses a method for controlling minority carrier lifetime in a bonded wafer semiconductor device.
  • the device is obtained by bonding two wafers, each wafer having a free and a bonding surface, each wafer having a highly doped surface region on its free surface, and one wafer having a lightly doped blocking layer beneath the highly doped surface region.
  • the minority carrier lifetime is controlled by orientating the two bonding surfaces of the wafers at an angle to the crystal lattice structures and then bonding the two wafers.
  • the present invention is defined according to claim 1.
  • An object of the present invention is to provide a novel method and device in which recombination centers of a semiconductor device are concentrated in a buffer layer at or near a wafer-to-wafer bonding interface, in which the density of recombination centers in a buffer layer adjacent a blocking layer in a semiconductor device is significantly higher than that of the blocking layer.
  • Another object is to provide a method and device in which a semiconductor device formed by bonding two wafers has a blocking layer and an adjacent buffer layer containing the wafer-to-wafer bonding interface in which the recombination centers are concentrated in the buffer layer and are substantially absent from the blocking layer, and to provide a method of controlling minority carrier lifetime in a semiconductor device by selectively misaligning features of the bonding surfaces of two wafers to control a density of recombination centers in a layer at or adjacent a wafer-to-wafer bonding interface between the two wafers, the two wafers being bonded so that the features of the bonding surfaces of the two wafers are misaligned to generate dislocations which form the recombination centers in the layer.
  • the present invention includes a method of controlling minority carrier lifetime in a semiconductor device, comprising the step of: controlling a density of recombination centers at a wafer-to-wafer bonding interface adjacent a blocking layer of the semiconductor device so that the recombination centers are concentrated in a buffer layer adjacent the blocking layer, including bonding two wafers at the wafer-to-wafer bonding interface so that features of bonding surfaces of the two wafers at the bonding interface are not aligned, so as to when bonded, the misaligned features of the two wafers generate dislocations at the bonding interface which form the recombination centers.
  • the invention also includes a method of controlling minority carrier lifetime in a semiconductor device, comprising the steps of
  • Figures 1a-d show vertical cross-sections of various semiconductor devices of the prior art illustrating the distribution of recombination centers throughout the silicon substrate.
  • Figures 2a-d show vertical cross-sections of various semiconductor devices illustrating the layer of recombination centers in embodiments of the present invention.
  • Figure 3 is a pictorial depiction of two wafers to be bonded illustrating misalignment of crystalline features of the two wafers in an embodiment of the present invention.
  • a method of controlling minority carrier lifetime in a semiconductor device may include the step of controlling a density of recombination centers (x) at a wafer-to-wafer bonding interface 20 adjacent a blocking layer 22 of the semiconductor device so that the recombination centers are concentrated in a buffer layer 24 at or near bonding interface 20 and adjacent blocking layer 22.
  • the density of recombination centers (x) in the buffer layer 24 is in a range of from 10 14 /cm 3 to 10 19 /cm 3 .
  • the buffer layer 24 be from 1 micron to 50 microns in thickness.
  • the recombination centers (x) are substantially absent from the blocking layer 22 and, typically may be in a concentration of less than the concentration of the buffer layer in the blocking layer 22.
  • the figures show bonding interface 20 inside buffer layer 24, although bonding interface 20 may be at an edge or even slightly spaced from buffer layer 24.
  • the bonding surface of at least one of two wafers which are to be bonded to form substrate 12 is processed before bonding so that dislocations will form at the wafer-to-wafer bonding interface when the wafers are bonded.
  • the dislocations become recombination centers for the minority carriers.
  • the bonding surface may be processed before bonding by either or both of the two methods discussed below.
  • dislocation refers to any strain location regardless of the cause of the strain ( e . g ., dopant or crystalline misalignment).
  • Figure 3 illustrates one way to process the bonding surfaces is to purposely misalign corresponding features at the bonding surfaces 30 so that when the two wafers 32 are bonded the features are misaligned thereby creating dislocations at the wafer-to-wafer bonding interface.
  • one of the wafers may be rotated relative to the other so that crystalline axes of the two wafers are not aligned.
  • these axes are highly exaggerated by the misaligned lines 34 on the facing bonding surfaces 30.
  • one of the bonding surfaces 30 is polished off-axis relative to the other bonding surface. Lines 34 in Figure 3 are also illustrative of the polishing striations resulting from off-axis polishing.
  • the features of the either of these methods (that is, the crystal axes and the polishing striations) generate dislocations when wafers 32 are bonded.
  • the dislocations are at the wafer-to-wafer bonding interface on both bonding surfaces 30 so that buffer layer 24 is formed with the bonding interface therein.
  • the amount by which wafers 32 are misaligned determines the dislocation density in buffer layer 24.
  • the misalignment between wafers 32 illustrated in Figure 3 is in a range of from one to 45 degrees of the lines 34 of one wafer 32 relative to the other.
  • the greater the misalignment the higher the density of recombination centers.
  • the density and distribution of these recombination centers may be modified by appropriate heat treatments, such as a furnace operation or rapid thermal annealing, after bonding.
  • Another method of controlling the density of recombination centers is to dope one or both of the bonding surfaces with a suitable dopant or dopants.
  • a suitable dopant or dopants are, for example, Au, PT, PD, AG, Cu, Fe, Ni, Co.
  • dopants may be evaporated onto or implanted into one or both of the bonding surfaces after polishing and before bonding the two wafers.
  • the lower bonding surface (the one on the wafer which does not have blocking layer 22 therein) may be doped with a suitable metal dopant prior to polishing and bonding, and using conventional high temperature treatments to distribute the dopants in what will become buffer layer 24 and establish the desired concentration.
  • the dopant concentration in the buffer layer 24 is in a range from 10 14 /cm 3 to 10 19 /cm 3 , depending on the speed required.
  • These doping methods is used with the wafers purposely misaligned by a controlled amount to provide a combination of sources of recombination centers.
  • the dopant may be selected to provide optimum switching performance (if this is desired) without regard for its solubility or diffusion coefficient.
  • the dopant was typically a heavy metal evaporated on to one surface of the wafer which was then heated to 800° to 900°C at which the solid solubility of the metal produced an appropriate concentration of recombination centers.
  • the metal had to have an appropriately high diffusion rate so that it could diffuse into the wafer in an acceptable time at this temperature.
  • Gold and platinum were typically used because they provided the appropriate combination of energy level, solid solubility and diffusion coefficient to allow the prior art processes to work. Other metals did not meet the needed combination of characteristics.
  • the dopant when the dopant is applied just prior to bonding, almost any dopant can be used and may be chosen based on energy level alone.
  • the dopants do not move far from the wafer-to-wafer bonding interface because the subsequent bonding temperatures are low enough to not cause any appreciable diffusion.
  • suitable heat treatments may be used.
  • references to bonding herein are intended to refer generally to any conventional bonding technique, and particularly to the above-mentioned wafer bonding method in which the bonding surfaces of two silicon wafers are polished sufficiently flat so that when the polished surfaces are brought into contact with each other, enough of the neighboring silicon atoms can form covalent bonds across the wafer-to-wafer bonding interface to link the two wafers into a single crystal.
  • a method of controlling minority carrier lifetime in a semiconductor device in which the density of recombination centers is controlled so that the recombination centers are concentrated in a thin buffer layer adjacent a blocking layer in one of two bonded wafers.
  • the density is controlled by misaligning crystal axes of the two wafers or by doping the bonding surface of one of the wafers before the wafers are bonded. Both methods generate recombination centers in the thin buffer layer that forms around or adjacent the bonding interface.
  • a semiconductor device made by this method includes a buffer layer with a significantly higher density of recombination centers than the adjacent blocking layer.

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  • Recrystallisation Techniques (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Claims (7)

  1. Procédé pour contrôler la durée de vie de porteurs minoritaires dans un dispositif semiconducteur à tranches liées, comprenant les étapes suivantes :
    prévoir des première et deuxième tranches (32), chaque tranche comportant une surface de liaison (30), chaque tranche comportant au moins une couche fortement dopée, et une des tranches comportant une couche de blocage faiblement dopée (22) en tant que couche de liaison, la couche de blocage faiblement dopée (22) étant placée directement sur la couche fortement dopée de la tranche ; caractérisé par
    un polissage, avant la liaison, d'une des surfaces de liaison (30) avec un décalage axial par rapport à l'autre surface de liaison pour produire, lorsque les tranches (32) sont liées, des dislocations au niveau de l'interface de liaison de tranche à tranche (20) sur les deux surfaces de liaison (30) de sorte qu'une couche tampon (24) est formée avec l'interface de liaison à l'intérieur ;
    le dopage d'une des surfaces de liaison (30) dans ce qui va devenir la couche tampon (24) ; et
    la liaison des tranches (32) entre elles au niveau de leurs surfaces de liaison (30) pour créer des centres de recombinaison pour des porteurs minoritaires dans la couche tampon (24).
  2. Procédé selon la revendication 1, dans lequel l'étape de polissage avec décalage axial provoque des stries de polissage dans la surface de liaison (30).
  3. Procédé selon la revendication 2, comprenant en outre l'évaporation d'un dopant sur une surface de liaison (30).
  4. Procédé selon la revendication 2, dans lequel l'étape de dopage comprend l'étape consistant à implanter des dopants métalliques dans la tranche (32) ne comportant pas la couche de blocage (22) puis à chauffer pour répartir les dopants métalliques.
  5. Procédé selon la revendication 2, dans lequel l'implant est un métal choisi dans le groupe comprenant Au, Pt, Pd, Ag, Cu, Fe, Ni et Co.
  6. Procédé selon la revendication 1, dans lequel la concentration du dopant dans la couche tampon (24) est comprise entre 1014/cm3 et 1019/cm3 et la densité des centres de recombinaison concentrés dans la couche tampon (24) est comprise entre 1014/cm3 et 1019/cm3 et l'épaisseur de la couche tampon (24) est comprise entre 1 micromètre et 50 micromètres.
  7. Procédé selon la revendication 2, dans lequel les stries de l'une des tranches sont orientées par rapport aux stries de l'autre tranche avec un angle compris entre un et quarante cinq degrés.
EP98111147A 1997-06-30 1998-06-17 Contrôle de la durée de vie pour des dispositifs semi-conducteurs Expired - Lifetime EP0889509B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/885,878 US6054369A (en) 1997-06-30 1997-06-30 Lifetime control for semiconductor devices
US885878 1997-06-30

Publications (3)

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EP0889509A2 EP0889509A2 (fr) 1999-01-07
EP0889509A3 EP0889509A3 (fr) 1999-11-17
EP0889509B1 true EP0889509B1 (fr) 2009-05-20

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US (1) US6054369A (fr)
EP (1) EP0889509B1 (fr)
JP (1) JPH1140633A (fr)
KR (1) KR100720675B1 (fr)
DE (1) DE69840843D1 (fr)

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KR100720675B1 (ko) 2007-11-12
KR19990007489A (ko) 1999-01-25
EP0889509A2 (fr) 1999-01-07
US6054369A (en) 2000-04-25
DE69840843D1 (de) 2009-07-02
JPH1140633A (ja) 1999-02-12

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