EP0910124A3 - Semi-conducteur avec une isolation latérale - Google Patents

Semi-conducteur avec une isolation latérale Download PDF

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Publication number
EP0910124A3
EP0910124A3 EP98307577A EP98307577A EP0910124A3 EP 0910124 A3 EP0910124 A3 EP 0910124A3 EP 98307577 A EP98307577 A EP 98307577A EP 98307577 A EP98307577 A EP 98307577A EP 0910124 A3 EP0910124 A3 EP 0910124A3
Authority
EP
European Patent Office
Prior art keywords
layers
oxidation
semiconductor
fets
oxidizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98307577A
Other languages
German (de)
English (en)
Other versions
EP0910124A2 (fr
Inventor
Jack Oon Chu
Khalid Ezzeldin Ismail
Kim Yang Lee
John Albrecht Ott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0910124A2 publication Critical patent/EP0910124A2/fr
Publication of EP0910124A3 publication Critical patent/EP0910124A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
EP98307577A 1997-10-16 1998-09-17 Semi-conducteur avec une isolation latérale Withdrawn EP0910124A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US951827 1997-10-16
US08/951,827 US5963817A (en) 1997-10-16 1997-10-16 Bulk and strained silicon on insulator using local selective oxidation

Publications (2)

Publication Number Publication Date
EP0910124A2 EP0910124A2 (fr) 1999-04-21
EP0910124A3 true EP0910124A3 (fr) 2000-08-16

Family

ID=25492209

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98307577A Withdrawn EP0910124A3 (fr) 1997-10-16 1998-09-17 Semi-conducteur avec une isolation latérale

Country Status (7)

Country Link
US (2) US5963817A (fr)
EP (1) EP0910124A3 (fr)
JP (1) JP3014372B2 (fr)
KR (1) KR100275399B1 (fr)
CN (1) CN1103497C (fr)
SG (1) SG67564A1 (fr)
TW (1) TW392223B (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US7846802B2 (en) 2001-09-21 2010-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

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* Cited by examiner, † Cited by third party
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US6251751B1 (en) 2001-06-26
CN1103497C (zh) 2003-03-19
TW392223B (en) 2000-06-01
US5963817A (en) 1999-10-05
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JP3014372B2 (ja) 2000-02-28
EP0910124A2 (fr) 1999-04-21
SG67564A1 (en) 1999-09-21

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