EP0929862A1 - Elements logiques pour systemes entrelaces de report de retenue/retenue negative possedant un agencement uniforme - Google Patents

Elements logiques pour systemes entrelaces de report de retenue/retenue negative possedant un agencement uniforme

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Publication number
EP0929862A1
EP0929862A1 EP96912409A EP96912409A EP0929862A1 EP 0929862 A1 EP0929862 A1 EP 0929862A1 EP 96912409 A EP96912409 A EP 96912409A EP 96912409 A EP96912409 A EP 96912409A EP 0929862 A1 EP0929862 A1 EP 0929862A1
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European Patent Office
Prior art keywords
input
output
gate
inverting
type
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EP96912409A
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German (de)
English (en)
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EP0929862A4 (fr
Inventor
Nathan Grundland
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Perkel Manley
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Perkel Manley
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3876—Alternation of true and inverted stages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Definitions

  • the present invention relates generally to switching systems, and more particularly to logic elements or cells having pairs of specific similar logic circuities comprising inverting output gates or complementary output gates, which are utilized for various ⁇ hierarchical ⁇ carry systems.
  • the present inventional so features advantages of gate construction using technologies having a complementary nature, as with the C-MOS technology.
  • a well-known technique for improving the computation speed is by constructing a parallel adder/subtractor with a fast carry/borrow speed-up system.
  • CLA carry look ahead
  • RS recurrence solver
  • SC skip carry
  • the SC technique as an example, requires impractical, irregular array construction, having a very high gate fan-in as the adder is expanded.
  • the structure of a carry system is partitioned into groups of bits in parallel at level one of a carry system, then into groups of groups in parallel at level two of a carry system, etc.
  • the conventional CLA system is based on partitioning of four (bits, groups) and the RS system is based on binary tree expansion, partitioning of two.
  • An adder is, in general, composed of three parts: the input part, the carry part and the sum part.
  • the embodiment of a fast carry system is based on the implementation of a pair of signals, the Generate (G) and the Propagate (P) signals.
  • G ⁇ " GB2 " P ⁇ 2 + GB2 • GB1 (Eq. 2b) where B2 and ⁇ l represent two respective bits bunches [k ⁇ (j+1)] and fj ⁇ (i+1)].
  • B2 and ⁇ l represent two respective bits bunches [k ⁇ (j+1)] and fj ⁇ (i+1)].
  • the typical True P and False P carry-propagate functions further require two different logical gates as follow:
  • Inversion is an inherent component in logic design techniques, which is used by existing practical design techniques and requires complicated logic combinations.
  • Texas Instruments in its component SN74S 181, offers essentially, the same two gates circuities for generating G or Y (pin 17) and P or X (pin 15) for True and False input signals.
  • a general object of the present invention is to establish a new approach in logic design regarding the specific logic domain, in which a specific pre-existing logic relationship exists.
  • Another general object of the present invention is to improve the performance of parallel adders constructed in different technologies featuring different advantages, mainly reducing the worst case propagation delay through the adders and to construct them in a most regular (repetitive circuits) layout uniformity.
  • a further general object of the present invention is to define and construct uniform logical cells, each including a pair of gates with minimum circuitry, utilized as building blocks for producing the carry generate and the carry propagate signal pairs of a carry system in a form that improves the overall adder/subtractor performance.
  • One object of the present invention is to construct a novel partitioned carry system having an Expanded Interlaced interconnecting pattern for improving carry system performance (reference is made to the paper entitled “Fast Area-Efficient VLSI Adders" by T. Han et al., Arith. Symp. 1987 IEEE p. 54, Fig 2.1).
  • Still one further object of the present invention is to construct a novel multibit comparator.
  • a further object of the present invention is to construct a modified extended bit-sum device, at the summing level of an adder/subtractor.
  • One further object of the present invention is to construct with a complementary output technology a 16-bit adder having a total of only 3 units (Wired-OR/NOR gates) delay.
  • One further general object of the present invention is to construct with Complementary (C-MOS) technology, a special group of logical gates characterized in having a sy ⁇ unetrical/anti-symmetrical (SAS) gate construction for use with the logical cells of the novel carry system.
  • C-MOS Complementary
  • SAS sy ⁇ unetrical/anti-symmetrical
  • One special object of the present invention is to construct with the C-MOS technology a modified bit-sum device having Tri-State output features.
  • Still one special object of the present invention is to construct with the C-MOS technology a Three-State gate structure for representing an arithmetic ZERO as a high-impedance output.
  • Still a further special object of the present invention is to construct, with the C-MOS technology, a special gate that provides an optional programmable carry-in input signal.
  • the present invention refers to the design of the carry system using the IMPLY function as a practical guideline for designing a carry system for adders/subtractors.
  • the IMPLY relationship is referred to in the texts "Logic Design of Digital Systems” by D. L. Dietmeyer, Allyn & Bacon, Inc. (1971), pp. 130-131, and in “Modern Switching Theory and Digital Design” by S. C. Lee, Prentice-Hall (1978), p. 38.
  • the invention applies these functions as they relate to two different terms corresponding to the U and V input signals at Eq. 4a and Eq. 4b and to the Propagate and the Generate functions whether for one bit i or for a bunch of bits ⁇ .
  • Xi and Yi are the i-th bit of two N-bits operands [X] and [Y]. (+) and ( • ) are respectively representing the OR and the AND combinations.
  • the carry-Propagate (P) term will hereinafter be referred to as a carry- Integrate (I) term, as it includes the carry-Generate signal (information) with the carry-Propagate signal (information), (in other words, a redundant term Gi is included in the Pi term).
  • Eqs. 5a, 5c, 5d and 5e indicates that the TWIN, True and False, Generate and Integrate signal pairs, can be produced by the same AND-NOR gate combination, which is the same gate construction as for the carry signal over one bit (i+1):
  • the Cin(i+1) signal may be replaced by Cin(i+1) giving the Cout (i+2) signal expression or vice versa.
  • Inverting Eqs. 5a, 5c, 5d, 5e, 5f and 5g provides the True and False Generate and Integrate signals which are produced by the same OR-NAND gate, all of which are referred to herein as Binary gates, and similarly, a Binary gate pair comprises a Binary cell which implements the matched TWIN Generate and Integrate signal function pair and the Carry signal function pair.
  • the Generate and the novel Integrate signal functions are the matched TWIN signal function pair which replace the prior art Generate G ⁇ (or G ⁇ ) and the Propagate ⁇ P ⁇ (or ⁇ P ⁇ ) signals.
  • ⁇ - represents a bunch of bits j to i+ 1
  • ⁇ - represents a bunch of bits k to j+ 1
  • the general form of the carry signal expressions is given by:
  • False input signals C ⁇ ⁇ LB + GB • Co
  • TWIN signal expressions are implemented: G ⁇ ⁇ IB • (GB + G ⁇ ) , T ⁇ ⁇ IB • (GB + G ⁇ ) I ⁇ ⁇ GB • ( ⁇ B + T ⁇ ) , G ⁇ ⁇ G ⁇ • (T ⁇ + G ⁇ )
  • the general form of the carry signal expressions is given by: C ⁇ ⁇ IB ⁇ (G ⁇ + C ⁇ ) C ⁇ ⁇ GB ⁇ (IB + C ⁇ )
  • the defined cells are based on the partitioning choice as well as on the logic expression of the gate. These novel cells are used in an expanded interlaced interconnection form implementing an Expanded Interlaced Carry system (ElC-system), with the same partitioning choice.
  • ElC-system Expanded Interlaced Carry system
  • CMOS gates are affected and can be modified wherever the IMPLY relationship is involved in logic functions.
  • the novelty is characterized in the embodiment of gates, featuring symmetrical structure of switching pairs and crosswise (anti-symmetrical) wiring actuating these pairs (SAS gates), where pairs of gates are not fed by a common input signal, rather they are fed by a pair of signals having the IMPLY relationship.
  • SAS gates crosswise (anti-symmetrical) wiring actuating these pairs
  • pairs of gates are not fed by a common input signal, rather they are fed by a pair of signals having the IMPLY relationship.
  • the same pairs of signal expressions enable the use of the same logical cells, for either True or False input signal polarities.
  • the Expanded Interlaced Carry system utilizes the same logical cells as building blocks for the pairs of Generate and Integrate (Propagate) terms and the Carry, Not-Carry terms.
  • both polarities of the carry signals are available for the sum level rather than with additional inversion level.
  • the number of fanouts at either of the sequential carry levels are constant (rather than being doubled as for the binary tree, recurrence solvers carry system).
  • Tri-State conditions are accepted without additional delays through the critical signal path of a carry system.
  • Fig. la illustrates a prior art cell, comprising a pair of gates which produces the Generate and Propagate signal pairs for True input polarity;
  • Fig. lb illustrates a prior art cell, comprising a pair of gates which produces the Generate and Propagate signal pairs for False input polarity
  • Fig. lc illustrates a logic symbol of a conventional inherently inverting AND-NOR gate referred to herein as a Binary Inverting Gate
  • Fig. Id illustrates, in accordance with the present invention, a logic schematic of a pair of logic symbols given in
  • Fig. lc referred to herein as a Binary Inverting Carry cell (BIC-cell) having two input pairs, for implementing a novel twin Generate and Integrate output signal pair, with the twin output signal pair providing a predetermined logic relationship;
  • BIC-cell Binary Inverting Carry cell
  • Fig.le illustrates a logic symbol of a conventional inherently inverting OR-NAND gate also referred to herein as a Binary Inverting Gate;
  • Fig. If illustrates a logic schematic of a BIC-cell as described in Fig. Id of a pair of logic symbols as in Fig. le;
  • Fig. 2a illustrates a conventionally combined logic schematic of two NOR gate logic symbols referred to herein as a Binary Non-inverting Gate
  • Fig.2b illustrates a logic schematic, in accordance with the present invention, of a pair of two NOR gate logic symbols as described in Fig.2a, referred to herein as a Binary Non-inverting Carry cell (BNC-cell) having two input pairs, for implementing a novel twin Generate and Integrate output signal pair, with the twin output signal pair having a predetermined logic relationship;
  • BNC-cell Binary Non-inverting Carry cell
  • Fig. 2c illustrates a conventionally combined logic schematic of two NAND gate logic symbols also referred to herein as a Binary Non-inverting Gate
  • Fig. 2d illustrates a logic schematic of a BNC-cell as described in Fig. 2b using a pair of schematics as in Fig. 2c;
  • Figs. 3a and 3b illustrate, for reference only, prior an implementations with Complementary (MOS) technology of an inverter and of a gate operating in a Tri-State mode;
  • MOS Complementary
  • Fig.3c illustrates, in accordance with the present invention, a schematic of basic logic components for circuit implementation with CMOS technology of a gate being inputted with a twin input signal pair having between them, a predetermined logic relationship;
  • Fig. 3d illustrates, in accordance with the present invention, a C-MOS technology circuit implementation of an AND-NOR gate, given in Fig. lc and utilizing the schematic of the basic logic components given in Fig. 3c, featuring a non-conventional gate combination having a Symmetrical switching components wiring layout and a crosswise (Anti-Symmetrical) actuation wiring layout, referred to herein as a Binary SAS Inverting Gate (SAS gate), having further in accordance with the present invention, an input signal pair with a preexisting logic relationship of predetermined signal expressions;
  • SAS gate Binary SAS Inverting Gate
  • Fig. 3e illustrates, in accordance with the present invention, a C-MOS technology circuit implementation, similar to that of Fig. 3d, featuring the use of a non-conventional gate combination of an OR-NAND gate, given in Fig. le;
  • Fig. 3f illustrates a unique version of Fig. 3d
  • Fig. 3g illustrates a unique version of Fig. 3e
  • Fig. 3h illustrates a C-MOS technology circuit implementation of a BIC-cell as described in Fig. Id, comprising two modified binary SAS gates related to Fig. 3d, implementing a novel binary twin Generate and Integrate output signal pair, with the twin output signal pair having a predetermined logic relationship;
  • Fig. 3i illustrates a C-MOS technology circuit implementation of a BIC-cell as described in Fig. I f, comprising two modified binary SAS gates related to Fig. 3e, implementing a novel binary twin Generate and Integrate output signal pair, with the twin output signal pair having a predetermined logic relationship;
  • Figs. 4a-4d illustrate in accordance with the present invention, a C-MOS technology circuit implementation of logic circuities, for implementing novel ternary gates referred to herein as Ternary SAS Inverting Gates featuring, as for Figs. 3d and 3e, the use of non-conventional gate combinations, used for implementing the ternary Generate and the ternary Integrate output signals;
  • Fig. 4e illustrates schematically, in accordance with the present invention, a cell referred to herein as a Ternary Inverting Carry cell (TIC-cell) comprising a pair of ternary inverting gates which are as in Figs. 4a-4d, for implementing a twin Generate and Integrate output signal pair, with the twin output signal pair having a predetermined logic relationship;
  • TIC-cell Ternary Inverting Carry cell
  • Fig. 4f illustrates in accordance with the present invention, a C-MOS technology circuit implementation of logic circuities, for implementing a novel gate for a skip carry system;
  • Fig. 5a illustrates, with a C-MOS technology, a prior art circuit implementation of a typical bit-sum cell
  • Fig. 5b illustrates, with a C-MOS technology, a circuit implementation of a bit-sum cell, given in Fig.5a, which incorporates the Tri-State connection through the half-sum H signals;
  • Fig. 5c illustrates, with a C-MOS technology, in accordance with the present invention, a modified circuit implementation of an extended bit-sum cell
  • Fig. 5d illustrates a circuit implementation of a bit-sum cell, given in Fig. 5c which incorporates the Tri-State connection as described in Fig.5b and incorporates a connection whether to ENable or Disable a carry input signal into the sum level;
  • Fig.5e illustrates a logic schematic that produces the four combined Tri-State signal functions which are used with Figs. 5b and 5d
  • Fig.5g illustrates an elementary complementary conduction/inverting N-mos and non-conduction/inverting P-mos transistor pair combination having in accordance with the present invention, an input signal pair with a preexisting logic relationship of predetermined signal expressions providing meaningful Tri-State output states;
  • Fig. 5h illustrates a useful implementation of Fig. 5g
  • Fig. 5i illustrates an alternative version of Fig. 5h
  • Fig. 5j illustrates a novel minimized implementation of the H function as a function of G and P.
  • Fig. 6a illustrates a prior art Complementary Outputs Logic schematic (COL-schematic), comprising the logic symbols of four OR/NOR gates, producing the complementary outputs of one-bit Generate and one-bit Propagate terms, and the complementary half-sum output signals for each of the two input bits;
  • Fig. 6b illustrates, in accordance with the present invention, a COL-schematic comprising the logic symbols of six OR/NOR gates combining the WIRED-OR and WIRED-AND logic circuitry of three logic symbols each, for producing the twin two-bit Generate and the two-bit Integrate complementary output signal pair, with the complementary twin output signal pair having a predetermined logic relationship;
  • Fig. 6c illustrates a prior art COL-schematic comprising the logic symbols of two OR/NOR gates, producing complementary bit-sum F signals
  • Fig. 6d illustrates, in accordance with the present invention, a COL-schematic comprising the logic symbols of four OR/NOR gates, for implementing modified extended bit-sum F signals;
  • Fig. 7a illustrates, in accordance with the present invention, a cell comprising a pair of logic schematics each comprising four OR/NOR gates, each logic schematic combining the WIRED-OR and WIRED-AND outputs for each of the four gates, defining the cell as a Quaternary Complementary Carry cell (QCC-cell), for implementing the quaternary twin Generate and Integrate complementary output signal pair, with the complementary twin output signal pair having a predetermined logic relationship;
  • QCC-cell Quaternary Complementary Carry cell
  • Fig. 7b illustrates a QCC-cell as described in Fig. 7a where each logic schematic is minimized into three OR/NOR gates;
  • Fig. 7c illustrates a Quaternary Carry cell (QC-cell) that differs from the QCC-cell as described in Fig.7b in that the WIRED-AND outputs of the QC-cell are minimized, producing a pair of (Quasi-Sum) signals which are properly used as substitute signals for the quaternary twin Generate and Integrate signals;
  • QC-cell Quaternary Carry cell
  • Fig. 8a illustrates schematically, a floor-plan layout of a general purpose Binary partitioned Expanded Interlaced array using, in accordance with the present invention, the BIC-cells as described in Figs. Id, If, 3h, 3i or the BNC-cells as described in Figs. 2b and 2d;
  • Fig. 8b illustrates schematically, a modified floor-plan layout of Fig. 8a, used as a Carry system (Binary ElC-system) for an 8-bit adder/subtractor or a comparator;
  • Carry system Binary ElC-system
  • Figs. 9a, 9c (Table 1), illustrate as an example, a schematic of logic symbols implementing an 8-bit adder using the Binary ElC-system as in Fig.8b with the BIC-cells of Fig. Id, where Zone A in Table 1 represents the implemented signal function pairs according to the present invention
  • Fig. 9b illustrate as an example a schematic circuit of logic symbols implementing the design of an 8-bit adder using the Binary ElC-system as in Fig. 8a with the BNC-cells of Fig. 2b;
  • Fig.10 illustrate a floor-plan layout representing a carry system which interlaces 16 groups of 4-bits into a main four-level Binary ElC-system which provides a carry system for a 64-bit adder;
  • Fig.1 1 illustrate a floor-plan layout representing an 89-bit adder without input provision for Cin, which interlaces, ten groups of 9-bits, each with a Ternary partitioning ElC-system into a main two-level Ternary ElC-system;
  • Fig. 12a illustrates as an example, in accordance with the present invention, a schematic circuit of logic symbols implementing the design of a two-bit slice adder;
  • Fig. 12b illustrates, a schematic floor-plan array, representing a 16-bits adder array which comprises eight slices as represented by Fig. 12a;
  • Fig. 13 illustrates in accordance with the present invention, an example of a schematic floor-plan array of a 16-bit comparator including adder/subtractor.
  • the cell 32 of Fig. 4e can be used for a Ternary ElC-system, and the cells 34, 36 or 38 respectively of Figs. 7a, 7b or 7c can be used for a Complementary Quaternary ElC-system.
  • the BIC-cell 20 comprises a pair of gates as in Fig. lc, and implements the logical expressions which are derived from Eqs. 4a and 4b;
  • the BIC-cell 22 comprises a pair of gates as in Fig. le, and implements the logical expressions;
  • the modified Expanded Interlaced array relies on a mathematical method describing binary expansion, indicating that a wiring pattern which corresponds to the appropriate (R-based, Binary, Ternary etc.) cells (elements, nodes) has a regular and uniform layout and interconnecting pattern as shown in Fig. 8a (refer to the paper, "A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations, by P. M. KOGGE et al., IEEE Trans, of Computers Vol. C-22 No. 8, pp. 786-792, Aug. 1973)
  • k(e,i) is a cell at level e and position i.
  • An interlaced pattern can be expanded to any number N of bits (positions i).
  • the required number of levels is a function of the required number of positions according to L ⁇ LOG R N > (L-l).
  • R e, i and r are parameters defining the specific locations or wire connections of each cell in the layout, with the following ranges:
  • Cells K accept wire connections from R cells at the preceding level which are located at: [e-1 , i-r • R ⁇ e-1 ⁇ ] for R > r > 0.
  • Cell K (e, i) delivers wire connections to R cells at the succeeding level which are located at: [e+1, i+r • R ⁇ e ⁇ ] for R > r ⁇ 0.
  • a set of output wire connections per cell comprises at least one pair and can be more for R > 3 or at least four wires for complementary output technology.
  • 8a is an example of an interconnections array 44 having eight positions with three logic levels for eight input wire pairs 46 A in i and Bin i and eight output wire pairs 48 Aout i and Bout i, and additional peripheral input pairs 50, designated A ⁇ e>in ⁇ and B ⁇ e>in ⁇ .
  • peripheral input pairs A ⁇ 2>in 2 and B ⁇ 2>in 2, A ⁇ 3>in 2 and B ⁇ 3>in 2, A ⁇ 3>in 3 and B ⁇ 3>in 3, and A ⁇ 3>in 4 and B ⁇ 3>in 4 are redundant for a carry system array Fig. ⁇ b but they are preferably included in the description for showing the regular consistency of the array. Additional peripheral output pairs 52 A ⁇ e>out ⁇ and B ⁇ e>out ⁇ are also redundant but might appear in a design with CAD (computer aided design) tools.
  • CAD computer aided design
  • Figs. 9a, 9c shows the embodiment of an 8-bit adder utilizing the Expanded Interlaced wiring array 54 of Fig. 8b and the BIC-cells 20 of Fig. Id as the building blocks K and the cells Kl of Fig. lc 21.
  • the entire carry system wiring for an 8-bit adder at each block K and Kl can be realized through the use of the logic expressions at each respective rectangular of Table 1.
  • the twin Gi and Pi(Ii) signal pairs 76, for 8 > i ⁇ 1 are respectively connected to the inputs, A in (i) and Bin (i) 46 of the Binary ElC-system array 54 of Fig. 8b.
  • the carry-in, Cin input signal 58 is designated C ⁇ 0> 1 , notice that the subscripts for C and C are higher by 1.
  • HEET RULE 26 Each of the output signals Gi and Pi is respectively connected to two BIC-cells 20 located at level el position (Pos.) i, K(l,i) and Pos. i+1, K(l,i+1) producing the twin signal pairs 60 for two bits with respect to Pos.
  • the C ⁇ 0>1 signal is inverted, producing the C ⁇ 1>1 signal 64.
  • Detailed logic signal expressions are given in Col. 2 of Table 1.
  • Each of the twin output signal pairs 60 G(i+ l,i) and I(i+l,i) is connected to two respective BIC-cells 20 located at level e2 Pos. i, K(2,i) and Pos. i+2, K(2,i+2) producing the four bitt win output signal pairs 66 with respect to Pos. 8 ⁇ i ⁇ 4 as follows: the G(8,5) and 1(8,5) twin output signal pair , the G(7,4) and 1(7,4) " the G(6,3) and 1(6,3) " the G(5,2) and 1(5,2) " the G(4,l) and 1(4,1) " and with respect to Pos.
  • Table 1 Detailed signal expressions are given in Col. 4 of Table 1.
  • the Gi signals of 76 are inverted, producing the Gi signals 77, which are inputted into the half-sum gates 78 for producing the function Hi ⁇ Gi • Pi.
  • the Hi signals 80 are inverted, producing the Hi signals.
  • the Ci , Ci signal pairs and the Hi , Hi signal pairs are connected to the bit-sum cells (F) at the output level 82, producing the bit-sums Fi result, using for 8 ⁇ i ⁇ 1 the signal expressions Fi ⁇ Hi • Ci + Hi • Ci and yielding a full-sum for an 8-bit adder.
  • the G(8,l) signal at (Bout8) and the 1(8,1) 72 signal at (Aout8) can be used to generate the C9 and C9 output signal pair, the overflow output signal or being inverted and giving the G(8,l) and 1(8,1) signals for further producing the following novel signals:
  • Eq. 6a indicates that the mantissa in a Floating Point adder can be normalized over eight bits.
  • the Cells GPHi implements the functions Gi ⁇ Xi + Yi Pi ⁇ Xi • Yi AND Hi ⁇ Gi + Pi.
  • the cells B implement the logic circuit of Fig. lc
  • the cells BB represents the BIC-cells 20.
  • This example completes an 8-bit adder, representing the principal embodiment of the novel adder/subtractor/comparator yielding a total of less than five (single) units delay and one inverter delay.
  • the fanout loading of the example has a maximum of four fanouts at the initial Gi and Pi signals and maximum three fanout at either level of the Binary ElC-system, rather than, at least five fanouts at the worst case (critical) signal path propagation delay of plural carry levels, L > 3 , as with the prior art binary tree.
  • Fig. 8a for the adder of Fig. 9b indicates a full bit slice regularity and uniformity. However the BNC-cells 28 (or 30) marked ⁇ K 88 are redundant.
  • the BNC-cells 28 of Fig. 2b implement the following twin signal pairs;
  • the inputs A l and Bl of cells K(2,l), K(3,l)and K(3,2) may be connected to either LOGIC HIGH or LOGIC LOW.
  • a unique advantage of the design with only NOR gates (or NAND gates) is, that although both polarities are required at either logical level, inverters are not needed and a very regular bit slice and compact design is gained.
  • the example relates to any adder/subtractor having higher bit amount. Notice that the G signals have True polarity and the I signals have False polarity. This is dictated by the use of the NOR gates or inversely by the NAND gates.
  • the inverters (marked b) 90 can be eliminated by replacing the two-input NOR gates (marked m) with three-input NOR gates.
  • Fig. 10 is a carry system for a 64-bit adder.
  • Fig.10 include the input level eO having sixty four input cells Q, sixteen sub-groups Mi of 4-bits comprising levels eland e2, one main-group 100 of 16-positions comprising levels e3, e4, e5 and e6, an inverting level and one final level e7.
  • Each sub-group Mi utilize a 4-bits Binary ElC-system array and the main-group 100 utilize a 16-positions Binary ElC-system array.
  • Rectangles K represent one BIC-cell 20
  • rectangles D represent the logic circuit of Fig. lc
  • rectangles E represent the logic circuit of Fig. lc and an inverter
  • rectangles F represent three H rectangles
  • rectangles H represent two circuits as per Fig. lc.
  • the Q cell of level eO are organized in four bits per group where there are implemented, the twin output signal pairs G[4(g-l)+i] and P [4(g-l)+i] as a function of the sub-group Mi Pos. 16 ⁇ g > 1 and the bit-Pos. 4 ⁇ i ⁇ 1 per sub-group.
  • the twin signal pairs are:
  • the four twin output signal pairs of each sub-group Mi are represented by the signal pair G[(4(g-l )+i) , (4(g-l)+ l)] and I[(4(g-l)+i) , (4(g-l)+l)].
  • the twin output signal pairs of each sub-group Mi are respectively connected, directly and through inverters, to the H rectangles at the F rectangles at the final carry level e7.
  • the twin output signal pairs G [4g,4(g-l)+ l] and I[4g,4(g-1)+1] of each sub-group Mi is connected to the respective input end pair 102 of the main group 100.
  • the twin output signals pairs 106 are inputted to the respective D and E cells where they are combined with less significant carry signals for producing at the D and E cells output ends 108 the more significant carry output signals C(4g + 1 ) and their inverted output signal C(4g + 1).
  • the twin output signal pair 1 10 is G(64, 1) and 1(64, 1).
  • the Carry output signals C[4(g-1) + 1] and C[4(g- 1) + 1] are the final carry signal pairs and are directly used for the bit -sum F[ (g-1) + i] (not shown).
  • the Carry output signals C[4(g-1) + 1] and C[4(g-1) + 1] are respectively combined to the respective H rectangle at the respective rectangle F with the respective signal pair of the three twin output signal pairs from the respective groups 102 and inverters 1 12 producing thereby the final carry signal pairs according to the following carry signal function pair: C[4(g- l)+i] ⁇ G[(4(g-l)+(i-l)) , (4(g-l)+l)] +
  • This fast carry system comprising Binary Grouped Binary ElC-systems and referred to as BGB ElC-system, yields a 64-Pos. carry system having seven units delay + inverter delay(excluding level eO) rather than eleven units delay + inverters as with the carry look ahead system.
  • the max. fanout at the main Binary ElC-system outputs is four (adjacent loads).
  • the total amount of carry cells is 355 AND-NOR gates of Fig. lc + 119 inverters.
  • the BGB-system uses 13V2 elements (gates and inverters) per bit adder.
  • Fig. 1 1 is a schematic floor-plan of an 89-bit Adder, with C in. Fig. 11 is composed of one main group 130 and ten sub-groups 132 each having 9-bit positions (i). Rectangles marked K represents one Ternary cell 32 as Fig. 4e, rectangle marked ⁇ K represents one Ternary gate as Fig.4a and inverter, rectangle marked ⁇ K1 represents one Ternary gate as Fig. 4a, rectangle marked #K represents one Binary gate as Fig. lc and inverter, rectangle marked #K1 represents one Binary gate as Fig. lc and rectangle marked M represents an extended bit sum cell as Fig. 5c.
  • the nine output signal pairs produced at each group gia are G[9(g-l)+i,9(g-l)] and I[9(g-l)+i,9(g-l)] except for group gla.
  • the output signal pairs for 10 > g ⁇ 2 and 7 ⁇ i 0 are G[9(g-l)+i,9(g-l)] and I[9(g-l)+i,9(g-l)] which are directly connected to the extended bit -sum cells marked M at the sum level marked D and through an inversion level marked R, producing the inverted matched twin output signal pairs G[9(g- l)+i,9(g-l)] and I[9(g-l)+i,9(g-l)] which are also connected to the extended bit-sum cells M at the sum level marked Di.
  • the output signal is the grouped carry signal C ⁇ 2>9 134.
  • the matched twin output signal pair of each group gia is G[9g-l,9(g-l)] andl[9g-l,9(g- l)]136 which are connected to the respective input end pair positions of the main Ternary ElC-system array 130 producing the matched twin output signal pairs at the output end 138 as follows: the G[17,9] and I[17,9) signals are combined with the C ⁇ 2>9 signal, producing the C ⁇ 3>18 which is then inverted, and combining G[26,18], I[26,18], G[17,9], I[17,9] and C ⁇ 2>9 signals for producing the C ⁇ 3>27 signal which is then inverted, and combining G[17,9], I[17,9], G[26,18], I[26,18], G[35,27] and I[35,27] signals for
  • the G[9(g-1) + i] signals at level eO are inverted (not shown in Fig. 11), producing the signals G[9(g-1) + i] which are required for producing the Half-sum H[9(g-1) + i] signals as follows: H[9(g-1) + i] ⁇ G[9(g-1) + i] ⁇ P[9(g-1) + i].
  • the H[9(g-1) + i] signals are inverted (not shown in Fig. 1 1) for producing the signal H[9(g-1) + i].
  • bit-sum signals are implemented at the extended bit-sum cells M having the following logical expression; F ⁇ H-G + H I C + H I + H-G : [or Alternatively by F ⁇ (H + G) (H + I + C) H + T) H + G + C)].
  • bit-sum signals are implemented by prior art cells (marked m) using the logical expression F ⁇ H • C + H • C [or alternatively by F ⁇ (H + C) • (H + ] where the signal combinations are obvious.
  • the Ternary-Grouped Ternary ElC-system (TGT ElC-system) of Fig. 11 yields an 89-bit adder having six logic levels + inv. including the input and the sum level giving six TIC-cells + inv. units delay (buffers, if required, are not included). It includes also one additional inversion level which doesn 't affect the worst case signal path propagation delay of the adder.
  • the maximum fanout loading at the output of level eO, the initial Pi and Gi signals is six, and this can be reduced to five.
  • the maximum fanout loading at either carry level is five and can be reduced to four.
  • the maximum fanout loading at the outputs of the main Ternary ElC-system is nine.
  • the average amount of logical elements per bit (including inverters) is 11.
  • a 32-bit adder can be constructed by using an input logic level, eight sub-groups of 4-bits having two levels Binary Expanded Interlaced Carry system and one main group having three levels Binary expanded carry system and a final sum level using extended bit-sum devices resulting in a reduced amount of components.
  • One further example of a Grouped ElC-system which provides flexible partitioning and optimized adder dimensions can be constructed by mixing Binary and Ternary ElC-systems, e.g. for multiplication, by implementing a Carry Assimilate Adder (CAA).
  • CAA Carry Assimilate Adder
  • This design uses 4-bit groups, either as a single level Quatenary groups (Q-groups) or as a two levels Binary groups.
  • the Q-groups comprise one Quatenary carry cell (QC-cell) and additional gate pairs, in which the output end pairs of the QC-cells of each of the Q-groups are connected to the input end pairs of a sub-main ElC-system based on any partitioning number.
  • Grouping of groups as in this example requires two additional logical levels for the carry system or one logical level and extended bit-sum cell. Longer wires have less fanouts.
  • Fig. 12a represents a two-bit adder herein referred to as a slice 180 (s).
  • Fig. 12b shows a 16-bit adder comprising eight slices 180 and additional peripheral circuitry 182 at the most significant side. This adder design yields only three units delay including the input and the sum levels having in general a fanout less than four per output.
  • the two-bit slice adder 180 of Fig. 12a comprises one logical circuit 184 as in prior art Fig. 6a, one logical circuit 186 as in Fig. 6b, two ED gates 188, two QC-cells 38 as in Fig. 7c and two extended bit-sum cells 190 as in Fig. 6d.
  • Fig. 6b implements the two-bit carry Generate G(2s-1, 2s-2) ⁇ G(2s-I,2) [the symbol ( ⁇ ) indicates that the term on the right side is a short version of the term on left side] and the modified two-bit carry Integrate (Propagate) I(2s-1.2) terms according to the following signal expressions of Equation Group No. 1.
  • the underlined input terms X/Y(2s-1) are the modifying term for I(2s-1,2) and ⁇ (2s-l,2) of the twin complementary output signals with respect to the prior art.
  • the output signals G(2s-1,2) and I(2s-1,2) are highly loaded (12 loads), therefore, the ED gates 188 produce the following logical-sum ( ⁇ )signals,for driving four fanouts at the appropriate location (slice);
  • Fig.7a shows the basic QCC-cell 34 which readily provides four output signals having the complementary output signals G ⁇ , G ⁇ , I ⁇ and I ⁇ .
  • Fig. 7b shows a QCC cell 36 which is a minimized cell of Fig. 7a and Fig. 7c shows a QCC-cell 38 which is a further minimization of Fig. 7b providing the signals:
  • These substitute signals (marked with ⁇ ) are referred to herein as Quasi-Sum signals which are no longer the complementary signals of the ED outputs and no longer contain the information that maintains the IMPLY relation. Yet, in order to reduce fanout, the Quasi-Sum signals are used at appropriate locations replacing logical-sum signals, e.g. at the sum-level.
  • Each cell of Figs. 7a-7c may be used in a Quaternary ElC-system.
  • the Quasi-Sum signals ⁇ GB and ⁇ IB may replace, where possible, the original signals GB and f ⁇ at locations ⁇ GB and ⁇ IB inputs in Figs.7a-7c.
  • the minimized terms are used, shown as an example, in the following twin binary signal functions;
  • the sum-level comprises the extended bit-sums 190 of Fig. 6d, which is a modification of the prior art extended bit-sum gate that implements the following signal expression;
  • I(2s-1,8) + H(2s) ⁇ ⁇ CD F(2s)
  • DI/EN Disable/Enable signal
  • the unwired inputs should be connected to LOGIC LOW "0".
  • the output signals G(2s-1 , 2), I(2s-1 , 2),T(2s- l , 2) and G(2s-1 , 2) are respectively C*2, C**2, C**2 and C*2.
  • the I(2s-1 , 8) signals becomes the C(2s) signals and the G(2s-1 , 8) signals becomes the C(2s) signals.
  • C**2, C*2, C**4, C*4, C**6, C*6, C**8 and C*8 are available and used at the next logical level (the sum-level).
  • Overflow signal expression (OV16), not shown in the drawings can be implemented by utilizing Eq. 9;
  • Symmetrical/Anti-Symmetrical(SAS) C-MOS gates structures having associatively symmetrical wiring of the (transistor) switching part (drain and source) and crosswise Anti-Symmetrical wiring of the (transistor) actuating part (the gate).
  • Fig. 3a shows a prior art implementation with a common input terminal connected to the complementary transistor gate pair forming an inverter, meaning that the same signal and polarity is fed as input to the circuit.
  • Fig.3c a separate input terminal pair is shown connected to the gates of the first transistor pair being fed by a pair of signals, Su and Sv, which are not complementary (but Sv includes Su).
  • This pair of signals Su and Sv corresponds to B includes A (B> A), and this feature is accomplished by additional circuitry as given by Figs. 3d, 3e, 3f, 3g and others.
  • D, E and F n-MOS transistors.
  • the drains of transistors D and E are connected to the Y output and the source of transistor D is connected to the Vss.
  • the source of transistor E is connected to the drain of transistor F and the source of transistor F is connected to the Vss.
  • D, E and F p-MOS transistors At the p-MOS zone there are D, E and F p-MOS transistors.
  • the drains of transistors D and E are connected to the Y [ or Z ] output and the source of transistor D is connected to the Vdd.
  • the source of transistor E is connected to the drain of transistor F, and the source of transistor F is connected to the Vdd.
  • the U input end is connected to gates of the D n-MOS and E p-MOS transistors, the V input end is connected to the gates of the E n-MOS and D p-MOS transistors and the W input end is connected to the gates of both F transistors.
  • SUBSTTTUTE SHEET (RI1LE26) feature can be combined into bit-sum cells and can be used to drive a bus having parallel inputs.
  • a pair of Binary SAS C-MOS gates comprises a BIC-cell 20 which performs the same functions as Fig. Id (or as Fig. If)-
  • Fig. 3h provides a further modification of the BIC-cell 20 which comprises ten transistors rather than twelve.
  • the BIC-cell 24 comprises five N-type MOS transistor Dl , El, FI, GI and HI and five P-type MOS transistor D2, E2, F2, G2 and H2 having the circuit embodiment as follows.
  • the input end A2 is connected to the gates of H2, El and Dl.
  • the input end B2 is connected to the gates of HI, E2 and D2.
  • the input end A 1 is connected to the gates of G 1 and G2.
  • the input end Bl is connected to the gates of FI and F2.
  • the sources of H2, E2 and D2 are connected to Vdd.
  • the sources of HI, El and Dl are connected to ground.
  • SUBSTTTUTE SHEET RULE 26 The drain of H2 is connected to the sources of G2 and F2.
  • the drain of HI is connected to the sources of Gl and FI.
  • the drains of Gl, G2, Dl and D2 are connected to the output BO.
  • the drains of FI, F2, El and E2 are connected to the output AO.
  • the logic circuitry of gate, the n-MOS transistors and the p-MOS transistors, are the same AND-OR combination with respect to the output Y for U + V • W or the same OR-AND combination with respect to the output Z for V • (U + W).
  • the G signal will be connected to the U input of the n-MOS transistor and to the V input of the p-MOS transistor.
  • the I signal will be connected to the V input of the n-MOS transistor and to the U input of the p-MOS transistor.
  • the C or C signals will commonly be connected to the W inputs of the n-MOS and the p-MOS transistors.
  • the W input may respectively accept G or I signals of the same polarity as the signals to U and V inputs.
  • Figs.4a- 4b are respectively implementing the four different gate structures for the four different logic expressions giving the same logical results.
  • a pair of either one or two of the four different Ternary SAS C-MOS gates of Figs.4a-4d comprise a logical TIC-cell 32, as shown in Fig. 4e.
  • the TIC-cell 32 has one output end pair (Ao , Bo) and three input end pairs (A3 , B3), (A2 , B2) and (Al , Bl).
  • Input end U3 of both gates are wired to A3 and input end V3 of both gates are wired to B3.
  • Input end U2 of both gates are wired to A2 and input end V2 of both gates are wired to B2.
  • Fig. 5a represents an ordinary bit-sum gate which can be used with the BGB-system of Fig.10.
  • Fig. 5c is a modified extended bit-sum gate which can be used with the TGT-system of Fig. 11. THE TRI-STATE EMBODIMENT OF AN ADDER
  • Figs. 5b, 5c, 5d and 5e In order to connect in parallel several input sources, e.g. bi-directional gates with bit-sum outputs of an adder to a bus, a Tri-State signal T is combined as shown in Fig. 5e with the half-sum Hi and Hi signals producing four signals H A i, H ⁇ i, H A A i and H A A i. These signals are respectively connected to the appropriate inputs of Fig. 5b replacing Fig. 5a, or to the appropriate inputs of Fig. 5d replacing Fig.5c.
  • Fig. 5b the H ⁇ i signal is connected to the G gate at the N-zone, the H A A i signal is connected to the F gate at the N-zone, the H A i signal is connected to the G gate at the P-zone and the H A A i signal is connected to the F gate at the P-zone.
  • Fig. 5d A similar construction is shown in Fig. 5d.
  • N-bit adders similar to the descriptions of Figs. 9, 10 and 11 are designed with the CMOS technology implementing the Tri-State option.
  • Adders may function with or without a Cin carry input, having different features.
  • my previous patent No. 4,584,661 such an implementation (splitting a multi-bit adder) is described.
  • Fig. 4f represents one example of a special gate which is useful in a skip carry technique.
  • This gate combines the skip carry (Cs) signal over a Variable Group (g) of propagate signals in parallel with the ripple carry (Cr) signal.
  • Two different (inhibited) signals ⁇ P and ⁇ G are used for the skip gate, each loaded by only one transistor according to the following signal expressions of the carry skip gate; j - i at the n-MOS zone Gj + Pj [Crj + ⁇ ⁇ Pg ⁇ • Cs(i+ 1)]
  • Fig. 5h is an example, showing a logic circuit where an arithmetic zero is represented as the third state output.
  • N-bit operand is represented by Bn bits, where 1 ⁇ n ⁇ N, the N-th Bit is the sign bit, negative numbers (NEG) are represented by BN, zero (ZERO) is
  • POS and NEG are INHIBITed or POS IMPLIES NEG, which also means that

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Abstract

Cette invention concerne des éléments logiques (20) destinés à des systèmes de comparaison et de report de retenue/retenue négative, lesquels éléments fonctionnent selon la relation logique de type IMPLY. Le recours à cette relation logique permet de surmonter le problème inhérent d'inversion de manière à ce qu'elle devienne un atout efficace. Ce procédé permet ainsi d'obtenir des agencements uniformes de systèmes de report de retenue, dont les éléments logiques uniformes utilisent, en général, une combinaison de paire de grilles récemment définie. Les éléments logiques (20) de paire de grilles permettent d'obtenir un nouveau signal P de propagation de report qui comprend un signal G redondant de génération de report, permettant ainsi de définir un nouveau signal I d'intégration de report (Ao). Le nouveau signal I d'intégration de report (Ao) et le signal G de génération de report (Bo) définissent une paire de signaux utilisés dans des niveaux de report successifs qui sont organisés de manière simplifiée.
EP96912409A 1996-03-11 1996-03-11 Elements logiques pour systemes entrelaces de report de retenue/retenue negative possedant un agencement uniforme Withdrawn EP0929862A4 (fr)

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US4882698A (en) * 1987-10-07 1989-11-21 Harris Corporation Cell based ALU with tree structured carry, inverting logic and balanced loading
US5043934A (en) * 1990-02-13 1991-08-27 Hewlett-Packard Company Lookahead adder with universal logic gates
US5235539A (en) * 1990-12-12 1993-08-10 Sun Microsystems, Inc. Method and apparatus for generating carry out signals

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