EP0964444A3 - Semiconducteurs ayant des zones dénudées - Google Patents

Semiconducteurs ayant des zones dénudées Download PDF

Info

Publication number
EP0964444A3
EP0964444A3 EP99108456A EP99108456A EP0964444A3 EP 0964444 A3 EP0964444 A3 EP 0964444A3 EP 99108456 A EP99108456 A EP 99108456A EP 99108456 A EP99108456 A EP 99108456A EP 0964444 A3 EP0964444 A3 EP 0964444A3
Authority
EP
European Patent Office
Prior art keywords
trench
region
substrate
oxygen concentration
reducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP99108456A
Other languages
German (de)
English (en)
Other versions
EP0964444A2 (fr
Inventor
Martin Schrems
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP0964444A2 publication Critical patent/EP0964444A2/fr
Publication of EP0964444A3 publication Critical patent/EP0964444A3/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/20—Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
EP99108456A 1998-06-09 1999-04-30 Semiconducteurs ayant des zones dénudées Ceased EP0964444A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93796 1987-09-04
US09/093,796 US6040211A (en) 1998-06-09 1998-06-09 Semiconductors having defect denuded zones

Publications (2)

Publication Number Publication Date
EP0964444A2 EP0964444A2 (fr) 1999-12-15
EP0964444A3 true EP0964444A3 (fr) 2004-11-10

Family

ID=22240774

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99108456A Ceased EP0964444A3 (fr) 1998-06-09 1999-04-30 Semiconducteurs ayant des zones dénudées

Country Status (6)

Country Link
US (1) US6040211A (fr)
EP (1) EP0964444A3 (fr)
JP (1) JP2000082804A (fr)
KR (1) KR100647940B1 (fr)
CN (1) CN1239317A (fr)
TW (1) TW418486B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6406982B2 (en) * 2000-06-05 2002-06-18 Denso Corporation Method of improving epitaxially-filled trench by smoothing trench prior to filling
JP2002184779A (ja) * 2000-12-13 2002-06-28 Shin Etsu Handotai Co Ltd アニールウェーハの製造方法及びアニールウェーハ
TW508696B (en) * 2001-11-06 2002-11-01 Nanya Technology Corp Method for etching of mask layer and passivation layer of metal contact windows
US6583024B1 (en) 2001-12-06 2003-06-24 Seh America, Inc. High resistivity silicon wafer with thick epitaxial layer and method of producing same
US20040259321A1 (en) * 2003-06-19 2004-12-23 Mehran Aminzadeh Reducing processing induced stress
CN100503755C (zh) * 2003-09-02 2009-06-24 永记造漆工业股份有限公司 可硬化且形成压花的涂料组成物
US7402487B2 (en) * 2004-10-18 2008-07-22 Infineon Technologies Richmond, Lp Process for fabricating a semiconductor device having deep trench structures
JP2006156973A (ja) * 2004-10-25 2006-06-15 Toyota Motor Corp 絶縁ゲート型半導体装置の製造方法
KR100668509B1 (ko) * 2005-06-10 2007-01-12 주식회사 하이닉스반도체 비대칭 스텝구조의 게이트를 갖는 반도체소자의 제조 방법
US8008107B2 (en) * 2006-12-30 2011-08-30 Calisolar, Inc. Semiconductor wafer pre-process annealing and gettering method and system for solar cell formation
US20130023097A1 (en) * 2011-07-14 2013-01-24 Purtell Robert J U-mos trench profile optimization and etch damage removal using microwaves
US10141413B2 (en) 2013-03-13 2018-11-27 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer strength by control of uniformity of edge bulk micro defects
US9064823B2 (en) * 2013-03-13 2015-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method for qualifying a semiconductor wafer for subsequent processing
KR102428659B1 (ko) * 2015-08-24 2022-08-04 삼성전자주식회사 반도체 소자의 제조 방법
KR102731054B1 (ko) * 2019-05-29 2024-11-15 삼성전자주식회사 집적회로 소자 및 그 제조 방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH107625A (ja) * 1996-06-06 1998-01-13 Sanfuku Kako Kofun Yugenkoshi シクロヘキシルアミンの製法
JPH1173728A (ja) * 1997-05-05 1999-03-16 Wea Mfg Inc チャネル毎に分解能が異なるマルチチャネルデジタル音声の記録および再生

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69233314T2 (de) * 1991-10-11 2005-03-24 Canon K.K. Verfahren zur Herstellung von Halbleiter-Produkten
KR960004443B1 (ko) * 1992-03-19 1996-04-03 삼성전자주식회사 커패시터를 갖는 반도체 장치 및 그 제조방법
US5573973A (en) * 1993-03-19 1996-11-12 National Semiconductor Corporation Integrated circuit having a diamond thin film trench arrangement as a component thereof and method
US5757063A (en) * 1994-03-25 1998-05-26 Kabushiki Kaisha Toshiba Semiconductor device having an extrinsic gettering film
US5786263A (en) * 1995-04-04 1998-07-28 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
US5827765A (en) * 1996-02-22 1998-10-27 Siemens Aktiengesellschaft Buried-strap formation in a dram trench capacitor
US5893735A (en) * 1996-02-22 1999-04-13 Siemens Aktiengesellschaft Three-dimensional device layout with sub-groundrule features
TW429478B (en) * 1997-08-29 2001-04-11 Toshiba Corp Semiconductor device and method for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH107625A (ja) * 1996-06-06 1998-01-13 Sanfuku Kako Kofun Yugenkoshi シクロヘキシルアミンの製法
JPH1173728A (ja) * 1997-05-05 1999-03-16 Wea Mfg Inc チャネル毎に分解能が異なるマルチチャネルデジタル音声の記録および再生

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
IWAI H ET AL: "COMPARISON OF INSTRINSIC GETTERING AND EPITAXIAL WAFERS IN TERMS OF SOFT ERROR ENDURANCE AND OTHER CHARACTERISTICS OF 64K BIT DYNAMIC RAM", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 31, no. 9, September 1984 (1984-09-01), pages 1149 - 1151, XP000835576, ISSN: 0018-9383 *
PATENT ABSTRACTS OF JAPAN vol. 0131, no. 81 (E - 750) 27 April 1989 (1989-04-27) *
PATENT ABSTRACTS OF JAPAN vol. 0134, no. 45 (E - 829) 6 October 1989 (1989-10-06) *

Also Published As

Publication number Publication date
JP2000082804A (ja) 2000-03-21
TW418486B (en) 2001-01-11
EP0964444A2 (fr) 1999-12-15
KR20000006001A (ko) 2000-01-25
CN1239317A (zh) 1999-12-22
KR100647940B1 (ko) 2006-11-17
US6040211A (en) 2000-03-21

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