Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N7/00—Television systems
  • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
  • H04N7/0105—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level using a storage device with different write and read speed

Definitions

• the invention relates to image and/or data signal processing.
• US-A-5,301,031 discloses a display apparatus using a matrix display panel, such as a liquid crystal panel, for converting the number of scanning lines to be displayed to a number that can be accommodated on a panel having a smaller number of scanning lines.
• the apparatus includes a control circuit which produces control signals in synchronism with the input video signal, horizontal and vertical scanning circuits each including a shift register operated by a control circuit, and a display panel which is formed of a matrix arrangement of pixels that are driven selectively by the scanning circuits.
• the apparatus further includes a circuit which halts the operation of the vertical shift register at a certain interval within the effective scanning period of the vertical scanning circuit so as to extract vertical shift clocks, thereby removing the vertical shift clocks within the effective display period of the video signal, thereby periodically extracting scanning lines. In sum, every sixth line is skipped to display PAL on an NTSC matrix display.
• a first aspect of the invention provides an image and/or data signal processing method as defined in claim 1.
• a second aspect of the invention provides an image and/or data signal processing device as defined in claim 4.
• a third aspect of the invention provides multi-media apparatus as defined in claim 7.
• a fourth aspect of the invention provides television receiver as defined in claim 9.
• Advantageous embodiments are defined in the dependent claims.
• input image and/or data signals having an input frequency and a number of active input lines are written into a buffer at the input frequency, while output image and/or data signals are read from the buffer at an output frequency other than the input frequency thereby ensuring that the output image and/or data signals have a number of active output lines other than the number of active input lines.
• the buffer consist of a single line memory for each color.
• the invention is used in an interface board designed for connecting a Fujitsu 42" Plasma Display Panel to a normal small signal panel of a TV set.
• the display panel has 852h x 480v resolution.
• Each 1.08 mm x 1.08 mm square pixel consists of 3 sub-pixels: R,G,B.
• Data is transferred over 3 synchronous 8-bit wide data-busses, 1 for each color, with only a single accompanying clock signal. Start of line and field is signalled by synchronous H-sync and V-sync lines.
• the display is connected to a regular picture source, as if it were a CRT.
• a standard VGA cable is used for this connection. This transfers analog RGB signals plus H- and V-sync.
• At least one VGA mode must be displayed: 640h x 480v x 16M colors @ 60 Hz.
• the picture will be displayed on the center part of the panel.
• the picture In order to minimize the effects of phosphor burn-in, the picture must be padded with 212 grey pixels, to be divided over the left and right side-panels.
• the 640 source pixels are sampled with a 39.7 ns clock period. 212 grey pixels need to be added and the total of 852 pixels must be transferred to the panel within 31.8 ⁇ s. This requires a clock period ⁇ 37.3 ns, so again a video line memory will be essential to get a shorter clock period.
• This line memory buffer receives the image signal with horizontal and vertical flybacks at an input clock rate, and supplies only the active pixels at an output clock rate which is lower than the input clock rate and within the range the display can handle.
• the VGA input is specified only at 640h x 480v @ 60 Hz and possibly at 852h x 480v @ 60 Hz as well. There will always be somebody who wants to connect e.g. a 800h x 600v signal or a > > 60 Hz field frequency. Such signals will have a line period ⁇ 29 ⁇ s or a field period ⁇ 16.5 ms or a line number >_ 480. No proper operation will be specified in such case, the customer will be asked to adjust his computer to the only mode that is supported. It would be nice though, if he could still see on the display what he is doing when he is trying to set his video driver to the proper mode.
• Each color channel contains an A/D convertor and a video line memory.
• the A/D convertor connects to the input side of the memory, the output side connects to the display panel.
• Each line memory has 2 clock inputs, so it may be used to separate 2 clock domains:
• the output side is operated on a free-running clock, the clock frequency is always 32.000 Ms/s.
• the input clock frequency is optimized to display the correct amount of visible video signal.
• the output clock frequency is low enough to satisfy the display requirements and high enough to always transfer all the video samples within a line period.
• the clock PLL for the input side of the display interface has a wide locking range: it now does 9 to 45 Ms/s.
• the display is operated from the fixed 32 Ms/s clock, this is generated from a crystal oscillator.
• the display line period is limited between 28.00 ⁇ s (896 clock periods) and 34.375 ⁇ s (1100 clock periods). If the input line period is shorter than 28.00 ⁇ s, the display will free-run at 28.00 ⁇ s. If the input line period is longer than 34.375 ⁇ s the display will free-run at 34.375 ⁇ s. These times are within the display spec.
• the number of lines per field is also limited, between 429 and 675 lines per field. Apart from no-sync conditions, these limits are never met in practise. If for example an 800h x 600v @ 60 Hz SVGA signal is connected, the line sync period will be 26.4 ⁇ s. The input PLL will follow this. The output PLL will not follow this but it will free-run at 28.0 ⁇ s. Thus, synchronisation between the input side (write) and output side (read) of the line memories will be lost. The memory will perform more write than read operations. Periodically, the (period-limited) read process will be overtaken by the faster write process. As a result, some lines of video information will be deleted.
• the deleted lines will be spread evenly over the picture height and there will always be different lines deleted because of the lost line-synchronisation.
• the user will see an unstable but readable picture. This is the cheapest form of vertical sample rate reduction possible. It is the nearest neighbor algorithm for sample deletion. All the information from the original video signal will be there sometimes. At least this mode of operation allows the user some visual control over his computer until he has adjusted it to the only proper video mode: 640h x 480v @ 60 Hz (and any number of colors).
• a primary aspect of the invention can be summarized as follows. All matrix displays share a problem that normal CRT do not have: they have a fixed resolution. All input formats that are not exactly right will have to be converted in some way to fit them into the resolution of the panel. For instance, PAL resolution (576 active lines) will have to be converted to 480 lines. In the flat TV this is done by the feature box (linear interpolation). However, some sources are not processed by the feature box. For instance, all VGA sources are inserted directly into the TDA4780 and bypass the feature box entirely. If the input format is not correct, some measures have to be taken. Linear interpolation (one of the cheapest conversions) is already very bulky in electronics, and expensive. Line dropping will lead to pixels in the input signal that are never visible on the output. The trick should be designing an algorithm that is cheap, easy to implement and shows all data in the input signal, preferably without distortions.
• the solution is based on a very simple conversion scheme.
• the line memories are fed with all the input lines and pixels with a line frequency of f_line_in. If we read the line memories with a much lower frequency, the write pointer will be asynchronous to the read pointer, and every now and then the write pointer will overtake the read pointer. If for instance the read pointer reads at 0.5 * f_line_in, the write pointer will overtake the read pointer every line. If the read pointer is overtaken by the read pointer, the output data will be partly of line N (before being overtaken) and partly of line N+l (after being overtaken). In the process, fewer lines will be displayed by the output clock.
• this invention is not only suitable for displaying an SVGA signal on a VGA monitor, but also for displaying on any other display, any other signal having a lower or higher number of lines than the display can handle.
• the only costs are those of one line memory per color channel, while these costs may be about zero if these line memories are already there for some other purpose (like removing the horizontal and vertical flybacks from an image so that only the active pixels are applied to the display at a pixel frequency that the display can handle) .
• the figure shows an embodiment of a television receiver in accordance with the present invention. Television signals received by an antenna A are applied to a tuner T.
• An output of the tuner T is connected to a small signal processor unit SSP for carrying several picture signal processing functions irrelevant to the present invention.
• the small signal processor unit SSP has a VGA input for receiving VGA signals.
• the small signal processor unit SSP supplies input red, green and blue color signals Ri, Gi, Bi to dual-port
• Synchronization signals from the tuner T are applied to a write clock circuit WCK for generating a write clock signal Ci and an input horizontal sync signal Hi.
• a read clock circuit RCK generates a read clock signal Co and an output horizontal sync signal Ho.
• the read clock Co is preferably formed by a fixed crystal clock.
• the output horizontal sync signal Ho is free-running at a suitably chosen frequency if the input horizontal sync signal Hi is outside a range as defined above: 896-1100 pixels (input clock pulses Ci) per line period.
• the suitably chosen frequency corresponds either to the maximum (minimum) allowable number of 1100 (896), or to a suitably chosen number somewhere within this range so that the most pleasant output picture is obtained.
• the ratio between Hi and Ho determines the conversion ratio.
• the read clock RCK is reset at each input vertical sync pulse to make the picture stable and slightly more pleasant to watch.
• the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims.
• any reference signs placed between parentheses shall not be construed as limiting the claim.
• the invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware.

Landscapes

• Engineering & Computer Science (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Controls And Circuits For Display Device (AREA)
• Transforming Electric Information Into Light Information (AREA)
• Image Processing (AREA)

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• 1999
  • 1999-02-22 EP EP99902772A patent/EP0981904A2/de not_active Withdrawn
  • 1999-02-22 JP JP54553699A patent/JP2001525157A/ja active Pending
  • 1999-02-22 WO PCT/IB1999/000312 patent/WO1999046935A2/en not_active Ceased

Non-Patent Citations (1)

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