EP1246241A2 - Boítier semi-conducteur - Google Patents

Boítier semi-conducteur Download PDF

Info

Publication number
EP1246241A2
EP1246241A2 EP20020251806 EP02251806A EP1246241A2 EP 1246241 A2 EP1246241 A2 EP 1246241A2 EP 20020251806 EP20020251806 EP 20020251806 EP 02251806 A EP02251806 A EP 02251806A EP 1246241 A2 EP1246241 A2 EP 1246241A2
Authority
EP
European Patent Office
Prior art keywords
interposer
wiring layer
semiconductor chip
light blocking
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20020251806
Other languages
German (de)
English (en)
Other versions
EP1246241A3 (fr
Inventor
Mitsuru I.P.D. Toshiba Corporation Oida
Masatoshi I.P.D. Toshiba Corporation Fukuda
Yasuhiro I.P.D. Toshiba Corporation Koshio
Hiroshi I.P.D. Toshiba Corporation Funakura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of EP1246241A2 publication Critical patent/EP1246241A2/fr
Publication of EP1246241A3 publication Critical patent/EP1246241A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/657—Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H10W74/473—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins containing a filler
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a semiconductor package, and particularly, to a technique of preventing the generation of leak current due to photoexcitation in a thin semiconductor package.
  • a earlier semiconductor package is thinned by (1) thinning an interposer of the package and by (2) thinning a resin mold of the package.
  • An example of a semiconductor package thinned by the techniques (1) and (2) is a Thin Quad Outline Nonleaded (TQON) package.
  • the TQON package employs a flip-chip connection process and guarantees a package thickness of 0.5 mm or thinner.
  • Figure 1 is a sectional view showing a semiconductor package according to a related art
  • Fig. 2 is a plan view showing a wiring layer formed on an interposer of the package of Fig. 1.
  • the wiring layer 48 is formed on the interposer 40.
  • a semiconductor chip 10 is mounted upside down and connected to the wiring layer 48 by flip-chip contacts 20.
  • the interposer 40, the wiring layer 48, and the contacts 20 are sealed with an underfill material 30.
  • the chip 10 and the underfill material 30 are sealed with a resin mold 60.
  • the wiring layer 48 includes conductors that are spaced widely apart from one another.
  • the thin package according to the related art has a problem (1) that the interposer allows the transmission of light which optically excites semiconductor elements in the semiconductor chip and generates leakage current causing malfunctions.
  • the related art fabricates the interposer from a resin substrate made of, for example, glass epoxy resin, Bismaleimide Triazine (BT) resin, or polyimide (PI) resin, instead of a metal lead frame.
  • the related art also has a problem (2) that the resin mold on the semiconductor chip allows the transmission of light, in particular, light of 780 nm or longer in wavelength which optically excites the semiconductor elements and generates leakage current causing malfunctions.
  • the problem (2) occurs when the resin mold on the semiconductor chip is excessively thinned to reduce the thickness of the package.
  • a semiconductor package includes an interposer, a wiring layer formed on the interposer, a semiconductor chip electrically connected to the wiring layer, and a resin mold protecting the wiring layer and semiconductor chip.
  • the wiring layer includes conductors formed adjacent to each other at intervals that cause no short circuit among the conductors.
  • the package is provided with a light blocking layer formed in areas on the interposer where the conductors are not present.
  • the semiconductor package according to the first embodiment includes (a) an interposer 40, (b) a wiring layer 50 containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer 50 covering a given area of the interposer 40, to block light from passing through the given area, (c) a light blocking layer 80 covering a no-wiring area of the interposer 40 not covered by the wiring layer 50, to block light from passing through the no-wiring area, (d) a semiconductor chip 10 electrically connected to the wiring layer 50, and (e) a resin mold 62 sealing the wiring layer 50, the light blocking layer 80, and the chip 10.
  • An underfill material 30 seals flip-chip contacts 20 that electrically connect the chip 10, which is mounted upside down, to the wiring layer 50.
  • the underfill material 30 improves the connection reliability of the contacts 20.
  • the resin mold 62 may contain light blocking components such as carbon black powder and metal oxide powder. Even if the resin mold 62 is thinned to about 0.100 mm, the light blocking components in the resin mold 62 allow the transmittance of only about 0 to 1% of light of 780 nm or longer in wavelength.
  • the interposer 40 is made of, for example, organic material such as BT resin or PI resin.
  • the wiring layer 50 is made of light blocking conductive material such as copper (Cu), aluminum (Al), and copper-nickel (Cu-Ni) alloy.
  • the wiring layer 50 electrically connects terminals of chip 10 to external terminals 70.
  • the light blocking layer 80 is formed where the wiring layer 50 is not present, for example, under the chip 10 and at the corners of the package.
  • the light blocking layer 80 is made of light blocking material which may be conductive or nonconductive. Simultaneously forming the wiring layer 50 and light blocking layer 80 reduces the number of processes. In this regard, it is preferable to simultaneously form the light blocking layer 80 and wiring layer 50 from the same material.
  • the conductors in the wiring layer 50 cover a large part of the interposer 40 and are formed adjacent to each other at intervals that cause no short circuit among the conductors.
  • the interval between the conductors must be in the range of, for example, 0.010 to 0.100 mm.
  • wider intervals are preferred between the conductors. Wider intervals, however, increase the risk of light permeation.
  • the light wavelengths that must be blocked vary, and depending on the light wavelengths to be blocked, the adequate interval changes.
  • an interval between adjacent conductors in the wiring layer 50 is, for example, about 0.050 mm.
  • the light blocking layer 80 consists of a light blocking layer 80a and light blocking layers 80b formed where no wiring layer is present, i.e., under the chip 10 and at the corners of the package.
  • the interposer 40 is made of a polyimide tape in this example.
  • the semiconductor chip 10 is set in an upside-down configuration, and the wiring layer 50 and chip 10 are connected to each other by the contacts 20.
  • the chip 10 and wiring layer 50 are sealed with the resin mold 62, to complete the semiconductor package.
  • the semiconductor package according to the first embodiment differs from the related art in that the conductors in the wiring layer 50 are arranged adjacent to each other at intervals that cause no short circuit among the conductors and in that the light blocking layer 80 is added.
  • the conductors are arranged adjacent to each other at intervals as close as possible without causing short circuit among the conductors, in order to prevent light from passing through gaps between the conductors.
  • the light blocking layer 80 formed in areas where there is no wiring layer prevents light from reaching the semiconductor chip 10 through the no-wiring area.
  • the semiconductor package according to the first embodiment differs from the related art in that the resin mold 62 contains light blocking components. Adding light blocking components to the resin mold 62 prevents light from passing through the resin mold 62 even if the resin mold 62 is thin.
  • Blocking light from reaching the semiconductor chip 10 prevents semiconductor elements in the chip 10 from being optically excited to generate leakage current, thereby preventing the malfunctions of the elements.
  • a resin mold 60 contains no light blocking components. Instead, a light blocking layer 82 is formed on the semiconductor chip 10.
  • the light blocking layer 82 is formed by, for example, a spatter deposition method or an electroless plating method, to have a thickness in the range of, for example, 100 to 10000 angstroms.
  • the light blocking layer 82 may contain, for example, gold (Au), nickel (Ni), or carbon (C).
  • the resin mold 60 according to the second embodiment contains no light blocking components, and therefore, is unable to block light.
  • the second embodiment forms the light blocking layer 82 on the chip 10, to block light passing through the resin mold 60 from reaching the chip 10.
  • the second embodiment forms a light blocking layer 80 between the chip 10 and an interposer 40, to prevent light passing through the interposer 40 from reaching the chip 10.
  • Fig. 6A to 6F are plan views showing various shapes of wiring layers and light blocking layers on interposers in semiconductor packages formed according to the first or second embodiments.
  • a numeral 20 is a flip-chip contact
  • 50 is a wiring layer
  • 70 is an external connection terminal
  • 80 is a light blocking layer.
  • Fig. 6A two (upper left and upper right) corners among the four corners of the interposer are covered with light blocking layers 80b, and the remaining (lower left and lower right) corners are covered with conductors 50a of the wiring layer 50.
  • Fig. 6C the four corners of the interposer are covered with conductors of the wiring layer 50 like Fig. 6B.
  • some conductors for example the upper right conductor 50b
  • Fig. 6C no conductor is provided with a plurality of flip-chip contacts.
  • some conductors of a wiring layer in a semiconductor package according to an embodiment of the present invention may each have two or more contacts connected to a semiconductor chip.
  • each side of the interposer is provided with five external connection terminals 70.
  • each side of the interposers are provided with seven external connection terminals 70.
  • the number of external connection terminals 70 on a side of an interposer according to the present invention is optional and is not limited to 5 or 7.
  • external connection terminals 70 are arranged along each edge of each interposer and at intermediate positions between the edges of the interposer and semiconductor chip. More precisely, the external connection terminals 70a are arranged along each edge of each interposer, and the external connection terminals 70b are arranged at intermediate positions between the edges of the interposer and the semiconductor chip.
  • an end of a conductor (for example, 50c) at the edge of the semiconductor chip branches into two.
  • the semiconductor package according to the third embodiment includes the interposer 40, the wiring layer 54 and the light blocking layer 84 formed on the interposer 40, the semiconductor chip 10, the metal wires 90 electrically connecting the semiconductor chip 10 to the wiring layer 54, and the resin mold 64 protecting the semiconductor chip 10, the wiring layer 54, and the metal wires 90.
  • the semiconductor chip 10 is mounted in a face-up position and is connected to the wiring layer 54 by the metal wires 90.
  • the light blocking layer 84 under the chip 10 is larger than the chip 10.
  • the third embodiment further nesures the prevention of light passing through the interposer 40 from reaching the chip 10. If the light blocking layer 84 is smaller than the chip 10, light passing through gaps between the wiring layer 54 and the light blocking layer 84 may directly contact with the chip 10. According to the third embodiment, the light blocking layer 84 under the chip 10 is larger than the chip 10, and therefore, light passing through gaps between the wiring layer 54 and the light blocking layer 84 never directly reaches the chip 10 because the chip 10 is not present right above the gaps.
  • the third embodiment adds light blocking components to the resin mold 64, to block light from passing through the resin mold 64 to the chip 10.
  • the semiconductor package according to any one of the embodiments of the present invention minimizes the gaps between conductors of a wiring layer on the interposer of the package and arranges a light blocking layer in areas where the wiring layer is not present, to block light from passing through the interposer, thereby preventing leakage current from being generated by semiconductor elements in the package. This prevents malfunction and reduces power consumption of the package.

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
EP20020251806 2001-03-30 2002-03-13 Boítier semi-conducteur Withdrawn EP1246241A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001102061 2001-03-30
JP2001102061A JP4212255B2 (ja) 2001-03-30 2001-03-30 半導体パッケージ

Publications (2)

Publication Number Publication Date
EP1246241A2 true EP1246241A2 (fr) 2002-10-02
EP1246241A3 EP1246241A3 (fr) 2005-05-18

Family

ID=18955305

Family Applications (1)

Application Number Title Priority Date Filing Date
EP20020251806 Withdrawn EP1246241A3 (fr) 2001-03-30 2002-03-13 Boítier semi-conducteur

Country Status (6)

Country Link
US (1) US7148529B2 (fr)
EP (1) EP1246241A3 (fr)
JP (1) JP4212255B2 (fr)
KR (1) KR100731332B1 (fr)
CN (1) CN1210791C (fr)
TW (1) TW538485B (fr)

Cited By (1)

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EP1246241A3 (fr) 2005-05-18
KR20020077198A (ko) 2002-10-11
CN1210791C (zh) 2005-07-13
TW538485B (en) 2003-06-21
JP4212255B2 (ja) 2009-01-21
US7148529B2 (en) 2006-12-12
JP2002299498A (ja) 2002-10-11
CN1379467A (zh) 2002-11-13
US20020140062A1 (en) 2002-10-03

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